1
2#ifndef NVE4_COMPUTE_H
3#define NVE4_COMPUTE_H
4
5#include "nvc0/nve4_compute.xml.h"
6
7struct nve4_cp_launch_desc
8{
9   u32 unk0[8];
10   u32 entry;
11   u32 unk9[2];
12   u32 unk11_0      : 30;
13   u32 linked_tsc   : 1;
14   u32 unk11_31     : 1;
15   u32 griddim_x    : 31;
16   u32 unk12        : 1;
17   u16 griddim_y;
18   u16 griddim_z;
19   u32 unk14[3];
20   u16 shared_size; /* must be aligned to 0x100 */
21   u16 unk17;
22   u16 unk18;
23   u16 blockdim_x;
24   u16 blockdim_y;
25   u16 blockdim_z;
26   u32 cb_mask      : 8;
27   u32 unk20_8      : 21;
28   u32 cache_split  : 2;
29   u32 unk20_31     : 1;
30   u32 unk21[8];
31   struct {
32      u32 address_l;
33      u32 address_h : 8;
34      u32 reserved  : 7;
35      u32 size      : 17;
36   } cb[8];
37   u32 local_size_p : 20;
38   u32 unk45_20     : 7;
39   u32 bar_alloc    : 5;
40   u32 local_size_n : 20;
41   u32 unk46_20     : 4;
42   u32 gpr_alloc    : 8;
43   u32 cstack_size  : 20;
44   u32 unk47_20     : 12;
45   u32 unk48[16];
46};
47
48struct gp100_cp_launch_desc
49{
50   u32 unk0[8];
51   u32 entry;
52   u32 unk9[2];
53   u32 unk11_0      : 30;
54   u32 linked_tsc   : 1;
55   u32 unk11_31     : 1;
56   u32 griddim_x    : 31;
57   u32 unk12        : 1;
58   u16 griddim_y;
59   u16 unk13;
60   u16 griddim_z;
61   u16 unk14;
62   u32 unk15[2];
63   u32 shared_size  : 18;
64   u32 unk17        : 14;
65   u16 unk18;
66   u16 blockdim_x;
67   u16 blockdim_y;
68   u16 blockdim_z;
69   u32 cb_mask      : 8;
70   u32 unk20        : 24;
71   u32 unk21[8];
72   u32 local_size_p : 24;
73   u32 unk29        : 3;
74   u32 bar_alloc    : 5;
75   u32 local_size_n : 24;
76   u32 gpr_alloc    : 8;
77   u32 cstack_size  : 24;
78   u32 unk31        : 8;
79   struct {
80      u32 address_l;
81      u32 address_h : 17;
82      u32 reserved  : 2;
83      u32 size_sh4  : 13;
84   } cb[8];
85   u32 unk48[16];
86};
87
88static inline void
89nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
90{
91   memset(desc, 0, sizeof(*desc));
92
93   desc->unk0[7]  = 0xbc000000;
94   desc->unk11_0  = 0x04014000;
95   desc->unk47_20 = 0x300;
96}
97
98static inline void
99nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
100                           unsigned index,
101                           struct nouveau_bo *bo,
102                           uint32_t base, uint32_t size)
103{
104   uint64_t address = bo->offset + base;
105
106   assert(index < 8);
107   assert(!(base & 0xff));
108
109   desc->cb[index].address_l = address;
110   desc->cb[index].address_h = address >> 32;
111   desc->cb[index].size = size;
112
113   desc->cb_mask |= 1 << index;
114}
115
116static inline void
117gp100_cp_launch_desc_init_default(struct gp100_cp_launch_desc *desc)
118{
119   memset(desc, 0, sizeof(*desc));
120
121   desc->unk0[4]  = 0x40;
122   desc->unk11_0  = 0x04014000;
123}
124
125static inline void
126gp100_cp_launch_desc_set_cb(struct gp100_cp_launch_desc *desc,
127                            unsigned index,
128                            struct nouveau_bo *bo,
129                            uint32_t base, uint32_t size)
130{
131   uint64_t address = bo->offset + base;
132
133   assert(index < 8);
134   assert(!(base & 0xff));
135
136   desc->cb[index].address_l = address;
137   desc->cb[index].address_h = address >> 32;
138   desc->cb[index].size_sh4 = DIV_ROUND_UP(size, 16);
139
140   desc->cb_mask |= 1 << index;
141}
142
143struct nve4_mp_trap_info {
144   u32 lock;
145   u32 pc;
146   u32 trapstat;
147   u32 warperr;
148   u32 tid[3];
149   u32 ctaid[3];
150   u32 pad028[2];
151   u32 r[64];
152   u32 flags;
153   u32 pad134[3];
154   u32 s[0x3000];
155};
156
157#endif /* NVE4_COMPUTE_H */
158