1/* Author(s):
2 *  Alyssa Rosenzweig
3 *
4 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#define OP_IS_STORE_VARY(op) (\
26		op == midgard_op_store_vary_16 || \
27		op == midgard_op_store_vary_32 \
28	)
29
30#define OP_IS_STORE(op) (\
31                OP_IS_STORE_VARY(op) || \
32                op == midgard_op_store_cubemap_coords \
33	)
34
35#define OP_IS_MOVE(op) ( \
36                op == midgard_alu_op_fmov || \
37                op == midgard_alu_op_imov \
38        )
39
40/* ALU control words are single bit fields with a lot of space */
41
42#define ALU_ENAB_VEC_MUL  (1 << 17)
43#define ALU_ENAB_SCAL_ADD  (1 << 19)
44#define ALU_ENAB_VEC_ADD  (1 << 21)
45#define ALU_ENAB_SCAL_MUL  (1 << 23)
46#define ALU_ENAB_VEC_LUT  (1 << 25)
47#define ALU_ENAB_BR_COMPACT (1 << 26)
48#define ALU_ENAB_BRANCH   (1 << 27)
49
50/* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
51
52/* Denotes an opcode that takes a vector input with a fixed-number of
53 * channels, but outputs to only a single output channel, like dot products.
54 * For these, to determine the effective mask, this quirk can be set. We have
55 * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
56 * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
57 * make sense (since then why are we quirked?), so that corresponds to "no
58 * count set" */
59
60#define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
61#define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
62
63/* For instructions that take a single argument, normally the first argument
64 * slot is used for the argument and the second slot is a dummy #0 constant.
65 * However, there are exceptions: instructions like fmov store their argument
66 * in the _second_ slot and store a dummy r24 in the first slot, designated by
67 * QUIRK_FLIPPED_R24 */
68
69#define QUIRK_FLIPPED_R24 (1 << 2)
70
71/* Is the op commutative? */
72#define OP_COMMUTES (1 << 3)
73
74/* Vector-independant shorthands for the above; these numbers are arbitrary and
75 * not from the ISA. Convert to the above with unit_enum_to_midgard */
76
77#define UNIT_MUL 0
78#define UNIT_ADD 1
79#define UNIT_LUT 2
80
81/* 4-bit type tags */
82
83#define TAG_TEXTURE_4 0x3
84#define TAG_LOAD_STORE_4 0x5
85#define TAG_ALU_4 0x8
86#define TAG_ALU_8 0x9
87#define TAG_ALU_12 0xA
88#define TAG_ALU_16 0xB
89
90/* Special register aliases */
91
92#define MAX_WORK_REGISTERS 16
93
94/* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
95#define REGISTER_UNIFORMS 24
96
97#define REGISTER_UNUSED 24
98#define REGISTER_CONSTANT 26
99#define REGISTER_VARYING_BASE 26
100#define REGISTER_OFFSET 27
101#define REGISTER_TEXTURE_BASE 28
102#define REGISTER_SELECT 31
103
104/* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
105 * constant. UNUSED_1 encoded as REGISTER_UNUSED */
106
107#define SSA_UNUSED_0 0
108#define SSA_UNUSED_1 -2
109
110#define SSA_FIXED_SHIFT 24
111#define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
112#define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
113#define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
114
115/* Swizzle support */
116
117#define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
118#define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
119#define COMPONENT_X 0x0
120#define COMPONENT_Y 0x1
121#define COMPONENT_Z 0x2
122#define COMPONENT_W 0x3
123
124/* See ISA notes */
125
126#define LDST_NOP (3)
127
128/* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
129 * implemented on some subset of these units (or occassionally all of them).
130 * This table encodes a bit mask of valid units for each opcode, so the
131 * scheduler can figure where to plonk the instruction. */
132
133/* Shorthands for each unit */
134#define UNIT_VMUL ALU_ENAB_VEC_MUL
135#define UNIT_SADD ALU_ENAB_SCAL_ADD
136#define UNIT_VADD ALU_ENAB_VEC_ADD
137#define UNIT_SMUL ALU_ENAB_SCAL_MUL
138#define UNIT_VLUT ALU_ENAB_VEC_LUT
139
140/* Shorthands for usual combinations of units */
141
142#define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
143#define UNITS_ADD (UNIT_VADD | UNIT_SADD)
144#define UNITS_MOST (UNITS_MUL | UNITS_ADD)
145#define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
146#define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
147#define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
148#define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
149
150/* Table of mapping opcodes to accompanying properties relevant to
151 * scheduling/emission/etc */
152
153static struct {
154        const char *name;
155        unsigned props;
156} alu_opcode_props[256] = {
157        [midgard_alu_op_fadd]		 = {"fadd", UNITS_ADD | OP_COMMUTES},
158        [midgard_alu_op_fmul]		 = {"fmul", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
159        [midgard_alu_op_fmin]		 = {"fmin", UNITS_MUL | UNITS_ADD | OP_COMMUTES},
160        [midgard_alu_op_fmax]		 = {"fmax", UNITS_MUL | UNITS_ADD | OP_COMMUTES},
161        [midgard_alu_op_imin]		 = {"imin", UNITS_MOST | OP_COMMUTES},
162        [midgard_alu_op_imax]		 = {"imax", UNITS_MOST | OP_COMMUTES},
163        [midgard_alu_op_umin]		 = {"umin", UNITS_MOST | OP_COMMUTES},
164        [midgard_alu_op_umax]		 = {"umax", UNITS_MOST | OP_COMMUTES},
165        [midgard_alu_op_fmov]		 = {"fmov", UNITS_ALL | QUIRK_FLIPPED_R24},
166        [midgard_alu_op_fround]          = {"fround", UNITS_ADD},
167        [midgard_alu_op_froundeven]      = {"froundeven", UNITS_ADD},
168        [midgard_alu_op_ftrunc]          = {"ftrunc", UNITS_ADD},
169        [midgard_alu_op_ffloor]		 = {"ffloor", UNITS_ADD},
170        [midgard_alu_op_fceil]		 = {"fceil", UNITS_ADD},
171        [midgard_alu_op_ffma]		 = {"ffma", UNIT_VLUT},
172
173        /* Though they output a scalar, they need to run on a vector unit
174         * since they process vectors */
175        [midgard_alu_op_fdot3]		 = {"fdot3", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
176        [midgard_alu_op_fdot3r]		 = {"fdot3r", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
177        [midgard_alu_op_fdot4]		 = {"fdot4", UNIT_VMUL | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
178
179        /* Incredibly, iadd can run on vmul, etc */
180        [midgard_alu_op_iadd]		 = {"iadd", UNITS_MOST | OP_COMMUTES},
181        [midgard_alu_op_iabs]		 = {"iabs", UNITS_ADD},
182        [midgard_alu_op_isub]		 = {"isub", UNITS_MOST},
183        [midgard_alu_op_imul]		 = {"imul", UNITS_MUL | OP_COMMUTES},
184        [midgard_alu_op_imov]		 = {"imov", UNITS_MOST | QUIRK_FLIPPED_R24},
185
186        /* For vector comparisons, use ball etc */
187        [midgard_alu_op_feq]		 = {"feq", UNITS_MOST | OP_COMMUTES},
188        [midgard_alu_op_fne]		 = {"fne", UNITS_MOST | OP_COMMUTES},
189        [midgard_alu_op_fle]		 = {"fle", UNITS_MOST},
190        [midgard_alu_op_flt]		 = {"flt", UNITS_MOST},
191        [midgard_alu_op_ieq]		 = {"ieq", UNITS_MOST | OP_COMMUTES},
192        [midgard_alu_op_ine]		 = {"ine", UNITS_MOST | OP_COMMUTES},
193        [midgard_alu_op_ilt]		 = {"ilt", UNITS_MOST},
194        [midgard_alu_op_ile]		 = {"ile", UNITS_MOST},
195        [midgard_alu_op_ult]		 = {"ult", UNITS_MOST},
196        [midgard_alu_op_ule]		 = {"ule", UNITS_MOST},
197
198        [midgard_alu_op_icsel]		 = {"icsel", UNITS_ADD},
199        [midgard_alu_op_fcsel_i]	 = {"fcsel_i", UNITS_ADD},
200        [midgard_alu_op_fcsel]		 = {"fcsel", UNITS_ADD | UNIT_SMUL},
201
202        [midgard_alu_op_frcp]		 = {"frcp", UNIT_VLUT},
203        [midgard_alu_op_frsqrt]		 = {"frsqrt", UNIT_VLUT},
204        [midgard_alu_op_fsqrt]		 = {"fsqrt", UNIT_VLUT},
205        [midgard_alu_op_fpow_pt1]	 = {"fpow_pt1", UNIT_VLUT},
206        [midgard_alu_op_fexp2]		 = {"fexp2", UNIT_VLUT},
207        [midgard_alu_op_flog2]		 = {"flog2", UNIT_VLUT},
208
209        [midgard_alu_op_f2i]		 = {"f2i", UNITS_ADD},
210        [midgard_alu_op_f2u]		 = {"f2u", UNITS_ADD},
211        [midgard_alu_op_f2u8]		 = {"f2u8", UNITS_ADD},
212        [midgard_alu_op_i2f]		 = {"i2f", UNITS_ADD},
213        [midgard_alu_op_u2f]		 = {"u2f", UNITS_ADD},
214
215        [midgard_alu_op_fsin]		 = {"fsin", UNIT_VLUT},
216        [midgard_alu_op_fcos]		 = {"fcos", UNIT_VLUT},
217
218        /* XXX: Test case where it's right on smul but not sadd */
219        [midgard_alu_op_iand]		 = {"iand", UNITS_MOST | OP_COMMUTES},
220        [midgard_alu_op_iandnot]         = {"iandnot", UNITS_MOST},
221
222        [midgard_alu_op_ior]		 = {"ior", UNITS_MOST | OP_COMMUTES},
223        [midgard_alu_op_iornot]		 = {"iornot", UNITS_MOST | OP_COMMUTES},
224        [midgard_alu_op_inor]		 = {"inor", UNITS_MOST | OP_COMMUTES},
225        [midgard_alu_op_ixor]		 = {"ixor", UNITS_MOST | OP_COMMUTES},
226        [midgard_alu_op_inxor]		 = {"inxor", UNITS_MOST | OP_COMMUTES},
227        [midgard_alu_op_iclz]		 = {"iclz", UNITS_ADD},
228        [midgard_alu_op_ibitcount8]	 = {"ibitcount8", UNITS_ADD},
229        [midgard_alu_op_inand]		 = {"inand", UNITS_MOST},
230        [midgard_alu_op_ishl]		 = {"ishl", UNITS_ADD},
231        [midgard_alu_op_iasr]		 = {"iasr", UNITS_ADD},
232        [midgard_alu_op_ilsr]		 = {"ilsr", UNITS_ADD},
233
234        [midgard_alu_op_fball_eq]	 = {"fball_eq", UNITS_VECTOR | OP_COMMUTES},
235        [midgard_alu_op_fbany_neq]	 = {"fbany_neq", UNITS_VECTOR | OP_COMMUTES},
236        [midgard_alu_op_iball_eq]	 = {"iball_eq", UNITS_VECTOR | OP_COMMUTES},
237        [midgard_alu_op_iball_neq]	 = {"iball_neq", UNITS_VECTOR | OP_COMMUTES},
238        [midgard_alu_op_ibany_eq]	 = {"ibany_eq", UNITS_VECTOR | OP_COMMUTES},
239        [midgard_alu_op_ibany_neq]	 = {"ibany_neq", UNITS_VECTOR | OP_COMMUTES},
240
241        /* These instructions are not yet emitted by the compiler, so
242         * don't speculate about units yet */
243        [midgard_alu_op_ishladd]        = {"ishladd", 0},
244
245        [midgard_alu_op_uball_lt]       = {"uball_lt", 0},
246        [midgard_alu_op_uball_lte]      = {"uball_lte", 0},
247        [midgard_alu_op_iball_lt]       = {"iball_lt", 0},
248        [midgard_alu_op_iball_lte]      = {"iball_lte", 0},
249        [midgard_alu_op_ubany_lt]       = {"ubany_lt", 0},
250        [midgard_alu_op_ubany_lte]      = {"ubany_lte", 0},
251        [midgard_alu_op_ibany_lt]       = {"ibany_lt", 0},
252        [midgard_alu_op_ibany_lte]      = {"ibany_lte", 0},
253
254        [midgard_alu_op_freduce]        = {"freduce", 0},
255        [midgard_alu_op_bball_eq]       = {"bball_eq", 0 | OP_COMMUTES},
256        [midgard_alu_op_bbany_neq]      = {"bball_eq", 0 | OP_COMMUTES},
257        [midgard_alu_op_fatan2_pt1]     = {"fatan2_pt1", 0},
258        [midgard_alu_op_fatan_pt2]      = {"fatan_pt2", 0},
259};
260
261/* Is this opcode that of an integer (regardless of signedness)? Instruction
262 * names authoritatively determine types */
263
264static bool
265midgard_is_integer_op(int op)
266{
267        const char *name = alu_opcode_props[op].name;
268
269        if (!name)
270                return false;
271
272        return (name[0] == 'i') || (name[0] == 'u');
273}
274