1848b8605Smrg/*
2848b8605Smrg * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3848b8605Smrg *
4848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5848b8605Smrg * copy of this software and associated documentation files (the "Software"),
6848b8605Smrg * to deal in the Software without restriction, including without limitation
7848b8605Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub
8848b8605Smrg * license, and/or sell copies of the Software, and to permit persons to whom
9848b8605Smrg * the Software is furnished to do so, subject to the following conditions:
10848b8605Smrg *
11848b8605Smrg * The above copyright notice and this permission notice (including the next
12848b8605Smrg * paragraph) shall be included in all copies or substantial portions of the
13848b8605Smrg * Software.
14848b8605Smrg *
15848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16848b8605Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17848b8605Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18848b8605Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19848b8605Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20848b8605Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21848b8605Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22848b8605Smrg
23848b8605Smrg#ifndef R300_CONTEXT_H
24848b8605Smrg#define R300_CONTEXT_H
25848b8605Smrg
26848b8605Smrg#define R300_BUFFER_ALIGNMENT 64
27848b8605Smrg
28848b8605Smrg#include "draw/draw_vertex.h"
29848b8605Smrg
30848b8605Smrg#include "util/u_blitter.h"
31848b8605Smrg
32848b8605Smrg#include "pipe/p_context.h"
33848b8605Smrg#include "util/u_inlines.h"
34848b8605Smrg#include "util/u_transfer.h"
35848b8605Smrg
36848b8605Smrg#include "r300_defines.h"
37848b8605Smrg#include "r300_screen.h"
38848b8605Smrg#include "compiler/radeon_regalloc.h"
39848b8605Smrg
40848b8605Smrgstruct u_upload_mgr;
41848b8605Smrgstruct r300_context;
42848b8605Smrgstruct r300_fragment_shader;
43848b8605Smrgstruct r300_vertex_shader;
44848b8605Smrgstruct r300_stencilref_context;
45848b8605Smrg
46848b8605Smrgenum colormask_swizzle {
47848b8605Smrg    COLORMASK_BGRA,
48848b8605Smrg    COLORMASK_RGBA,
49848b8605Smrg    COLORMASK_RRRR,
50848b8605Smrg    COLORMASK_AAAA,
51848b8605Smrg    COLORMASK_GRRG,
52848b8605Smrg    COLORMASK_ARRA,
53848b8605Smrg    COLORMASK_BGRX,
54848b8605Smrg    COLORMASK_RGBX,
55848b8605Smrg    COLORMASK_NUM_SWIZZLES
56848b8605Smrg};
57848b8605Smrg
58848b8605Smrgstruct r300_atom {
59848b8605Smrg    /* Name, for debugging. */
60848b8605Smrg    const char* name;
61848b8605Smrg    /* Opaque state. */
62848b8605Smrg    void* state;
63848b8605Smrg    /* Emit the state to the context. */
64848b8605Smrg    void (*emit)(struct r300_context*, unsigned, void*);
65848b8605Smrg    /* Upper bound on number of dwords to emit. */
66848b8605Smrg    unsigned size;
67848b8605Smrg    /* Whether this atom should be emitted. */
68848b8605Smrg    boolean dirty;
69848b8605Smrg    /* Whether this atom may be emitted with state == NULL. */
70848b8605Smrg    boolean allow_null_state;
71848b8605Smrg};
72848b8605Smrg
73848b8605Smrgstruct r300_aa_state {
74848b8605Smrg    struct r300_surface *dest;
75848b8605Smrg
76848b8605Smrg    uint32_t aa_config;
77848b8605Smrg};
78848b8605Smrg
79848b8605Smrgstruct r300_blend_state {
80848b8605Smrg    struct pipe_blend_state state;
81848b8605Smrg
82848b8605Smrg    uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
83848b8605Smrg    uint32_t cb_noclamp[8];
84848b8605Smrg    uint32_t cb_noclamp_noalpha[8];
85848b8605Smrg    uint32_t cb_no_readwrite[8];
86848b8605Smrg};
87848b8605Smrg
88848b8605Smrgstruct r300_blend_color_state {
89848b8605Smrg    struct pipe_blend_color state;
90848b8605Smrg    uint32_t cb[3];
91848b8605Smrg};
92848b8605Smrg
93848b8605Smrgstruct r300_clip_state {
94848b8605Smrg    uint32_t cb[29];
95848b8605Smrg};
96848b8605Smrg
97848b8605Smrgstruct r300_dsa_state {
98848b8605Smrg    struct pipe_depth_stencil_alpha_state dsa;
99848b8605Smrg
100848b8605Smrg    /* This is actually a command buffer with named dwords. */
101848b8605Smrg    uint32_t cb_begin;
102848b8605Smrg    uint32_t z_buffer_control;  /* R300_ZB_CNTL: 0x4f00 */
103848b8605Smrg    uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
104848b8605Smrg    uint32_t stencil_ref_mask;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
105848b8605Smrg    uint32_t cb_reg;
106848b8605Smrg    uint32_t stencil_ref_bf;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
107848b8605Smrg    uint32_t cb_reg1;
108848b8605Smrg    uint32_t alpha_value;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
109848b8605Smrg
110848b8605Smrg    /* Same, but without ZB reads and writes. */
111848b8605Smrg    uint32_t cb_zb_no_readwrite[8]; /* ZB not bound */
112848b8605Smrg
113848b8605Smrg    /* Emitted separately: */
114848b8605Smrg    uint32_t alpha_function;
115848b8605Smrg
116848b8605Smrg    /* Whether a two-sided stencil is enabled. */
117848b8605Smrg    boolean two_sided;
118848b8605Smrg    /* Whether a fallback should be used for a two-sided stencil ref value. */
119848b8605Smrg    boolean two_sided_stencil_ref;
120848b8605Smrg};
121848b8605Smrg
122848b8605Smrgstruct r300_hyperz_state {
123848b8605Smrg    int flush;
124848b8605Smrg    /* This is actually a command buffer with named dwords. */
125848b8605Smrg    uint32_t cb_flush_begin;
126848b8605Smrg    uint32_t zb_zcache_ctlstat;     /* R300_ZB_CACHE_CNTL */
127848b8605Smrg    uint32_t cb_begin;
128848b8605Smrg    uint32_t zb_bw_cntl;            /* R300_ZB_BW_CNTL */
129848b8605Smrg    uint32_t cb_reg1;
130848b8605Smrg    uint32_t zb_depthclearvalue;    /* R300_ZB_DEPTHCLEARVALUE */
131848b8605Smrg    uint32_t cb_reg2;
132848b8605Smrg    uint32_t sc_hyperz;             /* R300_SC_HYPERZ */
133848b8605Smrg    uint32_t cb_reg3;
134848b8605Smrg    uint32_t gb_z_peq_config;       /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
135848b8605Smrg};
136848b8605Smrg
137848b8605Smrgstruct r300_gpu_flush {
138848b8605Smrg    uint32_t cb_flush_clean[6];
139848b8605Smrg};
140848b8605Smrg
141848b8605Smrg#define RS_STATE_MAIN_SIZE 27
142848b8605Smrg
143848b8605Smrgstruct r300_rs_state {
144848b8605Smrg    /* Original rasterizer state. */
145848b8605Smrg    struct pipe_rasterizer_state rs;
146848b8605Smrg    /* Draw-specific rasterizer state. */
147848b8605Smrg    struct pipe_rasterizer_state rs_draw;
148848b8605Smrg
149848b8605Smrg    /* Command buffers. */
150848b8605Smrg    uint32_t cb_main[RS_STATE_MAIN_SIZE];
151848b8605Smrg    uint32_t cb_poly_offset_zb16[5];
152848b8605Smrg    uint32_t cb_poly_offset_zb24[5];
153848b8605Smrg
154848b8605Smrg    /* The index to cb_main where the cull_mode register value resides. */
155848b8605Smrg    unsigned cull_mode_index;
156848b8605Smrg
157848b8605Smrg    /* Whether polygon offset is enabled. */
158848b8605Smrg    boolean polygon_offset_enable;
159848b8605Smrg
160848b8605Smrg    /* This is emitted in the draw function. */
161848b8605Smrg    uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
162848b8605Smrg};
163848b8605Smrg
164848b8605Smrgstruct r300_rs_block {
165848b8605Smrg    uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
166848b8605Smrg    uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
167848b8605Smrg    uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
168848b8605Smrg    uint32_t gb_enable;
169848b8605Smrg
170848b8605Smrg    uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
171848b8605Smrg    uint32_t count; /* R300_RS_COUNT */
172848b8605Smrg    uint32_t inst_count; /* R300_RS_INST_COUNT */
173848b8605Smrg    uint32_t inst[8]; /* R300_RS_INST_[0-7] */
174848b8605Smrg};
175848b8605Smrg
176848b8605Smrgstruct r300_sampler_state {
177848b8605Smrg    struct pipe_sampler_state state;
178848b8605Smrg
179848b8605Smrg    uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
180848b8605Smrg    uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
181848b8605Smrg
182848b8605Smrg    /* Min/max LOD must be clamped to [0, last_level], thus
183848b8605Smrg     * it's dependent on a currently bound texture */
184848b8605Smrg    unsigned min_lod, max_lod;
185848b8605Smrg};
186848b8605Smrg
187848b8605Smrgstruct r300_texture_format_state {
188848b8605Smrg    uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
189848b8605Smrg    uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
190848b8605Smrg    uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
191848b8605Smrg    uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
192848b8605Smrg    uint32_t us_format0;   /* R500_US_FORMAT0_0: 0x4640 (through 15) */
193848b8605Smrg};
194848b8605Smrg
195848b8605Smrgstruct r300_sampler_view {
196848b8605Smrg    struct pipe_sampler_view base;
197848b8605Smrg
198848b8605Smrg    /* For resource_copy_region. */
199848b8605Smrg    unsigned width0_override;
200848b8605Smrg    unsigned height0_override;
201848b8605Smrg
202b8e80941Smrg    /* Swizzles in the PIPE_SWIZZLE_* representation,
203848b8605Smrg     * derived from base. */
204848b8605Smrg    unsigned char swizzle[4];
205848b8605Smrg
206848b8605Smrg    /* Copy of r300_texture::texture_format_state with format-specific bits
207848b8605Smrg     * added. */
208848b8605Smrg    struct r300_texture_format_state format;
209848b8605Smrg
210848b8605Smrg    /* The texture cache region for this texture. */
211848b8605Smrg    uint32_t texcache_region;
212848b8605Smrg};
213848b8605Smrg
214848b8605Smrgstruct r300_texture_sampler_state {
215848b8605Smrg    struct r300_texture_format_state format;
216848b8605Smrg    uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
217848b8605Smrg    uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
218848b8605Smrg    uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
219848b8605Smrg};
220848b8605Smrg
221848b8605Smrgstruct r300_textures_state {
222848b8605Smrg    /* Textures. */
223848b8605Smrg    struct r300_sampler_view *sampler_views[16];
224848b8605Smrg    int sampler_view_count;
225848b8605Smrg    /* Sampler states. */
226848b8605Smrg    struct r300_sampler_state *sampler_states[16];
227848b8605Smrg    int sampler_state_count;
228848b8605Smrg
229848b8605Smrg    /* This is the merge of the texture and sampler states. */
230848b8605Smrg    unsigned count;
231848b8605Smrg    uint32_t tx_enable;         /* R300_TX_ENABLE: 0x4101 */
232848b8605Smrg    struct r300_texture_sampler_state regs[16];
233848b8605Smrg};
234848b8605Smrg
235848b8605Smrgstruct r300_vertex_stream_state {
236848b8605Smrg    /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
237848b8605Smrg    uint32_t vap_prog_stream_cntl[8];
238848b8605Smrg    /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
239848b8605Smrg    uint32_t vap_prog_stream_cntl_ext[8];
240848b8605Smrg
241848b8605Smrg    unsigned count;
242848b8605Smrg};
243848b8605Smrg
244848b8605Smrgstruct r300_invariant_state {
245848b8605Smrg    uint32_t cb[24];
246848b8605Smrg};
247848b8605Smrg
248848b8605Smrgstruct r300_vap_invariant_state {
249848b8605Smrg    uint32_t cb[11];
250848b8605Smrg};
251848b8605Smrg
252848b8605Smrgstruct r300_viewport_state {
253848b8605Smrg    float xscale;         /* R300_VAP_VPORT_XSCALE:  0x2098 */
254848b8605Smrg    float xoffset;        /* R300_VAP_VPORT_XOFFSET: 0x209c */
255848b8605Smrg    float yscale;         /* R300_VAP_VPORT_YSCALE:  0x20a0 */
256848b8605Smrg    float yoffset;        /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
257848b8605Smrg    float zscale;         /* R300_VAP_VPORT_ZSCALE:  0x20a8 */
258848b8605Smrg    float zoffset;        /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
259848b8605Smrg    uint32_t vte_control; /* R300_VAP_VTE_CNTL:      0x20b0 */
260848b8605Smrg};
261848b8605Smrg
262848b8605Smrgstruct r300_ztop_state {
263848b8605Smrg    uint32_t z_buffer_top;      /* R300_ZB_ZTOP: 0x4f14 */
264848b8605Smrg};
265848b8605Smrg
266848b8605Smrg/* The next several objects are not pure Radeon state; they inherit from
267848b8605Smrg * various Gallium classes. */
268848b8605Smrg
269848b8605Smrgstruct r300_constant_buffer {
270848b8605Smrg    /* Buffer of constants */
271848b8605Smrg    uint32_t *ptr;
272848b8605Smrg    /* Remapping table. */
273848b8605Smrg    unsigned *remap_table;
274848b8605Smrg    /* const buffer base */
275848b8605Smrg    uint32_t buffer_base;
276848b8605Smrg};
277848b8605Smrg
278848b8605Smrg/* Query object.
279848b8605Smrg *
280848b8605Smrg * This is not a subclass of pipe_query because pipe_query is never
281848b8605Smrg * actually fully defined. So, rather than have it as a member, and do
282848b8605Smrg * subclass-style casting, we treat pipe_query as an opaque, and just
283848b8605Smrg * trust that our state tracker does not ever mess up query objects.
284848b8605Smrg */
285848b8605Smrgstruct r300_query {
286848b8605Smrg    /* The kind of query. Currently only OQ is supported. */
287848b8605Smrg    unsigned type;
288848b8605Smrg    /* The number of pipes where query results are stored. */
289848b8605Smrg    unsigned num_pipes;
290848b8605Smrg    /* How many results have been written, in dwords. It's incremented
291848b8605Smrg     * after end_query and flush. */
292848b8605Smrg    unsigned num_results;
293848b8605Smrg    /* if begin has been emitted */
294848b8605Smrg    boolean begin_emitted;
295848b8605Smrg
296848b8605Smrg    /* The buffer where query results are stored. */
297848b8605Smrg    struct pb_buffer *buf;
298848b8605Smrg};
299848b8605Smrg
300848b8605Smrgstruct r300_surface {
301848b8605Smrg    struct pipe_surface base;
302848b8605Smrg
303848b8605Smrg    /* Winsys buffer backing the texture. */
304848b8605Smrg    struct pb_buffer *buf;
305848b8605Smrg
306848b8605Smrg    enum radeon_bo_domain domain;
307848b8605Smrg
308848b8605Smrg    uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
309848b8605Smrg    uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
310848b8605Smrg    uint32_t pitch_zmask; /* ZMASK_PITCH */
311848b8605Smrg    uint32_t pitch_hiz;   /* HIZ_PITCH */
312848b8605Smrg    uint32_t pitch_cmask; /* CMASK_PITCH */
313848b8605Smrg    uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
314848b8605Smrg
315848b8605Smrg    /* Parameters dedicated to the CBZB clear. */
316848b8605Smrg    uint32_t cbzb_width;            /* Aligned width. */
317848b8605Smrg    uint32_t cbzb_height;           /* Half of the height. */
318848b8605Smrg    uint32_t cbzb_midpoint_offset;  /* DEPTHOFFSET. */
319848b8605Smrg    uint32_t cbzb_pitch;            /* DEPTHPITCH. */
320848b8605Smrg    uint32_t cbzb_format;           /* ZB_FORMAT. */
321848b8605Smrg
322848b8605Smrg    /* Whether the CBZB clear is allowed on the surface. */
323848b8605Smrg    boolean cbzb_allowed;
324848b8605Smrg
325848b8605Smrg    unsigned colormask_swizzle;
326848b8605Smrg};
327848b8605Smrg
328848b8605Smrgstruct r300_texture_desc {
329848b8605Smrg    /* Width, height, and depth.
330848b8605Smrg     * Most of the time, these are equal to pipe_texture::width0, height0,
331848b8605Smrg     * and depth0. However, NPOT 3D textures must have dimensions aligned
332848b8605Smrg     * to POT, and this is the only case when these variables differ from
333848b8605Smrg     * pipe_texture. */
334848b8605Smrg    unsigned width0, height0, depth0;
335848b8605Smrg
336848b8605Smrg    /* Buffer tiling.
337848b8605Smrg     * Macrotiling is specified per-level because small mipmaps cannot
338848b8605Smrg     * be macrotiled. */
339848b8605Smrg    enum radeon_bo_layout microtile;
340848b8605Smrg    enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
341848b8605Smrg
342848b8605Smrg    /* Offsets into the buffer. */
343848b8605Smrg    unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
344848b8605Smrg
345848b8605Smrg    /* Strides for each mip-level. */
346848b8605Smrg    unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
347848b8605Smrg
348848b8605Smrg    /* Size of one zslice or face or 2D image based on the texture target. */
349848b8605Smrg    unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
350848b8605Smrg
351848b8605Smrg    /* Total size of this texture, in bytes,
352848b8605Smrg     * derived from the texture properties. */
353848b8605Smrg    unsigned size_in_bytes;
354848b8605Smrg
355848b8605Smrg    /**
356848b8605Smrg     * If non-zero, override the natural texture layout with
357848b8605Smrg     * a custom stride (in bytes).
358848b8605Smrg     *
359848b8605Smrg     * \note Mipmapping fails for textures with a non-natural layout!
360848b8605Smrg     *
361848b8605Smrg     * \sa r300_texture_get_stride
362848b8605Smrg     */
363848b8605Smrg    unsigned stride_in_bytes_override;
364848b8605Smrg
365848b8605Smrg    /* Whether this texture has non-power-of-two dimensions.
366848b8605Smrg     * It can be either a regular texture or a rectangle one. */
367848b8605Smrg    boolean is_npot;
368848b8605Smrg
369848b8605Smrg    /* This flag says that hardware must use the stride for addressing
370848b8605Smrg     * instead of the width. */
371848b8605Smrg    boolean uses_stride_addressing;
372848b8605Smrg
373848b8605Smrg    /* Whether CBZB fast color clear is allowed on the miplevel. */
374848b8605Smrg    boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
375848b8605Smrg
376848b8605Smrg    /* Zbuffer compression info for each miplevel. */
377848b8605Smrg    boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
378848b8605Smrg    /* If zero, then disable Z compression/HiZ. */
379848b8605Smrg    unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
380848b8605Smrg    unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
381848b8605Smrg    /* Zmask/HiZ strides for each miplevel. */
382848b8605Smrg    unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
383848b8605Smrg    unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
384848b8605Smrg
385848b8605Smrg    /* CMASK info for AA buffers (no mipmapping). */
386848b8605Smrg    unsigned cmask_dwords;
387848b8605Smrg    unsigned cmask_stride_in_pixels;
388848b8605Smrg};
389848b8605Smrg
390848b8605Smrgstruct r300_resource
391848b8605Smrg{
392848b8605Smrg    struct u_resource b;
393848b8605Smrg
394848b8605Smrg    /* Winsys buffer backing this resource. */
395848b8605Smrg    struct pb_buffer *buf;
396848b8605Smrg    enum radeon_bo_domain domain;
397848b8605Smrg
398848b8605Smrg    /* Constant buffers and SWTCL vertex and index buffers are in user
399848b8605Smrg     * memory. */
400848b8605Smrg    uint8_t *malloced_buffer;
401848b8605Smrg
402848b8605Smrg    /* Texture description (addressing, layout, special features). */
403848b8605Smrg    struct r300_texture_desc tex;
404848b8605Smrg
405848b8605Smrg    /* This is the level tiling flags were last time set for.
406848b8605Smrg     * It's used to prevent redundant tiling-flags changes from happening.*/
407848b8605Smrg    unsigned surface_level;
408848b8605Smrg};
409848b8605Smrg
410848b8605Smrgstruct r300_vertex_element_state {
411848b8605Smrg    unsigned count;
412848b8605Smrg    struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
413848b8605Smrg    unsigned format_size[PIPE_MAX_ATTRIBS];
414848b8605Smrg
415848b8605Smrg    /* The size of the vertex, in dwords. */
416848b8605Smrg    unsigned vertex_size_dwords;
417848b8605Smrg
418848b8605Smrg    struct r300_vertex_stream_state vertex_stream;
419848b8605Smrg};
420848b8605Smrg
421848b8605Smrgenum r300_hiz_func {
422848b8605Smrg    HIZ_FUNC_NONE,
423848b8605Smrg
424848b8605Smrg    /* The function, when determined, is set in stone
425848b8605Smrg     * until the next HiZ clear. */
426848b8605Smrg
427848b8605Smrg    /* MAX is written to the HiZ buffer.
428848b8605Smrg     * Used for LESS, LEQUAL. */
429848b8605Smrg    HIZ_FUNC_MAX,
430848b8605Smrg
431848b8605Smrg    /* MIN is written to the HiZ buffer.
432848b8605Smrg     * Used for GREATER, GEQUAL. */
433848b8605Smrg    HIZ_FUNC_MIN,
434848b8605Smrg};
435848b8605Smrg
436848b8605Smrg/* For deferred fragment shader state validation. */
437848b8605Smrgenum r300_fs_validity_status {
438848b8605Smrg    FRAGMENT_SHADER_VALID,      /* No need to change/validate the FS. */
439848b8605Smrg    FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
440848b8605Smrg    FRAGMENT_SHADER_DIRTY       /* Always validate the FS (if the FS was changed) */
441848b8605Smrg};
442848b8605Smrg
443848b8605Smrgstruct r300_context {
444848b8605Smrg    /* Parent class */
445848b8605Smrg    struct pipe_context context;
446848b8605Smrg
447848b8605Smrg    /* The interface to the windowing system, etc. */
448848b8605Smrg    struct radeon_winsys *rws;
449b8e80941Smrg    /* The submission context. */
450b8e80941Smrg    struct radeon_winsys_ctx *ctx;
451848b8605Smrg    /* The command stream. */
452b8e80941Smrg    struct radeon_cmdbuf *cs;
453848b8605Smrg    /* Screen. */
454848b8605Smrg    struct r300_screen *screen;
455848b8605Smrg
456848b8605Smrg    /* Draw module. Used mostly for SW TCL. */
457848b8605Smrg    struct draw_context* draw;
458848b8605Smrg    /* Vertex buffer for SW TCL. */
459848b8605Smrg    struct pb_buffer *vbo;
460848b8605Smrg    /* Offset and size into the SW TCL VBO. */
461848b8605Smrg    size_t draw_vbo_offset;
462848b8605Smrg
463848b8605Smrg    /* Accelerated blit support. */
464848b8605Smrg    struct blitter_context* blitter;
465848b8605Smrg    /* Stencil two-sided reference value fallback. */
466848b8605Smrg    struct r300_stencilref_context *stencilref_fallback;
467848b8605Smrg
468848b8605Smrg    /* The KIL opcode needs the first texture unit to be enabled
469848b8605Smrg     * on r3xx-r4xx. In order to calm down the CS checker, we bind this
470848b8605Smrg     * dummy texture there. */
471848b8605Smrg    struct r300_sampler_view *texkill_sampler;
472848b8605Smrg
473848b8605Smrg    /* When no vertex buffer is set, this one is used instead to prevent
474848b8605Smrg     * hardlocks. */
475848b8605Smrg    struct pipe_vertex_buffer dummy_vb;
476848b8605Smrg
477848b8605Smrg    /* The currently active query. */
478848b8605Smrg    struct r300_query *query_current;
479848b8605Smrg    /* The saved query for blitter operations. */
480848b8605Smrg    struct r300_query *blitter_saved_query;
481848b8605Smrg    /* Query list. */
482848b8605Smrg    struct r300_query query_list;
483848b8605Smrg
484848b8605Smrg    /* Various CSO state objects. */
485848b8605Smrg
486848b8605Smrg    /* Each atom is emitted in the order it appears here, which can affect
487848b8605Smrg     * performance and stability if not handled with care. */
488848b8605Smrg    /* GPU flush. */
489848b8605Smrg    struct r300_atom gpu_flush;
490848b8605Smrg    /* Clears must be emitted immediately after the flush. */
491848b8605Smrg    /* HiZ clear */
492848b8605Smrg    struct r300_atom hiz_clear;
493848b8605Smrg    /* zmask clear */
494848b8605Smrg    struct r300_atom zmask_clear;
495848b8605Smrg    /* cmask clear */
496848b8605Smrg    struct r300_atom cmask_clear;
497848b8605Smrg    /* Anti-aliasing (MSAA) state. */
498848b8605Smrg    struct r300_atom aa_state;
499848b8605Smrg    /* Framebuffer state. */
500848b8605Smrg    struct r300_atom fb_state;
501848b8605Smrg    /* HyperZ state (various SC/ZB bits). */
502848b8605Smrg    struct r300_atom hyperz_state;
503848b8605Smrg    /* ZTOP state. */
504848b8605Smrg    struct r300_atom ztop_state;
505848b8605Smrg    /* Depth, stencil, and alpha state. */
506848b8605Smrg    struct r300_atom dsa_state;
507848b8605Smrg    /* Blend state. */
508848b8605Smrg    struct r300_atom blend_state;
509848b8605Smrg    /* Blend color state. */
510848b8605Smrg    struct r300_atom blend_color_state;
511848b8605Smrg    /* Scissor state. */
512848b8605Smrg    struct r300_atom scissor_state;
513848b8605Smrg    /* Sample mask. */
514848b8605Smrg    struct r300_atom sample_mask;
515848b8605Smrg    /* Invariant state. This must be emitted to get the engine started. */
516848b8605Smrg    struct r300_atom invariant_state;
517848b8605Smrg    /* Viewport state. */
518848b8605Smrg    struct r300_atom viewport_state;
519848b8605Smrg    /* PVS flush. */
520848b8605Smrg    struct r300_atom pvs_flush;
521848b8605Smrg    /* VAP invariant state. */
522848b8605Smrg    struct r300_atom vap_invariant_state;
523848b8605Smrg    /* Vertex stream formatting state. */
524848b8605Smrg    struct r300_atom vertex_stream_state;
525848b8605Smrg    /* Vertex shader. */
526848b8605Smrg    struct r300_atom vs_state;
527848b8605Smrg    /* User clip planes. */
528848b8605Smrg    struct r300_atom clip_state;
529848b8605Smrg    /* RS block state + VAP (vertex shader) output mapping state. */
530848b8605Smrg    struct r300_atom rs_block_state;
531848b8605Smrg    /* Rasterizer state. */
532848b8605Smrg    struct r300_atom rs_state;
533848b8605Smrg    /* Framebuffer state (pipelined regs). */
534848b8605Smrg    struct r300_atom fb_state_pipelined;
535848b8605Smrg    /* Fragment shader. */
536848b8605Smrg    struct r300_atom fs;
537848b8605Smrg    /* Fragment shader RC_CONSTANT_STATE variables. */
538848b8605Smrg    struct r300_atom fs_rc_constant_state;
539848b8605Smrg    /* Fragment shader constant buffer. */
540848b8605Smrg    struct r300_atom fs_constants;
541848b8605Smrg    /* Vertex shader constant buffer. */
542848b8605Smrg    struct r300_atom vs_constants;
543848b8605Smrg    /* Texture cache invalidate. */
544848b8605Smrg    struct r300_atom texture_cache_inval;
545848b8605Smrg    /* Textures state. */
546848b8605Smrg    struct r300_atom textures_state;
547848b8605Smrg    /* Occlusion query. */
548848b8605Smrg    struct r300_atom query_start;
549848b8605Smrg
550848b8605Smrg    /* The pointers to the first and the last atom. */
551848b8605Smrg    struct r300_atom *first_dirty, *last_dirty;
552848b8605Smrg
553848b8605Smrg    /* Vertex elements for Gallium. */
554848b8605Smrg    struct r300_vertex_element_state *velems;
555848b8605Smrg
556848b8605Smrg    /* Vertex info for Draw. */
557848b8605Smrg    struct vertex_info vertex_info;
558848b8605Smrg
559848b8605Smrg    struct pipe_stencil_ref stencil_ref;
560848b8605Smrg    struct pipe_viewport_state viewport;
561848b8605Smrg
562848b8605Smrg    /* Stream locations for SWTCL. */
563848b8605Smrg    int stream_loc_notcl[16];
564848b8605Smrg
565848b8605Smrg    /* Flag indicating whether or not the HW is dirty. */
566848b8605Smrg    uint32_t dirty_hw;
567848b8605Smrg    /* Whether polygon offset is enabled. */
568848b8605Smrg    boolean polygon_offset_enabled;
569848b8605Smrg    /* Z buffer bit depth. */
570848b8605Smrg    uint32_t zbuffer_bpp;
571848b8605Smrg    /* Whether rendering is conditional and should be skipped. */
572848b8605Smrg    boolean skip_rendering;
573848b8605Smrg    /* The flag above saved by blitter. */
574848b8605Smrg    unsigned char blitter_saved_skip_rendering;
575848b8605Smrg    /* Point sprites texcoord index,  1 bit per texcoord */
576848b8605Smrg    int sprite_coord_enable;
577848b8605Smrg    /* Whether two-sided color selection is enabled (AKA light_twoside). */
578848b8605Smrg    boolean two_sided_color;
579848b8605Smrg    boolean flatshade;
580b8e80941Smrg    boolean clip_halfz;
581848b8605Smrg    /* Whether fast color clear is enabled. */
582848b8605Smrg    boolean cbzb_clear;
583848b8605Smrg    /* Whether fragment shader needs to be validated. */
584848b8605Smrg    enum r300_fs_validity_status fs_status;
585848b8605Smrg    /* Framebuffer multi-write. */
586848b8605Smrg    boolean fb_multiwrite;
587848b8605Smrg    unsigned num_samples;
588848b8605Smrg    boolean msaa_enable;
589848b8605Smrg    boolean alpha_to_one;
590848b8605Smrg    boolean alpha_to_coverage;
591848b8605Smrg
592848b8605Smrg    void *dsa_decompress_zmask;
593848b8605Smrg
594848b8605Smrg    struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
595848b8605Smrg    unsigned nr_vertex_buffers;
596848b8605Smrg    struct u_upload_mgr *uploader;
597848b8605Smrg
598b8e80941Smrg    struct slab_child_pool pool_transfers;
599848b8605Smrg
600848b8605Smrg    /* Stat counter. */
601848b8605Smrg    uint64_t flush_counter;
602848b8605Smrg
603848b8605Smrg    /* const tracking for VS */
604848b8605Smrg    int vs_const_base;
605848b8605Smrg
606848b8605Smrg    /* Vertex array state info */
607848b8605Smrg    boolean vertex_arrays_dirty;
608848b8605Smrg    boolean vertex_arrays_indexed;
609848b8605Smrg    int vertex_arrays_offset;
610848b8605Smrg    int vertex_arrays_instance_id;
611848b8605Smrg    boolean instancing_enabled;
612848b8605Smrg
613848b8605Smrg    /* Hyper-Z stats. */
614848b8605Smrg    boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
615848b8605Smrg    int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
616848b8605Smrg    unsigned num_z_clears;      /* Since the last flush. */
617848b8605Smrg
618848b8605Smrg    /* ZMask state. */
619848b8605Smrg    boolean zmask_in_use;       /* Whether ZMASK is enabled. */
620848b8605Smrg    boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
621848b8605Smrg    struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
622848b8605Smrg
623848b8605Smrg    /* HiZ state. */
624848b8605Smrg    boolean hiz_in_use;         /* Whether HIZ is enabled. */
625848b8605Smrg    enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
626848b8605Smrg    uint32_t hiz_clear_value;   /* HiZ clear value. */
627848b8605Smrg
628848b8605Smrg    /* CMASK state. */
629848b8605Smrg    boolean cmask_access;
630848b8605Smrg    boolean cmask_in_use;
631848b8605Smrg    uint32_t color_clear_value; /* RGBA8 or RGBA1010102 */
632848b8605Smrg    uint32_t color_clear_value_ar; /* RGBA16F */
633848b8605Smrg    uint32_t color_clear_value_gb; /* RGBA16F */
634848b8605Smrg
635848b8605Smrg    /* Compiler state. */
636848b8605Smrg    struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for
637848b8605Smrg                                                 * fragment shaders. */
638848b8605Smrg};
639848b8605Smrg
640848b8605Smrg#define foreach_atom(r300, atom) \
641848b8605Smrg    for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
642848b8605Smrg
643848b8605Smrg#define foreach_dirty_atom(r300, atom) \
644848b8605Smrg    for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
645848b8605Smrg
646848b8605Smrg/* Convenience cast wrappers. */
647b8e80941Smrgstatic inline struct r300_query* r300_query(struct pipe_query* q)
648848b8605Smrg{
649848b8605Smrg    return (struct r300_query*)q;
650848b8605Smrg}
651848b8605Smrg
652b8e80941Smrgstatic inline struct r300_surface* r300_surface(struct pipe_surface* surf)
653848b8605Smrg{
654848b8605Smrg    return (struct r300_surface*)surf;
655848b8605Smrg}
656848b8605Smrg
657b8e80941Smrgstatic inline struct r300_resource* r300_resource(struct pipe_resource* tex)
658848b8605Smrg{
659848b8605Smrg    return (struct r300_resource*)tex;
660848b8605Smrg}
661848b8605Smrg
662b8e80941Smrgstatic inline struct r300_context* r300_context(struct pipe_context* context)
663848b8605Smrg{
664848b8605Smrg    return (struct r300_context*)context;
665848b8605Smrg}
666848b8605Smrg
667b8e80941Smrgstatic inline struct r300_fragment_shader *r300_fs(struct r300_context *r300)
668848b8605Smrg{
669848b8605Smrg    return (struct r300_fragment_shader*)r300->fs.state;
670848b8605Smrg}
671848b8605Smrg
672b8e80941Smrgstatic inline void r300_mark_atom_dirty(struct r300_context *r300,
673848b8605Smrg                                        struct r300_atom *atom)
674848b8605Smrg{
675848b8605Smrg    atom->dirty = TRUE;
676848b8605Smrg
677848b8605Smrg    if (!r300->first_dirty) {
678848b8605Smrg        r300->first_dirty = atom;
679848b8605Smrg        r300->last_dirty = atom+1;
680848b8605Smrg    } else {
681848b8605Smrg        if (atom < r300->first_dirty)
682848b8605Smrg            r300->first_dirty = atom;
683848b8605Smrg        else if (atom+1 > r300->last_dirty)
684848b8605Smrg            r300->last_dirty = atom+1;
685848b8605Smrg    }
686848b8605Smrg}
687848b8605Smrg
688b8e80941Smrgstatic inline struct pipe_surface *
689848b8605Smrgr300_get_nonnull_cb(struct pipe_framebuffer_state *fb, unsigned i)
690848b8605Smrg{
691848b8605Smrg    if (fb->cbufs[i])
692848b8605Smrg        return fb->cbufs[i];
693848b8605Smrg
694848b8605Smrg    /* The i-th framebuffer is NULL, return any non-NULL one. */
695848b8605Smrg    for (i = 0; i < fb->nr_cbufs; i++)
696848b8605Smrg        if (fb->cbufs[i])
697848b8605Smrg            return fb->cbufs[i];
698848b8605Smrg
699848b8605Smrg    return NULL;
700848b8605Smrg}
701848b8605Smrg
702848b8605Smrgstruct pipe_context* r300_create_context(struct pipe_screen* screen,
703b8e80941Smrg                                         void *priv, unsigned flags);
704848b8605Smrg
705848b8605Smrg/* Context initialization. */
706848b8605Smrgstruct draw_stage* r300_draw_stage(struct r300_context* r300);
707848b8605Smrgvoid r300_init_blit_functions(struct r300_context *r300);
708848b8605Smrgvoid r300_init_flush_functions(struct r300_context* r300);
709848b8605Smrgvoid r300_init_query_functions(struct r300_context* r300);
710848b8605Smrgvoid r300_init_render_functions(struct r300_context *r300);
711848b8605Smrgvoid r300_init_state_functions(struct r300_context* r300);
712848b8605Smrgvoid r300_init_resource_functions(struct r300_context* r300);
713848b8605Smrg
714848b8605Smrg/* r300_blit.c */
715848b8605Smrgvoid r300_decompress_zmask(struct r300_context *r300);
716848b8605Smrgvoid r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
717848b8605Smrgvoid r300_decompress_zmask_locked(struct r300_context *r300);
718848b8605Smrgbool r300_is_blit_supported(enum pipe_format format);
719848b8605Smrg
720848b8605Smrg/* r300_flush.c */
721848b8605Smrgvoid r300_flush(struct pipe_context *pipe,
722848b8605Smrg                unsigned flags,
723848b8605Smrg                struct pipe_fence_handle **fence);
724848b8605Smrg
725848b8605Smrg/* r300_hyperz.c */
726848b8605Smrgvoid r300_update_hyperz_state(struct r300_context* r300);
727848b8605Smrg
728848b8605Smrg/* r300_query.c */
729848b8605Smrgvoid r300_resume_query(struct r300_context *r300,
730848b8605Smrg                       struct r300_query *query);
731848b8605Smrgvoid r300_stop_query(struct r300_context *r300);
732848b8605Smrg
733848b8605Smrg/* r300_render_translate.c */
734848b8605Smrgvoid r300_translate_index_buffer(struct r300_context *r300,
735b8e80941Smrg                                 const struct pipe_draw_info *info,
736848b8605Smrg                                 struct pipe_resource **out_index_buffer,
737848b8605Smrg                                 unsigned *index_size, unsigned index_offset,
738848b8605Smrg                                 unsigned *start, unsigned count);
739848b8605Smrg
740848b8605Smrg/* r300_render_stencilref.c */
741848b8605Smrgvoid r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
742848b8605Smrg
743848b8605Smrg/* r300_render.c */
744848b8605Smrgvoid r500_emit_index_bias(struct r300_context *r300, int index_bias);
745848b8605Smrgvoid r300_blitter_draw_rectangle(struct blitter_context *blitter,
746b8e80941Smrg                                 void *vertex_elements_cso,
747b8e80941Smrg                                 blitter_get_vs_func get_vs,
748848b8605Smrg                                 int x1, int y1, int x2, int y2,
749b8e80941Smrg                                 float depth, unsigned num_instances,
750848b8605Smrg                                 enum blitter_attrib_type type,
751b8e80941Smrg                                 const union blitter_attrib *attrib);
752848b8605Smrg
753848b8605Smrg/* r300_state.c */
754848b8605Smrgenum r300_fb_state_change {
755848b8605Smrg    R300_CHANGED_FB_STATE = 0,
756848b8605Smrg    R300_CHANGED_HYPERZ_FLAG,
757848b8605Smrg    R300_CHANGED_MULTIWRITE,
758848b8605Smrg    R300_CHANGED_CMASK_ENABLE,
759848b8605Smrg};
760848b8605Smrg
761848b8605Smrgvoid r300_mark_fb_state_dirty(struct r300_context *r300,
762848b8605Smrg                              enum r300_fb_state_change change);
763848b8605Smrgvoid r300_mark_fs_code_dirty(struct r300_context *r300);
764848b8605Smrg
765848b8605Smrgstruct pipe_sampler_view *
766848b8605Smrgr300_create_sampler_view_custom(struct pipe_context *pipe,
767848b8605Smrg                         struct pipe_resource *texture,
768848b8605Smrg                         const struct pipe_sampler_view *templ,
769848b8605Smrg                         unsigned width0_override,
770848b8605Smrg                         unsigned height0_override);
771848b8605Smrg
772848b8605Smrg/* r300_state_derived.c */
773848b8605Smrgvoid r300_update_derived_state(struct r300_context* r300);
774848b8605Smrg
775848b8605Smrg/* r300_debug.c */
776848b8605Smrgvoid r500_dump_rs_block(struct r300_rs_block *rs);
777848b8605Smrg
778848b8605Smrg
779b8e80941Smrgstatic inline boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
780848b8605Smrg{
781848b8605Smrg    return SCREEN_DBG_ON(ctx->screen, flags);
782848b8605Smrg}
783848b8605Smrg
784b8e80941Smrgstatic inline void CTX_DBG(struct r300_context * ctx, unsigned flags,
785848b8605Smrg                       const char * fmt, ...)
786848b8605Smrg{
787848b8605Smrg    if (CTX_DBG_ON(ctx, flags)) {
788848b8605Smrg        va_list va;
789848b8605Smrg        va_start(va, fmt);
790848b8605Smrg        vfprintf(stderr, fmt, va);
791848b8605Smrg        va_end(va);
792848b8605Smrg    }
793848b8605Smrg}
794848b8605Smrg
795848b8605Smrg#define DBG_ON  CTX_DBG_ON
796848b8605Smrg#define DBG     CTX_DBG
797848b8605Smrg
798848b8605Smrg#endif /* R300_CONTEXT_H */
799