1848b8605Smrg/*
2848b8605Smrg * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3848b8605Smrg * Copyright 2010 Marek Olšák <maraeo@gmail.com>
4848b8605Smrg *
5848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
6848b8605Smrg * copy of this software and associated documentation files (the "Software"),
7848b8605Smrg * to deal in the Software without restriction, including without limitation
8848b8605Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub
9848b8605Smrg * license, and/or sell copies of the Software, and to permit persons to whom
10848b8605Smrg * the Software is furnished to do so, subject to the following conditions:
11848b8605Smrg *
12848b8605Smrg * The above copyright notice and this permission notice (including the next
13848b8605Smrg * paragraph) shall be included in all copies or substantial portions of the
14848b8605Smrg * Software.
15848b8605Smrg *
16848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17848b8605Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18848b8605Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19848b8605Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20848b8605Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21848b8605Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22848b8605Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23848b8605Smrg
24848b8605Smrg#include "util/u_format.h"
25848b8605Smrg#include "util/u_format_s3tc.h"
26b8e80941Smrg#include "util/u_screen.h"
27848b8605Smrg#include "util/u_memory.h"
28b8e80941Smrg#include "util/os_time.h"
29848b8605Smrg#include "vl/vl_decoder.h"
30848b8605Smrg#include "vl/vl_video_buffer.h"
31848b8605Smrg
32848b8605Smrg#include "r300_context.h"
33848b8605Smrg#include "r300_texture.h"
34848b8605Smrg#include "r300_screen_buffer.h"
35848b8605Smrg#include "r300_state_inlines.h"
36848b8605Smrg#include "r300_public.h"
37848b8605Smrg
38848b8605Smrg#include "draw/draw_context.h"
39848b8605Smrg
40848b8605Smrg/* Return the identifier behind whom the brave coders responsible for this
41848b8605Smrg * amalgamation of code, sweat, and duct tape, routinely obscure their names.
42848b8605Smrg *
43848b8605Smrg * ...I should have just put "Corbin Simpson", but I'm not that cool.
44848b8605Smrg *
45848b8605Smrg * (Or egotistical. Yet.) */
46848b8605Smrgstatic const char* r300_get_vendor(struct pipe_screen* pscreen)
47848b8605Smrg{
48848b8605Smrg    return "X.Org R300 Project";
49848b8605Smrg}
50848b8605Smrg
51b8e80941Smrgstatic const char* r300_get_device_vendor(struct pipe_screen* pscreen)
52b8e80941Smrg{
53b8e80941Smrg    return "ATI";
54b8e80941Smrg}
55b8e80941Smrg
56848b8605Smrgstatic const char* chip_families[] = {
57848b8605Smrg    "unknown",
58848b8605Smrg    "ATI R300",
59848b8605Smrg    "ATI R350",
60848b8605Smrg    "ATI RV350",
61848b8605Smrg    "ATI RV370",
62848b8605Smrg    "ATI RV380",
63848b8605Smrg    "ATI RS400",
64848b8605Smrg    "ATI RC410",
65848b8605Smrg    "ATI RS480",
66848b8605Smrg    "ATI R420",
67848b8605Smrg    "ATI R423",
68848b8605Smrg    "ATI R430",
69848b8605Smrg    "ATI R480",
70848b8605Smrg    "ATI R481",
71848b8605Smrg    "ATI RV410",
72848b8605Smrg    "ATI RS600",
73848b8605Smrg    "ATI RS690",
74848b8605Smrg    "ATI RS740",
75848b8605Smrg    "ATI RV515",
76848b8605Smrg    "ATI R520",
77848b8605Smrg    "ATI RV530",
78848b8605Smrg    "ATI R580",
79848b8605Smrg    "ATI RV560",
80848b8605Smrg    "ATI RV570"
81848b8605Smrg};
82848b8605Smrg
83848b8605Smrgstatic const char* r300_get_name(struct pipe_screen* pscreen)
84848b8605Smrg{
85848b8605Smrg    struct r300_screen* r300screen = r300_screen(pscreen);
86848b8605Smrg
87848b8605Smrg    return chip_families[r300screen->caps.family];
88848b8605Smrg}
89848b8605Smrg
90848b8605Smrgstatic int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
91848b8605Smrg{
92848b8605Smrg    struct r300_screen* r300screen = r300_screen(pscreen);
93848b8605Smrg    boolean is_r500 = r300screen->caps.is_r500;
94848b8605Smrg
95848b8605Smrg    switch (param) {
96848b8605Smrg        /* Supported features (boolean caps). */
97848b8605Smrg        case PIPE_CAP_NPOT_TEXTURES:
98848b8605Smrg        case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
99b8e80941Smrg        case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
100848b8605Smrg        case PIPE_CAP_ANISOTROPIC_FILTER:
101848b8605Smrg        case PIPE_CAP_POINT_SPRITE:
102848b8605Smrg        case PIPE_CAP_OCCLUSION_QUERY:
103848b8605Smrg        case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104b8e80941Smrg        case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
105848b8605Smrg        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
106848b8605Smrg        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
107848b8605Smrg        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
108848b8605Smrg        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
109848b8605Smrg        case PIPE_CAP_CONDITIONAL_RENDER:
110848b8605Smrg        case PIPE_CAP_TEXTURE_BARRIER:
111848b8605Smrg        case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
112848b8605Smrg        case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
113848b8605Smrg        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
114b8e80941Smrg        case PIPE_CAP_CLIP_HALFZ:
115b8e80941Smrg        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
116848b8605Smrg            return 1;
117848b8605Smrg
118848b8605Smrg        case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
119848b8605Smrg            return R300_BUFFER_ALIGNMENT;
120848b8605Smrg
121848b8605Smrg        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
122848b8605Smrg            return 16;
123848b8605Smrg
124848b8605Smrg        case PIPE_CAP_GLSL_FEATURE_LEVEL:
125b8e80941Smrg        case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
126848b8605Smrg            return 120;
127848b8605Smrg
128848b8605Smrg        /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
129848b8605Smrg        case PIPE_CAP_TEXTURE_SWIZZLE:
130b8e80941Smrg            return r300screen->caps.dxtc_swizzle;
131848b8605Smrg
132848b8605Smrg        /* We don't support color clamping on r500, so that we can use color
133848b8605Smrg         * intepolators for generic varyings. */
134848b8605Smrg        case PIPE_CAP_VERTEX_COLOR_CLAMPED:
135848b8605Smrg            return !is_r500;
136848b8605Smrg
137848b8605Smrg        /* Supported on r500 only. */
138848b8605Smrg        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139848b8605Smrg        case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
140848b8605Smrg        case PIPE_CAP_SM3:
141848b8605Smrg            return is_r500 ? 1 : 0;
142848b8605Smrg
143848b8605Smrg        /* Unsupported features. */
144848b8605Smrg        case PIPE_CAP_QUERY_TIME_ELAPSED:
145848b8605Smrg        case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
146848b8605Smrg        case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
147848b8605Smrg        case PIPE_CAP_INDEP_BLEND_ENABLE:
148848b8605Smrg        case PIPE_CAP_INDEP_BLEND_FUNC:
149848b8605Smrg        case PIPE_CAP_DEPTH_CLIP_DISABLE:
150b8e80941Smrg        case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
151848b8605Smrg        case PIPE_CAP_SHADER_STENCIL_EXPORT:
152848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
153848b8605Smrg        case PIPE_CAP_TGSI_INSTANCEID:
154848b8605Smrg        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
155848b8605Smrg        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
156848b8605Smrg        case PIPE_CAP_SEAMLESS_CUBE_MAP:
157848b8605Smrg        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
158848b8605Smrg        case PIPE_CAP_MIN_TEXEL_OFFSET:
159848b8605Smrg        case PIPE_CAP_MAX_TEXEL_OFFSET:
160848b8605Smrg        case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
161848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
162848b8605Smrg        case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
163848b8605Smrg        case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
164848b8605Smrg        case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
165848b8605Smrg        case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
166848b8605Smrg        case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
167848b8605Smrg        case PIPE_CAP_MAX_VERTEX_STREAMS:
168848b8605Smrg        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
169b8e80941Smrg        case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
170848b8605Smrg        case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
171848b8605Smrg        case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
172848b8605Smrg        case PIPE_CAP_COMPUTE:
173848b8605Smrg        case PIPE_CAP_START_INSTANCE:
174848b8605Smrg        case PIPE_CAP_QUERY_TIMESTAMP:
175848b8605Smrg        case PIPE_CAP_TEXTURE_MULTISAMPLE:
176848b8605Smrg        case PIPE_CAP_CUBE_MAP_ARRAY:
177848b8605Smrg        case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
178848b8605Smrg        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
179848b8605Smrg        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
180848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
181848b8605Smrg        case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
182848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
183848b8605Smrg        case PIPE_CAP_TEXTURE_GATHER_SM5:
184848b8605Smrg        case PIPE_CAP_TEXTURE_QUERY_LOD:
185848b8605Smrg        case PIPE_CAP_FAKE_SW_MSAA:
186848b8605Smrg        case PIPE_CAP_SAMPLE_SHADING:
187848b8605Smrg        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
188848b8605Smrg        case PIPE_CAP_DRAW_INDIRECT:
189b8e80941Smrg        case PIPE_CAP_MULTI_DRAW_INDIRECT:
190b8e80941Smrg        case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191848b8605Smrg        case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
192848b8605Smrg        case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
193b8e80941Smrg        case PIPE_CAP_SAMPLER_VIEW_TARGET:
194b8e80941Smrg        case PIPE_CAP_VERTEXID_NOBASE:
195b8e80941Smrg        case PIPE_CAP_POLYGON_OFFSET_CLAMP:
196b8e80941Smrg        case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
197b8e80941Smrg        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
198b8e80941Smrg        case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
199b8e80941Smrg        case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
200b8e80941Smrg        case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
201b8e80941Smrg        case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
202b8e80941Smrg        case PIPE_CAP_DEPTH_BOUNDS_TEST:
203b8e80941Smrg        case PIPE_CAP_TGSI_TXQS:
204b8e80941Smrg        case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
205b8e80941Smrg        case PIPE_CAP_SHAREABLE_SHADERS:
206b8e80941Smrg        case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
207b8e80941Smrg        case PIPE_CAP_CLEAR_TEXTURE:
208b8e80941Smrg        case PIPE_CAP_DRAW_PARAMETERS:
209b8e80941Smrg        case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
210b8e80941Smrg        case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
211b8e80941Smrg        case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
212b8e80941Smrg        case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
213b8e80941Smrg        case PIPE_CAP_INVALIDATE_BUFFER:
214b8e80941Smrg        case PIPE_CAP_GENERATE_MIPMAP:
215b8e80941Smrg        case PIPE_CAP_STRING_MARKER:
216b8e80941Smrg        case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
217b8e80941Smrg        case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
218b8e80941Smrg        case PIPE_CAP_QUERY_BUFFER_OBJECT:
219b8e80941Smrg        case PIPE_CAP_QUERY_MEMORY_INFO:
220b8e80941Smrg        case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
221b8e80941Smrg        case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
222b8e80941Smrg        case PIPE_CAP_CULL_DISTANCE:
223b8e80941Smrg        case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
224b8e80941Smrg        case PIPE_CAP_TGSI_VOTE:
225b8e80941Smrg        case PIPE_CAP_MAX_WINDOW_RECTANGLES:
226b8e80941Smrg        case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
227b8e80941Smrg        case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
228b8e80941Smrg        case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
229b8e80941Smrg        case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
230b8e80941Smrg        case PIPE_CAP_NATIVE_FENCE_FD:
231b8e80941Smrg        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
232b8e80941Smrg        case PIPE_CAP_TGSI_FS_FBFETCH:
233b8e80941Smrg        case PIPE_CAP_TGSI_MUL_ZERO_WINS:
234b8e80941Smrg        case PIPE_CAP_DOUBLES:
235b8e80941Smrg        case PIPE_CAP_INT64:
236b8e80941Smrg        case PIPE_CAP_INT64_DIVMOD:
237b8e80941Smrg        case PIPE_CAP_TGSI_TEX_TXF_LZ:
238b8e80941Smrg        case PIPE_CAP_TGSI_CLOCK:
239b8e80941Smrg        case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
240b8e80941Smrg        case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
241b8e80941Smrg        case PIPE_CAP_TGSI_BALLOT:
242b8e80941Smrg        case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
243b8e80941Smrg        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
244b8e80941Smrg        case PIPE_CAP_POST_DEPTH_COVERAGE:
245b8e80941Smrg        case PIPE_CAP_BINDLESS_TEXTURE:
246b8e80941Smrg        case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
247b8e80941Smrg        case PIPE_CAP_QUERY_SO_OVERFLOW:
248b8e80941Smrg        case PIPE_CAP_MEMOBJ:
249b8e80941Smrg        case PIPE_CAP_LOAD_CONSTBUF:
250b8e80941Smrg        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
251b8e80941Smrg        case PIPE_CAP_TILE_RASTER_ORDER:
252b8e80941Smrg        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
253b8e80941Smrg        case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
254b8e80941Smrg        case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
255b8e80941Smrg        case PIPE_CAP_CONTEXT_PRIORITY_MASK:
256b8e80941Smrg        case PIPE_CAP_FENCE_SIGNAL:
257b8e80941Smrg        case PIPE_CAP_CONSTBUF0_FLAGS:
258b8e80941Smrg        case PIPE_CAP_PACKED_UNIFORMS:
259b8e80941Smrg        case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
260b8e80941Smrg        case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
261b8e80941Smrg        case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
262b8e80941Smrg        case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
263b8e80941Smrg        case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
264b8e80941Smrg        case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
265b8e80941Smrg        case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
266b8e80941Smrg        case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
267848b8605Smrg            return 0;
268848b8605Smrg
269b8e80941Smrg        case PIPE_CAP_MAX_GS_INVOCATIONS:
270b8e80941Smrg            return 32;
271b8e80941Smrg       case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
272b8e80941Smrg            return 1 << 27;
273b8e80941Smrg
274848b8605Smrg        /* SWTCL-only features. */
275848b8605Smrg        case PIPE_CAP_PRIMITIVE_RESTART:
276848b8605Smrg        case PIPE_CAP_USER_VERTEX_BUFFERS:
277b8e80941Smrg        case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
278848b8605Smrg            return !r300screen->caps.has_tcl;
279848b8605Smrg
280848b8605Smrg        /* HWTCL-only features / limitations. */
281848b8605Smrg        case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
282848b8605Smrg        case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
283848b8605Smrg        case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
284848b8605Smrg            return r300screen->caps.has_tcl;
285b8e80941Smrg        case PIPE_CAP_TGSI_TEXCOORD:
286848b8605Smrg            return 0;
287848b8605Smrg
288848b8605Smrg        /* Texturing. */
289848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
290848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
291848b8605Smrg        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
292848b8605Smrg            /* 13 == 4096, 12 == 2048 */
293848b8605Smrg            return is_r500 ? 13 : 12;
294848b8605Smrg
295848b8605Smrg        /* Render targets. */
296848b8605Smrg        case PIPE_CAP_MAX_RENDER_TARGETS:
297848b8605Smrg            return 4;
298b8e80941Smrg        case PIPE_CAP_ENDIANNESS:
299848b8605Smrg            return PIPE_ENDIAN_LITTLE;
300848b8605Smrg
301848b8605Smrg        case PIPE_CAP_MAX_VIEWPORTS:
302848b8605Smrg            return 1;
303848b8605Smrg
304b8e80941Smrg        case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
305b8e80941Smrg            return 2048;
306b8e80941Smrg
307b8e80941Smrg        case PIPE_CAP_MAX_VARYINGS:
308b8e80941Smrg            return 10;
309b8e80941Smrg
310848b8605Smrg        case PIPE_CAP_VENDOR_ID:
311848b8605Smrg                return 0x1002;
312848b8605Smrg        case PIPE_CAP_DEVICE_ID:
313848b8605Smrg                return r300screen->info.pci_id;
314848b8605Smrg        case PIPE_CAP_ACCELERATED:
315848b8605Smrg                return 1;
316848b8605Smrg        case PIPE_CAP_VIDEO_MEMORY:
317848b8605Smrg                return r300screen->info.vram_size >> 20;
318848b8605Smrg        case PIPE_CAP_UMA:
319848b8605Smrg                return 0;
320b8e80941Smrg        case PIPE_CAP_PCI_GROUP:
321b8e80941Smrg            return r300screen->info.pci_domain;
322b8e80941Smrg        case PIPE_CAP_PCI_BUS:
323b8e80941Smrg            return r300screen->info.pci_bus;
324b8e80941Smrg        case PIPE_CAP_PCI_DEVICE:
325b8e80941Smrg            return r300screen->info.pci_dev;
326b8e80941Smrg        case PIPE_CAP_PCI_FUNCTION:
327b8e80941Smrg            return r300screen->info.pci_func;
328b8e80941Smrg        default:
329b8e80941Smrg            return u_pipe_screen_get_param_defaults(pscreen, param);
330848b8605Smrg    }
331848b8605Smrg}
332848b8605Smrg
333b8e80941Smrgstatic int r300_get_shader_param(struct pipe_screen *pscreen,
334b8e80941Smrg                                 enum pipe_shader_type shader,
335b8e80941Smrg                                 enum pipe_shader_cap param)
336848b8605Smrg{
337848b8605Smrg   struct r300_screen* r300screen = r300_screen(pscreen);
338848b8605Smrg   boolean is_r400 = r300screen->caps.is_r400;
339848b8605Smrg   boolean is_r500 = r300screen->caps.is_r500;
340848b8605Smrg
341848b8605Smrg   switch (shader) {
342848b8605Smrg    case PIPE_SHADER_FRAGMENT:
343848b8605Smrg        switch (param)
344848b8605Smrg        {
345848b8605Smrg        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
346848b8605Smrg            return is_r500 || is_r400 ? 512 : 96;
347848b8605Smrg        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
348848b8605Smrg            return is_r500 || is_r400 ? 512 : 64;
349848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
350848b8605Smrg            return is_r500 || is_r400 ? 512 : 32;
351848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
352848b8605Smrg            return is_r500 ? 511 : 4;
353848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
354848b8605Smrg            return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
355848b8605Smrg            /* Fragment shader limits. */
356848b8605Smrg        case PIPE_SHADER_CAP_MAX_INPUTS:
357848b8605Smrg            /* 2 colors + 8 texcoords are always supported
358848b8605Smrg             * (minus fog and wpos).
359848b8605Smrg             *
360848b8605Smrg             * R500 has the ability to turn 3rd and 4th color into
361848b8605Smrg             * additional texcoords but there is no two-sided color
362848b8605Smrg             * selection then. However the facing bit can be used instead. */
363848b8605Smrg            return 10;
364b8e80941Smrg        case PIPE_SHADER_CAP_MAX_OUTPUTS:
365b8e80941Smrg            return 4;
366848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
367848b8605Smrg            return (is_r500 ? 256 : 32) * sizeof(float[4]);
368848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
369b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
370848b8605Smrg            return 1;
371848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEMPS:
372848b8605Smrg            return is_r500 ? 128 : is_r400 ? 64 : 32;
373848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
374848b8605Smrg        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
375848b8605Smrg           return r300screen->caps.num_tex_units;
376848b8605Smrg        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
377848b8605Smrg        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
378848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
379848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
380848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
381848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
382848b8605Smrg        case PIPE_SHADER_CAP_SUBROUTINES:
383848b8605Smrg        case PIPE_SHADER_CAP_INTEGERS:
384b8e80941Smrg        case PIPE_SHADER_CAP_INT64_ATOMICS:
385b8e80941Smrg        case PIPE_SHADER_CAP_FP16:
386b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
387b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
388b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
389b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
390b8e80941Smrg        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
391b8e80941Smrg        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
392b8e80941Smrg        case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
393b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
394b8e80941Smrg        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
395b8e80941Smrg        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
396848b8605Smrg            return 0;
397b8e80941Smrg        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
398b8e80941Smrg            return 32;
399848b8605Smrg        case PIPE_SHADER_CAP_PREFERRED_IR:
400848b8605Smrg            return PIPE_SHADER_IR_TGSI;
401b8e80941Smrg        case PIPE_SHADER_CAP_SUPPORTED_IRS:
402b8e80941Smrg            return 0;
403b8e80941Smrg        case PIPE_SHADER_CAP_SCALAR_ISA:
404b8e80941Smrg            return 0;
405848b8605Smrg        }
406848b8605Smrg        break;
407848b8605Smrg    case PIPE_SHADER_VERTEX:
408848b8605Smrg        switch (param)
409848b8605Smrg        {
410848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
411848b8605Smrg        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
412848b8605Smrg        case PIPE_SHADER_CAP_SUBROUTINES:
413848b8605Smrg            return 0;
414848b8605Smrg        default:;
415848b8605Smrg        }
416848b8605Smrg
417848b8605Smrg        if (!r300screen->caps.has_tcl) {
418848b8605Smrg            return draw_get_shader_param(shader, param);
419848b8605Smrg        }
420848b8605Smrg
421848b8605Smrg        switch (param)
422848b8605Smrg        {
423848b8605Smrg        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
424848b8605Smrg        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
425848b8605Smrg            return is_r500 ? 1024 : 256;
426848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
427848b8605Smrg            return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
428848b8605Smrg        case PIPE_SHADER_CAP_MAX_INPUTS:
429848b8605Smrg            return 16;
430b8e80941Smrg        case PIPE_SHADER_CAP_MAX_OUTPUTS:
431b8e80941Smrg            return 10;
432848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
433848b8605Smrg            return 256 * sizeof(float[4]);
434848b8605Smrg        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
435848b8605Smrg            return 1;
436848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEMPS:
437848b8605Smrg            return 32;
438848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
439b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
440848b8605Smrg            return 1;
441848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
442848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
443848b8605Smrg        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
444848b8605Smrg        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
445848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
446848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
447848b8605Smrg        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
448848b8605Smrg        case PIPE_SHADER_CAP_SUBROUTINES:
449848b8605Smrg        case PIPE_SHADER_CAP_INTEGERS:
450b8e80941Smrg        case PIPE_SHADER_CAP_FP16:
451b8e80941Smrg        case PIPE_SHADER_CAP_INT64_ATOMICS:
452848b8605Smrg        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
453848b8605Smrg        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
454b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
455b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
456b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
457b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
458b8e80941Smrg        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
459b8e80941Smrg        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
460b8e80941Smrg        case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
461b8e80941Smrg        case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
462b8e80941Smrg        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
463b8e80941Smrg        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
464848b8605Smrg            return 0;
465b8e80941Smrg        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
466b8e80941Smrg            return 32;
467848b8605Smrg        case PIPE_SHADER_CAP_PREFERRED_IR:
468848b8605Smrg            return PIPE_SHADER_IR_TGSI;
469b8e80941Smrg        case PIPE_SHADER_CAP_SUPPORTED_IRS:
470b8e80941Smrg            return 0;
471b8e80941Smrg        case PIPE_SHADER_CAP_SCALAR_ISA:
472b8e80941Smrg            return 0;
473848b8605Smrg        }
474848b8605Smrg        break;
475b8e80941Smrg    default:
476b8e80941Smrg        ; /* nothing */
477848b8605Smrg    }
478848b8605Smrg    return 0;
479848b8605Smrg}
480848b8605Smrg
481848b8605Smrgstatic float r300_get_paramf(struct pipe_screen* pscreen,
482848b8605Smrg                             enum pipe_capf param)
483848b8605Smrg{
484848b8605Smrg    struct r300_screen* r300screen = r300_screen(pscreen);
485848b8605Smrg
486848b8605Smrg    switch (param) {
487848b8605Smrg        case PIPE_CAPF_MAX_LINE_WIDTH:
488848b8605Smrg        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
489848b8605Smrg        case PIPE_CAPF_MAX_POINT_WIDTH:
490848b8605Smrg        case PIPE_CAPF_MAX_POINT_WIDTH_AA:
491848b8605Smrg            /* The maximum dimensions of the colorbuffer are our practical
492848b8605Smrg             * rendering limits. 2048 pixels should be enough for anybody. */
493848b8605Smrg            if (r300screen->caps.is_r500) {
494848b8605Smrg                return 4096.0f;
495848b8605Smrg            } else if (r300screen->caps.is_r400) {
496848b8605Smrg                return 4021.0f;
497848b8605Smrg            } else {
498848b8605Smrg                return 2560.0f;
499848b8605Smrg            }
500848b8605Smrg        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
501848b8605Smrg            return 16.0f;
502848b8605Smrg        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
503848b8605Smrg            return 16.0f;
504b8e80941Smrg        case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
505b8e80941Smrg        case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
506b8e80941Smrg        case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
507848b8605Smrg            return 0.0f;
508848b8605Smrg        default:
509848b8605Smrg            debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
510848b8605Smrg                         param);
511848b8605Smrg            return 0.0f;
512848b8605Smrg    }
513848b8605Smrg}
514848b8605Smrg
515848b8605Smrgstatic int r300_get_video_param(struct pipe_screen *screen,
516848b8605Smrg				enum pipe_video_profile profile,
517848b8605Smrg				enum pipe_video_entrypoint entrypoint,
518848b8605Smrg				enum pipe_video_cap param)
519848b8605Smrg{
520848b8605Smrg   switch (param) {
521848b8605Smrg      case PIPE_VIDEO_CAP_SUPPORTED:
522848b8605Smrg         return vl_profile_supported(screen, profile, entrypoint);
523848b8605Smrg      case PIPE_VIDEO_CAP_NPOT_TEXTURES:
524848b8605Smrg         return 0;
525848b8605Smrg      case PIPE_VIDEO_CAP_MAX_WIDTH:
526848b8605Smrg      case PIPE_VIDEO_CAP_MAX_HEIGHT:
527848b8605Smrg         return vl_video_buffer_max_size(screen);
528848b8605Smrg      case PIPE_VIDEO_CAP_PREFERED_FORMAT:
529848b8605Smrg         return PIPE_FORMAT_NV12;
530848b8605Smrg      case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
531848b8605Smrg         return false;
532848b8605Smrg      case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
533848b8605Smrg         return false;
534848b8605Smrg      case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
535848b8605Smrg         return true;
536848b8605Smrg      case PIPE_VIDEO_CAP_MAX_LEVEL:
537848b8605Smrg         return vl_level_supported(screen, profile);
538848b8605Smrg      default:
539848b8605Smrg         return 0;
540848b8605Smrg   }
541848b8605Smrg}
542848b8605Smrg
543848b8605Smrg/**
544848b8605Smrg * Whether the format matches:
545848b8605Smrg *   PIPE_FORMAT_?10?10?10?2_UNORM
546848b8605Smrg */
547b8e80941Smrgstatic inline boolean
548848b8605Smrgutil_format_is_rgba1010102_variant(const struct util_format_description *desc)
549848b8605Smrg{
550848b8605Smrg   static const unsigned size[4] = {10, 10, 10, 2};
551848b8605Smrg   unsigned chan;
552848b8605Smrg
553848b8605Smrg   if (desc->block.width != 1 ||
554848b8605Smrg       desc->block.height != 1 ||
555848b8605Smrg       desc->block.bits != 32)
556848b8605Smrg      return FALSE;
557848b8605Smrg
558848b8605Smrg   for (chan = 0; chan < 4; ++chan) {
559848b8605Smrg      if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
560848b8605Smrg         desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
561848b8605Smrg         return FALSE;
562848b8605Smrg      if (desc->channel[chan].size != size[chan])
563848b8605Smrg         return FALSE;
564848b8605Smrg   }
565848b8605Smrg
566848b8605Smrg   return TRUE;
567848b8605Smrg}
568848b8605Smrg
569b8e80941Smrgstatic bool r300_is_blending_supported(struct r300_screen *rscreen,
570b8e80941Smrg                                       enum pipe_format format)
571b8e80941Smrg{
572b8e80941Smrg    int c;
573b8e80941Smrg    const struct util_format_description *desc =
574b8e80941Smrg        util_format_description(format);
575b8e80941Smrg
576b8e80941Smrg    if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
577b8e80941Smrg        return false;
578b8e80941Smrg
579b8e80941Smrg    c = util_format_get_first_non_void_channel(format);
580b8e80941Smrg
581b8e80941Smrg    /* RGBA16F */
582b8e80941Smrg    if (rscreen->caps.is_r500 &&
583b8e80941Smrg        desc->nr_channels == 4 &&
584b8e80941Smrg        desc->channel[c].size == 16 &&
585b8e80941Smrg        desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
586b8e80941Smrg        return true;
587b8e80941Smrg
588b8e80941Smrg    if (desc->channel[c].normalized &&
589b8e80941Smrg        desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
590b8e80941Smrg        desc->channel[c].size >= 4 &&
591b8e80941Smrg        desc->channel[c].size <= 10) {
592b8e80941Smrg        /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
593b8e80941Smrg        if (desc->nr_channels >= 3)
594b8e80941Smrg            return true;
595b8e80941Smrg
596b8e80941Smrg        if (format == PIPE_FORMAT_R8G8_UNORM)
597b8e80941Smrg            return true;
598b8e80941Smrg
599b8e80941Smrg        /* R8, I8, L8, A8 */
600b8e80941Smrg        if (desc->nr_channels == 1)
601b8e80941Smrg            return true;
602b8e80941Smrg    }
603b8e80941Smrg
604b8e80941Smrg    return false;
605b8e80941Smrg}
606b8e80941Smrg
607848b8605Smrgstatic boolean r300_is_format_supported(struct pipe_screen* screen,
608848b8605Smrg                                        enum pipe_format format,
609848b8605Smrg                                        enum pipe_texture_target target,
610848b8605Smrg                                        unsigned sample_count,
611b8e80941Smrg                                        unsigned storage_sample_count,
612848b8605Smrg                                        unsigned usage)
613848b8605Smrg{
614848b8605Smrg    uint32_t retval = 0;
615848b8605Smrg    boolean is_r500 = r300_screen(screen)->caps.is_r500;
616848b8605Smrg    boolean is_r400 = r300_screen(screen)->caps.is_r400;
617848b8605Smrg    boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
618848b8605Smrg                              format == PIPE_FORMAT_R10G10B10X2_SNORM ||
619848b8605Smrg                              format == PIPE_FORMAT_B10G10R10A2_UNORM ||
620848b8605Smrg                              format == PIPE_FORMAT_B10G10R10X2_UNORM ||
621848b8605Smrg                              format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
622848b8605Smrg    boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
623848b8605Smrg                       format == PIPE_FORMAT_RGTC1_SNORM ||
624848b8605Smrg                       format == PIPE_FORMAT_LATC1_UNORM ||
625848b8605Smrg                       format == PIPE_FORMAT_LATC1_SNORM;
626848b8605Smrg    boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
627848b8605Smrg                       format == PIPE_FORMAT_RGTC2_SNORM ||
628848b8605Smrg                       format == PIPE_FORMAT_LATC2_UNORM ||
629848b8605Smrg                       format == PIPE_FORMAT_LATC2_SNORM;
630848b8605Smrg    boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
631848b8605Smrg                            format == PIPE_FORMAT_R16G16_FLOAT ||
632848b8605Smrg                            format == PIPE_FORMAT_R16G16B16_FLOAT ||
633848b8605Smrg                            format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
634848b8605Smrg                            format == PIPE_FORMAT_R16G16B16X16_FLOAT;
635848b8605Smrg    const struct util_format_description *desc;
636848b8605Smrg
637b8e80941Smrg    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
638b8e80941Smrg        return false;
639848b8605Smrg
640848b8605Smrg    /* Check multisampling support. */
641848b8605Smrg    switch (sample_count) {
642848b8605Smrg        case 0:
643848b8605Smrg        case 1:
644848b8605Smrg            break;
645848b8605Smrg        case 2:
646848b8605Smrg        case 4:
647848b8605Smrg        case 6:
648848b8605Smrg            /* No texturing and scanout. */
649848b8605Smrg            if (usage & (PIPE_BIND_SAMPLER_VIEW |
650848b8605Smrg                         PIPE_BIND_DISPLAY_TARGET |
651848b8605Smrg                         PIPE_BIND_SCANOUT)) {
652848b8605Smrg                return FALSE;
653848b8605Smrg            }
654848b8605Smrg
655848b8605Smrg            desc = util_format_description(format);
656848b8605Smrg
657848b8605Smrg            if (is_r500) {
658848b8605Smrg                /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
659848b8605Smrg                if (!util_format_is_depth_or_stencil(format) &&
660848b8605Smrg                    !util_format_is_rgba8_variant(desc) &&
661848b8605Smrg                    !util_format_is_rgba1010102_variant(desc) &&
662848b8605Smrg                    format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
663848b8605Smrg                    format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
664848b8605Smrg                    return FALSE;
665848b8605Smrg                }
666848b8605Smrg            } else {
667848b8605Smrg                /* Only allow depth/stencil, RGBA8. */
668848b8605Smrg                if (!util_format_is_depth_or_stencil(format) &&
669848b8605Smrg                    !util_format_is_rgba8_variant(desc)) {
670848b8605Smrg                    return FALSE;
671848b8605Smrg                }
672848b8605Smrg            }
673848b8605Smrg            break;
674848b8605Smrg        default:
675848b8605Smrg            return FALSE;
676848b8605Smrg    }
677848b8605Smrg
678848b8605Smrg    /* Check sampler format support. */
679848b8605Smrg    if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
680848b8605Smrg        /* these two are broken for an unknown reason */
681848b8605Smrg        format != PIPE_FORMAT_R8G8B8X8_SNORM &&
682848b8605Smrg        format != PIPE_FORMAT_R16G16B16X16_SNORM &&
683848b8605Smrg        /* ATI1N is r5xx-only. */
684848b8605Smrg        (is_r500 || !is_ati1n) &&
685848b8605Smrg        /* ATI2N is supported on r4xx-r5xx. */
686848b8605Smrg        (is_r400 || is_r500 || !is_ati2n) &&
687848b8605Smrg        r300_is_sampler_format_supported(format)) {
688848b8605Smrg        retval |= PIPE_BIND_SAMPLER_VIEW;
689848b8605Smrg    }
690848b8605Smrg
691848b8605Smrg    /* Check colorbuffer format support. */
692848b8605Smrg    if ((usage & (PIPE_BIND_RENDER_TARGET |
693848b8605Smrg                  PIPE_BIND_DISPLAY_TARGET |
694848b8605Smrg                  PIPE_BIND_SCANOUT |
695b8e80941Smrg                  PIPE_BIND_SHARED |
696b8e80941Smrg                  PIPE_BIND_BLENDABLE)) &&
697848b8605Smrg        /* 2101010 cannot be rendered to on non-r5xx. */
698b8e80941Smrg        (!is_color2101010 || is_r500) &&
699848b8605Smrg        r300_is_colorbuffer_format_supported(format)) {
700848b8605Smrg        retval |= usage &
701848b8605Smrg            (PIPE_BIND_RENDER_TARGET |
702848b8605Smrg             PIPE_BIND_DISPLAY_TARGET |
703848b8605Smrg             PIPE_BIND_SCANOUT |
704848b8605Smrg             PIPE_BIND_SHARED);
705b8e80941Smrg
706b8e80941Smrg        if (r300_is_blending_supported(r300_screen(screen), format)) {
707b8e80941Smrg            retval |= usage & PIPE_BIND_BLENDABLE;
708b8e80941Smrg        }
709848b8605Smrg    }
710848b8605Smrg
711848b8605Smrg    /* Check depth-stencil format support. */
712848b8605Smrg    if (usage & PIPE_BIND_DEPTH_STENCIL &&
713848b8605Smrg        r300_is_zs_format_supported(format)) {
714848b8605Smrg        retval |= PIPE_BIND_DEPTH_STENCIL;
715848b8605Smrg    }
716848b8605Smrg
717848b8605Smrg    /* Check vertex buffer format support. */
718848b8605Smrg    if (usage & PIPE_BIND_VERTEX_BUFFER) {
719848b8605Smrg        if (r300_screen(screen)->caps.has_tcl) {
720848b8605Smrg            /* Half float is supported on >= R400. */
721848b8605Smrg            if ((is_r400 || is_r500 || !is_half_float) &&
722848b8605Smrg                r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
723848b8605Smrg                retval |= PIPE_BIND_VERTEX_BUFFER;
724848b8605Smrg            }
725848b8605Smrg        } else {
726848b8605Smrg            /* SW TCL */
727848b8605Smrg            if (!util_format_is_pure_integer(format)) {
728848b8605Smrg                retval |= PIPE_BIND_VERTEX_BUFFER;
729848b8605Smrg            }
730848b8605Smrg        }
731848b8605Smrg    }
732848b8605Smrg
733848b8605Smrg    return retval == usage;
734848b8605Smrg}
735848b8605Smrg
736848b8605Smrgstatic void r300_destroy_screen(struct pipe_screen* pscreen)
737848b8605Smrg{
738848b8605Smrg    struct r300_screen* r300screen = r300_screen(pscreen);
739848b8605Smrg    struct radeon_winsys *rws = radeon_winsys(pscreen);
740848b8605Smrg
741848b8605Smrg    if (rws && !rws->unref(rws))
742848b8605Smrg      return;
743848b8605Smrg
744b8e80941Smrg    mtx_destroy(&r300screen->cmask_mutex);
745b8e80941Smrg    slab_destroy_parent(&r300screen->pool_transfers);
746848b8605Smrg
747848b8605Smrg    if (rws)
748848b8605Smrg      rws->destroy(rws);
749848b8605Smrg
750848b8605Smrg    FREE(r300screen);
751848b8605Smrg}
752848b8605Smrg
753848b8605Smrgstatic void r300_fence_reference(struct pipe_screen *screen,
754848b8605Smrg                                 struct pipe_fence_handle **ptr,
755848b8605Smrg                                 struct pipe_fence_handle *fence)
756848b8605Smrg{
757848b8605Smrg    struct radeon_winsys *rws = r300_screen(screen)->rws;
758848b8605Smrg
759848b8605Smrg    rws->fence_reference(ptr, fence);
760848b8605Smrg}
761848b8605Smrg
762848b8605Smrgstatic boolean r300_fence_finish(struct pipe_screen *screen,
763b8e80941Smrg                                 struct pipe_context *ctx,
764848b8605Smrg                                 struct pipe_fence_handle *fence,
765848b8605Smrg                                 uint64_t timeout)
766848b8605Smrg{
767848b8605Smrg    struct radeon_winsys *rws = r300_screen(screen)->rws;
768848b8605Smrg
769848b8605Smrg    return rws->fence_wait(rws, fence, timeout);
770848b8605Smrg}
771848b8605Smrg
772b8e80941Smrgstruct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
773b8e80941Smrg                                       const struct pipe_screen_config *config)
774848b8605Smrg{
775848b8605Smrg    struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
776848b8605Smrg
777848b8605Smrg    if (!r300screen) {
778848b8605Smrg        FREE(r300screen);
779848b8605Smrg        return NULL;
780848b8605Smrg    }
781848b8605Smrg
782848b8605Smrg    rws->query_info(rws, &r300screen->info);
783848b8605Smrg
784848b8605Smrg    r300_init_debug(r300screen);
785848b8605Smrg    r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
786848b8605Smrg
787848b8605Smrg    if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
788848b8605Smrg        r300screen->caps.zmask_ram = 0;
789848b8605Smrg    if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
790848b8605Smrg        r300screen->caps.hiz_ram = 0;
791848b8605Smrg
792848b8605Smrg    r300screen->rws = rws;
793848b8605Smrg    r300screen->screen.destroy = r300_destroy_screen;
794848b8605Smrg    r300screen->screen.get_name = r300_get_name;
795848b8605Smrg    r300screen->screen.get_vendor = r300_get_vendor;
796b8e80941Smrg    r300screen->screen.get_device_vendor = r300_get_device_vendor;
797848b8605Smrg    r300screen->screen.get_param = r300_get_param;
798848b8605Smrg    r300screen->screen.get_shader_param = r300_get_shader_param;
799848b8605Smrg    r300screen->screen.get_paramf = r300_get_paramf;
800848b8605Smrg    r300screen->screen.get_video_param = r300_get_video_param;
801848b8605Smrg    r300screen->screen.is_format_supported = r300_is_format_supported;
802848b8605Smrg    r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
803848b8605Smrg    r300screen->screen.context_create = r300_create_context;
804848b8605Smrg    r300screen->screen.fence_reference = r300_fence_reference;
805848b8605Smrg    r300screen->screen.fence_finish = r300_fence_finish;
806848b8605Smrg
807848b8605Smrg    r300_init_screen_resource_functions(r300screen);
808848b8605Smrg
809b8e80941Smrg    slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
810b8e80941Smrg
811b8e80941Smrg    (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
812848b8605Smrg
813848b8605Smrg    return &r300screen->screen;
814848b8605Smrg}
815