r600_asm.c revision 848b8605
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_sq.h" 24#include "r600_opcodes.h" 25#include "r600_formats.h" 26#include "r600_shader.h" 27#include "r600d.h" 28 29#include <errno.h> 30#include "util/u_dump.h" 31#include "util/u_memory.h" 32#include "util/u_math.h" 33#include "pipe/p_shader_tokens.h" 34 35#include "sb/sb_public.h" 36 37#define NUM_OF_CYCLES 3 38#define NUM_OF_COMPONENTS 4 39 40static inline unsigned int r600_bytecode_get_num_operands( 41 struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 42{ 43 return r600_isa_alu(alu->op)->src_count; 44} 45 46int r700_bytecode_alu_build(struct r600_bytecode *bc, 47 struct r600_bytecode_alu *alu, unsigned id); 48 49static struct r600_bytecode_cf *r600_bytecode_cf(void) 50{ 51 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf); 52 53 if (cf == NULL) 54 return NULL; 55 LIST_INITHEAD(&cf->list); 56 LIST_INITHEAD(&cf->alu); 57 LIST_INITHEAD(&cf->vtx); 58 LIST_INITHEAD(&cf->tex); 59 return cf; 60} 61 62static struct r600_bytecode_alu *r600_bytecode_alu(void) 63{ 64 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu); 65 66 if (alu == NULL) 67 return NULL; 68 LIST_INITHEAD(&alu->list); 69 return alu; 70} 71 72static struct r600_bytecode_vtx *r600_bytecode_vtx(void) 73{ 74 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx); 75 76 if (vtx == NULL) 77 return NULL; 78 LIST_INITHEAD(&vtx->list); 79 return vtx; 80} 81 82static struct r600_bytecode_tex *r600_bytecode_tex(void) 83{ 84 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex); 85 86 if (tex == NULL) 87 return NULL; 88 LIST_INITHEAD(&tex->list); 89 return tex; 90} 91 92static unsigned stack_entry_size(enum radeon_family chip) { 93 /* Wavefront size: 94 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/ 95 * Aruba/Sumo/Sumo2/redwood/juniper 96 * 32: R630/R730/R710/Palm/Cedar 97 * 16: R610/Rs780 98 * 99 * Stack row size: 100 * Wavefront Size 16 32 48 64 101 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4 102 * Columns per Row (R9xx+) 8 4 4 4 */ 103 104 switch (chip) { 105 /* FIXME: are some chips missing here? */ 106 /* wavefront size 16 */ 107 case CHIP_RV610: 108 case CHIP_RS780: 109 case CHIP_RV620: 110 case CHIP_RS880: 111 /* wavefront size 32 */ 112 case CHIP_RV630: 113 case CHIP_RV635: 114 case CHIP_RV730: 115 case CHIP_RV710: 116 case CHIP_PALM: 117 case CHIP_CEDAR: 118 return 8; 119 120 /* wavefront size 64 */ 121 default: 122 return 4; 123 } 124} 125 126void r600_bytecode_init(struct r600_bytecode *bc, 127 enum chip_class chip_class, 128 enum radeon_family family, 129 bool has_compressed_msaa_texturing) 130{ 131 static unsigned next_shader_id = 0; 132 133 bc->debug_id = ++next_shader_id; 134 135 if ((chip_class == R600) && 136 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) { 137 bc->ar_handling = AR_HANDLE_RV6XX; 138 bc->r6xx_nop_after_rel_dst = 1; 139 } else { 140 bc->ar_handling = AR_HANDLE_NORMAL; 141 bc->r6xx_nop_after_rel_dst = 0; 142 } 143 144 LIST_INITHEAD(&bc->cf); 145 bc->chip_class = chip_class; 146 bc->family = family; 147 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing; 148 bc->stack.entry_size = stack_entry_size(family); 149} 150 151int r600_bytecode_add_cf(struct r600_bytecode *bc) 152{ 153 struct r600_bytecode_cf *cf = r600_bytecode_cf(); 154 155 if (cf == NULL) 156 return -ENOMEM; 157 LIST_ADDTAIL(&cf->list, &bc->cf); 158 if (bc->cf_last) { 159 cf->id = bc->cf_last->id + 2; 160 if (bc->cf_last->eg_alu_extended) { 161 /* take into account extended alu size */ 162 cf->id += 2; 163 bc->ndw += 2; 164 } 165 } 166 bc->cf_last = cf; 167 bc->ncf++; 168 bc->ndw += 2; 169 bc->force_add_cf = 0; 170 bc->ar_loaded = 0; 171 return 0; 172} 173 174int r600_bytecode_add_output(struct r600_bytecode *bc, 175 const struct r600_bytecode_output *output) 176{ 177 int r; 178 179 if (output->gpr >= bc->ngpr) 180 bc->ngpr = output->gpr + 1; 181 182 if (bc->cf_last && (bc->cf_last->op == output->op || 183 (bc->cf_last->op == CF_OP_EXPORT && 184 output->op == CF_OP_EXPORT_DONE)) && 185 output->type == bc->cf_last->output.type && 186 output->elem_size == bc->cf_last->output.elem_size && 187 output->swizzle_x == bc->cf_last->output.swizzle_x && 188 output->swizzle_y == bc->cf_last->output.swizzle_y && 189 output->swizzle_z == bc->cf_last->output.swizzle_z && 190 output->swizzle_w == bc->cf_last->output.swizzle_w && 191 output->comp_mask == bc->cf_last->output.comp_mask && 192 (output->burst_count + bc->cf_last->output.burst_count) <= 16) { 193 194 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr && 195 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) { 196 197 bc->cf_last->op = bc->cf_last->output.op = output->op; 198 bc->cf_last->output.gpr = output->gpr; 199 bc->cf_last->output.array_base = output->array_base; 200 bc->cf_last->output.burst_count += output->burst_count; 201 return 0; 202 203 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) && 204 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) { 205 206 bc->cf_last->op = bc->cf_last->output.op = output->op; 207 bc->cf_last->output.burst_count += output->burst_count; 208 return 0; 209 } 210 } 211 212 r = r600_bytecode_add_cf(bc); 213 if (r) 214 return r; 215 bc->cf_last->op = output->op; 216 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output)); 217 bc->cf_last->barrier = 1; 218 return 0; 219} 220 221/* alu instructions that can ony exits once per group */ 222static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 223{ 224 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED); 225} 226 227static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 228{ 229 return (r600_isa_alu(alu->op)->flags & AF_REPL) && 230 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V); 231} 232 233static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 234{ 235 return r600_isa_alu(alu->op)->flags & AF_MOVA; 236} 237 238static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 239{ 240 unsigned num_src = r600_bytecode_get_num_operands(bc, alu); 241 unsigned src; 242 243 if (alu->dst.rel) { 244 return 1; 245 } 246 247 for (src = 0; src < num_src; ++src) { 248 if (alu->src[src].rel) { 249 return 1; 250 } 251 } 252 return 0; 253} 254 255static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 256{ 257 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op); 258 return !(slots & AF_S); 259} 260 261static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 262{ 263 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op); 264 return !(slots & AF_V); 265} 266 267/* alu instructions that can execute on any unit */ 268static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 269{ 270 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op); 271 return slots == AF_VS; 272} 273 274static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu) 275{ 276 return alu->op == ALU_OP0_NOP; 277} 278 279static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first, 280 struct r600_bytecode_alu *assignment[5]) 281{ 282 struct r600_bytecode_alu *alu; 283 unsigned i, chan, trans; 284 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; 285 286 for (i = 0; i < max_slots; i++) 287 assignment[i] = NULL; 288 289 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) { 290 chan = alu->dst.chan; 291 if (max_slots == 4) 292 trans = 0; 293 else if (is_alu_trans_unit_inst(bc, alu)) 294 trans = 1; 295 else if (is_alu_vec_unit_inst(bc, alu)) 296 trans = 0; 297 else if (assignment[chan]) 298 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */ 299 else 300 trans = 0; 301 302 if (trans) { 303 if (assignment[4]) { 304 assert(0); /* ALU.Trans has already been allocated. */ 305 return -1; 306 } 307 assignment[4] = alu; 308 } else { 309 if (assignment[chan]) { 310 assert(0); /* ALU.chan has already been allocated. */ 311 return -1; 312 } 313 assignment[chan] = alu; 314 } 315 316 if (alu->last) 317 break; 318 } 319 return 0; 320} 321 322struct alu_bank_swizzle { 323 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS]; 324 int hw_cfile_addr[4]; 325 int hw_cfile_elem[4]; 326}; 327 328static const unsigned cycle_for_bank_swizzle_vec[][3] = { 329 [SQ_ALU_VEC_012] = { 0, 1, 2 }, 330 [SQ_ALU_VEC_021] = { 0, 2, 1 }, 331 [SQ_ALU_VEC_120] = { 1, 2, 0 }, 332 [SQ_ALU_VEC_102] = { 1, 0, 2 }, 333 [SQ_ALU_VEC_201] = { 2, 0, 1 }, 334 [SQ_ALU_VEC_210] = { 2, 1, 0 } 335}; 336 337static const unsigned cycle_for_bank_swizzle_scl[][3] = { 338 [SQ_ALU_SCL_210] = { 2, 1, 0 }, 339 [SQ_ALU_SCL_122] = { 1, 2, 2 }, 340 [SQ_ALU_SCL_212] = { 2, 1, 2 }, 341 [SQ_ALU_SCL_221] = { 2, 2, 1 } 342}; 343 344static void init_bank_swizzle(struct alu_bank_swizzle *bs) 345{ 346 int i, cycle, component; 347 /* set up gpr use */ 348 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++) 349 for (component = 0; component < NUM_OF_COMPONENTS; component++) 350 bs->hw_gpr[cycle][component] = -1; 351 for (i = 0; i < 4; i++) 352 bs->hw_cfile_addr[i] = -1; 353 for (i = 0; i < 4; i++) 354 bs->hw_cfile_elem[i] = -1; 355} 356 357static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle) 358{ 359 if (bs->hw_gpr[cycle][chan] == -1) 360 bs->hw_gpr[cycle][chan] = sel; 361 else if (bs->hw_gpr[cycle][chan] != (int)sel) { 362 /* Another scalar operation has already used the GPR read port for the channel. */ 363 return -1; 364 } 365 return 0; 366} 367 368static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan) 369{ 370 int res, num_res = 4; 371 if (bc->chip_class >= R700) { 372 num_res = 2; 373 chan /= 2; 374 } 375 for (res = 0; res < num_res; ++res) { 376 if (bs->hw_cfile_addr[res] == -1) { 377 bs->hw_cfile_addr[res] = sel; 378 bs->hw_cfile_elem[res] = chan; 379 return 0; 380 } else if (bs->hw_cfile_addr[res] == sel && 381 bs->hw_cfile_elem[res] == chan) 382 return 0; /* Read for this scalar element already reserved, nothing to do here. */ 383 } 384 /* All cfile read ports are used, cannot reference vector element. */ 385 return -1; 386} 387 388static int is_gpr(unsigned sel) 389{ 390 return (sel <= 127); 391} 392 393/* CB constants start at 512, and get translated to a kcache index when ALU 394 * clauses are constructed. Note that we handle kcache constants the same way 395 * as (the now gone) cfile constants, is that really required? */ 396static int is_cfile(unsigned sel) 397{ 398 return (sel > 255 && sel < 512) || 399 (sel > 511 && sel < 4607) || /* Kcache before translation. */ 400 (sel > 127 && sel < 192); /* Kcache after translation. */ 401} 402 403static int is_const(int sel) 404{ 405 return is_cfile(sel) || 406 (sel >= V_SQ_ALU_SRC_0 && 407 sel <= V_SQ_ALU_SRC_LITERAL); 408} 409 410static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, 411 struct alu_bank_swizzle *bs, int bank_swizzle) 412{ 413 int r, src, num_src, sel, elem, cycle; 414 415 num_src = r600_bytecode_get_num_operands(bc, alu); 416 for (src = 0; src < num_src; src++) { 417 sel = alu->src[src].sel; 418 elem = alu->src[src].chan; 419 if (is_gpr(sel)) { 420 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src]; 421 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan) 422 /* Nothing to do; special-case optimization, 423 * second source uses first source’s reservation. */ 424 continue; 425 else { 426 r = reserve_gpr(bs, sel, elem, cycle); 427 if (r) 428 return r; 429 } 430 } else if (is_cfile(sel)) { 431 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem); 432 if (r) 433 return r; 434 } 435 /* No restrictions on PV, PS, literal or special constants. */ 436 } 437 return 0; 438} 439 440static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, 441 struct alu_bank_swizzle *bs, int bank_swizzle) 442{ 443 int r, src, num_src, const_count, sel, elem, cycle; 444 445 num_src = r600_bytecode_get_num_operands(bc, alu); 446 for (const_count = 0, src = 0; src < num_src; ++src) { 447 sel = alu->src[src].sel; 448 elem = alu->src[src].chan; 449 if (is_const(sel)) { /* Any constant, including literal and inline constants. */ 450 if (const_count >= 2) 451 /* More than two references to a constant in 452 * transcendental operation. */ 453 return -1; 454 else 455 const_count++; 456 } 457 if (is_cfile(sel)) { 458 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem); 459 if (r) 460 return r; 461 } 462 } 463 for (src = 0; src < num_src; ++src) { 464 sel = alu->src[src].sel; 465 elem = alu->src[src].chan; 466 if (is_gpr(sel)) { 467 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; 468 if (cycle < const_count) 469 /* Cycle for GPR load conflicts with 470 * constant load in transcendental operation. */ 471 return -1; 472 r = reserve_gpr(bs, sel, elem, cycle); 473 if (r) 474 return r; 475 } 476 /* PV PS restrictions */ 477 if (const_count && (sel == 254 || sel == 255)) { 478 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; 479 if (cycle < const_count) 480 return -1; 481 } 482 } 483 return 0; 484} 485 486static int check_and_set_bank_swizzle(struct r600_bytecode *bc, 487 struct r600_bytecode_alu *slots[5]) 488{ 489 struct alu_bank_swizzle bs; 490 int bank_swizzle[5]; 491 int i, r = 0, forced = 1; 492 boolean scalar_only = bc->chip_class == CAYMAN ? false : true; 493 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; 494 495 for (i = 0; i < max_slots; i++) { 496 if (slots[i]) { 497 if (slots[i]->bank_swizzle_force) { 498 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force; 499 } else { 500 forced = 0; 501 } 502 } 503 504 if (i < 4 && slots[i]) 505 scalar_only = false; 506 } 507 if (forced) 508 return 0; 509 510 /* Just check every possible combination of bank swizzle. 511 * Not very efficent, but works on the first try in most of the cases. */ 512 for (i = 0; i < 4; i++) 513 if (!slots[i] || !slots[i]->bank_swizzle_force) 514 bank_swizzle[i] = SQ_ALU_VEC_012; 515 else 516 bank_swizzle[i] = slots[i]->bank_swizzle; 517 518 bank_swizzle[4] = SQ_ALU_SCL_210; 519 while(bank_swizzle[4] <= SQ_ALU_SCL_221) { 520 521 init_bank_swizzle(&bs); 522 if (scalar_only == false) { 523 for (i = 0; i < 4; i++) { 524 if (slots[i]) { 525 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]); 526 if (r) 527 break; 528 } 529 } 530 } else 531 r = 0; 532 533 if (!r && max_slots == 5 && slots[4]) { 534 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]); 535 } 536 if (!r) { 537 for (i = 0; i < max_slots; i++) { 538 if (slots[i]) 539 slots[i]->bank_swizzle = bank_swizzle[i]; 540 } 541 return 0; 542 } 543 544 if (scalar_only) { 545 bank_swizzle[4]++; 546 } else { 547 for (i = 0; i < max_slots; i++) { 548 if (!slots[i] || !slots[i]->bank_swizzle_force) { 549 bank_swizzle[i]++; 550 if (bank_swizzle[i] <= SQ_ALU_VEC_210) 551 break; 552 else if (i < max_slots - 1) 553 bank_swizzle[i] = SQ_ALU_VEC_012; 554 else 555 return -1; 556 } 557 } 558 } 559 } 560 561 /* Couldn't find a working swizzle. */ 562 return -1; 563} 564 565static int replace_gpr_with_pv_ps(struct r600_bytecode *bc, 566 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev) 567{ 568 struct r600_bytecode_alu *prev[5]; 569 int gpr[5], chan[5]; 570 int i, j, r, src, num_src; 571 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; 572 573 r = assign_alu_units(bc, alu_prev, prev); 574 if (r) 575 return r; 576 577 for (i = 0; i < max_slots; ++i) { 578 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) { 579 gpr[i] = prev[i]->dst.sel; 580 /* cube writes more than PV.X */ 581 if (is_alu_reduction_inst(bc, prev[i])) 582 chan[i] = 0; 583 else 584 chan[i] = prev[i]->dst.chan; 585 } else 586 gpr[i] = -1; 587 } 588 589 for (i = 0; i < max_slots; ++i) { 590 struct r600_bytecode_alu *alu = slots[i]; 591 if(!alu) 592 continue; 593 594 num_src = r600_bytecode_get_num_operands(bc, alu); 595 for (src = 0; src < num_src; ++src) { 596 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel) 597 continue; 598 599 if (bc->chip_class < CAYMAN) { 600 if (alu->src[src].sel == gpr[4] && 601 alu->src[src].chan == chan[4] && 602 alu_prev->pred_sel == alu->pred_sel) { 603 alu->src[src].sel = V_SQ_ALU_SRC_PS; 604 alu->src[src].chan = 0; 605 continue; 606 } 607 } 608 609 for (j = 0; j < 4; ++j) { 610 if (alu->src[src].sel == gpr[j] && 611 alu->src[src].chan == j && 612 alu_prev->pred_sel == alu->pred_sel) { 613 alu->src[src].sel = V_SQ_ALU_SRC_PV; 614 alu->src[src].chan = chan[j]; 615 break; 616 } 617 } 618 } 619 } 620 621 return 0; 622} 623 624void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg) 625{ 626 switch(value) { 627 case 0: 628 *sel = V_SQ_ALU_SRC_0; 629 break; 630 case 1: 631 *sel = V_SQ_ALU_SRC_1_INT; 632 break; 633 case -1: 634 *sel = V_SQ_ALU_SRC_M_1_INT; 635 break; 636 case 0x3F800000: /* 1.0f */ 637 *sel = V_SQ_ALU_SRC_1; 638 break; 639 case 0x3F000000: /* 0.5f */ 640 *sel = V_SQ_ALU_SRC_0_5; 641 break; 642 case 0xBF800000: /* -1.0f */ 643 *sel = V_SQ_ALU_SRC_1; 644 *neg ^= 1; 645 break; 646 case 0xBF000000: /* -0.5f */ 647 *sel = V_SQ_ALU_SRC_0_5; 648 *neg ^= 1; 649 break; 650 default: 651 *sel = V_SQ_ALU_SRC_LITERAL; 652 break; 653 } 654} 655 656/* compute how many literal are needed */ 657static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, 658 uint32_t literal[4], unsigned *nliteral) 659{ 660 unsigned num_src = r600_bytecode_get_num_operands(bc, alu); 661 unsigned i, j; 662 663 for (i = 0; i < num_src; ++i) { 664 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) { 665 uint32_t value = alu->src[i].value; 666 unsigned found = 0; 667 for (j = 0; j < *nliteral; ++j) { 668 if (literal[j] == value) { 669 found = 1; 670 break; 671 } 672 } 673 if (!found) { 674 if (*nliteral >= 4) 675 return -EINVAL; 676 literal[(*nliteral)++] = value; 677 } 678 } 679 } 680 return 0; 681} 682 683static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc, 684 struct r600_bytecode_alu *alu, 685 uint32_t literal[4], unsigned nliteral) 686{ 687 unsigned num_src = r600_bytecode_get_num_operands(bc, alu); 688 unsigned i, j; 689 690 for (i = 0; i < num_src; ++i) { 691 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) { 692 uint32_t value = alu->src[i].value; 693 for (j = 0; j < nliteral; ++j) { 694 if (literal[j] == value) { 695 alu->src[i].chan = j; 696 break; 697 } 698 } 699 } 700 } 701} 702 703static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5], 704 struct r600_bytecode_alu *alu_prev) 705{ 706 struct r600_bytecode_alu *prev[5]; 707 struct r600_bytecode_alu *result[5] = { NULL }; 708 709 uint32_t literal[4], prev_literal[4]; 710 unsigned nliteral = 0, prev_nliteral = 0; 711 712 int i, j, r, src, num_src; 713 int num_once_inst = 0; 714 int have_mova = 0, have_rel = 0; 715 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; 716 717 r = assign_alu_units(bc, alu_prev, prev); 718 if (r) 719 return r; 720 721 for (i = 0; i < max_slots; ++i) { 722 if (prev[i]) { 723 if (prev[i]->pred_sel) 724 return 0; 725 if (is_alu_once_inst(bc, prev[i])) 726 return 0; 727 } 728 if (slots[i]) { 729 if (slots[i]->pred_sel) 730 return 0; 731 if (is_alu_once_inst(bc, slots[i])) 732 return 0; 733 } 734 } 735 736 for (i = 0; i < max_slots; ++i) { 737 struct r600_bytecode_alu *alu; 738 739 if (num_once_inst > 0) 740 return 0; 741 742 /* check number of literals */ 743 if (prev[i]) { 744 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral)) 745 return 0; 746 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral)) 747 return 0; 748 if (is_alu_mova_inst(bc, prev[i])) { 749 if (have_rel) 750 return 0; 751 have_mova = 1; 752 } 753 754 if (alu_uses_rel(bc, prev[i])) { 755 if (have_mova) { 756 return 0; 757 } 758 have_rel = 1; 759 } 760 761 num_once_inst += is_alu_once_inst(bc, prev[i]); 762 } 763 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral)) 764 return 0; 765 766 /* Let's check used slots. */ 767 if (prev[i] && !slots[i]) { 768 result[i] = prev[i]; 769 continue; 770 } else if (prev[i] && slots[i]) { 771 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) { 772 /* Trans unit is still free try to use it. */ 773 if (is_alu_any_unit_inst(bc, slots[i])) { 774 result[i] = prev[i]; 775 result[4] = slots[i]; 776 } else if (is_alu_any_unit_inst(bc, prev[i])) { 777 if (slots[i]->dst.sel == prev[i]->dst.sel && 778 (slots[i]->dst.write == 1 || slots[i]->is_op3) && 779 (prev[i]->dst.write == 1 || prev[i]->is_op3)) 780 return 0; 781 782 result[i] = slots[i]; 783 result[4] = prev[i]; 784 } else 785 return 0; 786 } else 787 return 0; 788 } else if(!slots[i]) { 789 continue; 790 } else { 791 if (max_slots == 5 && slots[i] && prev[4] && 792 slots[i]->dst.sel == prev[4]->dst.sel && 793 slots[i]->dst.chan == prev[4]->dst.chan && 794 (slots[i]->dst.write == 1 || slots[i]->is_op3) && 795 (prev[4]->dst.write == 1 || prev[4]->is_op3)) 796 return 0; 797 798 result[i] = slots[i]; 799 } 800 801 alu = slots[i]; 802 num_once_inst += is_alu_once_inst(bc, alu); 803 804 /* don't reschedule NOPs */ 805 if (is_nop_inst(bc, alu)) 806 return 0; 807 808 if (is_alu_mova_inst(bc, alu)) { 809 if (have_rel) { 810 return 0; 811 } 812 have_mova = 1; 813 } 814 815 if (alu_uses_rel(bc, alu)) { 816 if (have_mova) { 817 return 0; 818 } 819 have_rel = 1; 820 } 821 822 /* Let's check source gprs */ 823 num_src = r600_bytecode_get_num_operands(bc, alu); 824 for (src = 0; src < num_src; ++src) { 825 826 /* Constants don't matter. */ 827 if (!is_gpr(alu->src[src].sel)) 828 continue; 829 830 for (j = 0; j < max_slots; ++j) { 831 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3)) 832 continue; 833 834 /* If it's relative then we can't determin which gpr is really used. */ 835 if (prev[j]->dst.chan == alu->src[src].chan && 836 (prev[j]->dst.sel == alu->src[src].sel || 837 prev[j]->dst.rel || alu->src[src].rel)) 838 return 0; 839 } 840 } 841 } 842 843 /* more than one PRED_ or KILL_ ? */ 844 if (num_once_inst > 1) 845 return 0; 846 847 /* check if the result can still be swizzlet */ 848 r = check_and_set_bank_swizzle(bc, result); 849 if (r) 850 return 0; 851 852 /* looks like everything worked out right, apply the changes */ 853 854 /* undo adding previus literals */ 855 bc->cf_last->ndw -= align(prev_nliteral, 2); 856 857 /* sort instructions */ 858 for (i = 0; i < max_slots; ++i) { 859 slots[i] = result[i]; 860 if (result[i]) { 861 LIST_DEL(&result[i]->list); 862 result[i]->last = 0; 863 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu); 864 } 865 } 866 867 /* determine new last instruction */ 868 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1; 869 870 /* determine new first instruction */ 871 for (i = 0; i < max_slots; ++i) { 872 if (result[i]) { 873 bc->cf_last->curr_bs_head = result[i]; 874 break; 875 } 876 } 877 878 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head; 879 bc->cf_last->prev2_bs_head = NULL; 880 881 return 0; 882} 883 884/* we'll keep kcache sets sorted by bank & addr */ 885static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc, 886 struct r600_bytecode_kcache *kcache, 887 unsigned bank, unsigned line) 888{ 889 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2; 890 891 for (i = 0; i < kcache_banks; i++) { 892 if (kcache[i].mode) { 893 int d; 894 895 if (kcache[i].bank < bank) 896 continue; 897 898 if ((kcache[i].bank == bank && kcache[i].addr > line+1) || 899 kcache[i].bank > bank) { 900 /* try to insert new line */ 901 if (kcache[kcache_banks-1].mode) { 902 /* all sets are in use */ 903 return -ENOMEM; 904 } 905 906 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache)); 907 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1; 908 kcache[i].bank = bank; 909 kcache[i].addr = line; 910 return 0; 911 } 912 913 d = line - kcache[i].addr; 914 915 if (d == -1) { 916 kcache[i].addr--; 917 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) { 918 /* we are prepending the line to the current set, 919 * discarding the existing second line, 920 * so we'll have to insert line+2 after it */ 921 line += 2; 922 continue; 923 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) { 924 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2; 925 return 0; 926 } else { 927 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */ 928 return -ENOMEM; 929 } 930 } else if (d == 1) { 931 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2; 932 return 0; 933 } else if (d == 0) 934 return 0; 935 } else { /* free kcache set - use it */ 936 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1; 937 kcache[i].bank = bank; 938 kcache[i].addr = line; 939 return 0; 940 } 941 } 942 return -ENOMEM; 943} 944 945static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc, 946 struct r600_bytecode_kcache *kcache, 947 struct r600_bytecode_alu *alu) 948{ 949 int i, r; 950 951 for (i = 0; i < 3; i++) { 952 unsigned bank, line, sel = alu->src[i].sel; 953 954 if (sel < 512) 955 continue; 956 957 bank = alu->src[i].kc_bank; 958 line = (sel-512)>>4; 959 960 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line))) 961 return r; 962 } 963 return 0; 964} 965 966static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc, 967 struct r600_bytecode_alu *alu, 968 struct r600_bytecode_kcache * kcache) 969{ 970 int i, j; 971 972 /* Alter the src operands to refer to the kcache. */ 973 for (i = 0; i < 3; ++i) { 974 static const unsigned int base[] = {128, 160, 256, 288}; 975 unsigned int line, sel = alu->src[i].sel, found = 0; 976 977 if (sel < 512) 978 continue; 979 980 sel -= 512; 981 line = sel>>4; 982 983 for (j = 0; j < 4 && !found; ++j) { 984 switch (kcache[j].mode) { 985 case V_SQ_CF_KCACHE_NOP: 986 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX: 987 R600_ERR("unexpected kcache line mode\n"); 988 return -ENOMEM; 989 default: 990 if (kcache[j].bank == alu->src[i].kc_bank && 991 kcache[j].addr <= line && 992 line < kcache[j].addr + kcache[j].mode) { 993 alu->src[i].sel = sel - (kcache[j].addr<<4); 994 alu->src[i].sel += base[j]; 995 found=1; 996 } 997 } 998 } 999 } 1000 return 0; 1001} 1002 1003static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, 1004 struct r600_bytecode_alu *alu, 1005 unsigned type) 1006{ 1007 struct r600_bytecode_kcache kcache_sets[4]; 1008 struct r600_bytecode_kcache *kcache = kcache_sets; 1009 int r; 1010 1011 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache)); 1012 1013 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) { 1014 /* can't alloc, need to start new clause */ 1015 if ((r = r600_bytecode_add_cf(bc))) { 1016 return r; 1017 } 1018 bc->cf_last->op = type; 1019 1020 /* retry with the new clause */ 1021 kcache = bc->cf_last->kcache; 1022 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) { 1023 /* can't alloc again- should never happen */ 1024 return r; 1025 } 1026 } else { 1027 /* update kcache sets */ 1028 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache)); 1029 } 1030 1031 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */ 1032 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) { 1033 if (bc->chip_class < EVERGREEN) 1034 return -ENOMEM; 1035 bc->cf_last->eg_alu_extended = 1; 1036 } 1037 1038 return 0; 1039} 1040 1041static int insert_nop_r6xx(struct r600_bytecode *bc) 1042{ 1043 struct r600_bytecode_alu alu; 1044 int r, i; 1045 1046 for (i = 0; i < 4; i++) { 1047 memset(&alu, 0, sizeof(alu)); 1048 alu.op = ALU_OP0_NOP; 1049 alu.src[0].chan = i; 1050 alu.dst.chan = i; 1051 alu.last = (i == 3); 1052 r = r600_bytecode_add_alu(bc, &alu); 1053 if (r) 1054 return r; 1055 } 1056 return 0; 1057} 1058 1059/* load AR register from gpr (bc->ar_reg) with MOVA_INT */ 1060static int load_ar_r6xx(struct r600_bytecode *bc) 1061{ 1062 struct r600_bytecode_alu alu; 1063 int r; 1064 1065 if (bc->ar_loaded) 1066 return 0; 1067 1068 /* hack to avoid making MOVA the last instruction in the clause */ 1069 if ((bc->cf_last->ndw>>1) >= 110) 1070 bc->force_add_cf = 1; 1071 1072 memset(&alu, 0, sizeof(alu)); 1073 alu.op = ALU_OP1_MOVA_GPR_INT; 1074 alu.src[0].sel = bc->ar_reg; 1075 alu.src[0].chan = bc->ar_chan; 1076 alu.last = 1; 1077 alu.index_mode = INDEX_MODE_LOOP; 1078 r = r600_bytecode_add_alu(bc, &alu); 1079 if (r) 1080 return r; 1081 1082 /* no requirement to set uses waterfall on MOVA_GPR_INT */ 1083 bc->ar_loaded = 1; 1084 return 0; 1085} 1086 1087/* load AR register from gpr (bc->ar_reg) with MOVA_INT */ 1088static int load_ar(struct r600_bytecode *bc) 1089{ 1090 struct r600_bytecode_alu alu; 1091 int r; 1092 1093 if (bc->ar_handling) 1094 return load_ar_r6xx(bc); 1095 1096 if (bc->ar_loaded) 1097 return 0; 1098 1099 /* hack to avoid making MOVA the last instruction in the clause */ 1100 if ((bc->cf_last->ndw>>1) >= 110) 1101 bc->force_add_cf = 1; 1102 1103 memset(&alu, 0, sizeof(alu)); 1104 alu.op = ALU_OP1_MOVA_INT; 1105 alu.src[0].sel = bc->ar_reg; 1106 alu.src[0].chan = bc->ar_chan; 1107 alu.last = 1; 1108 r = r600_bytecode_add_alu(bc, &alu); 1109 if (r) 1110 return r; 1111 1112 bc->cf_last->r6xx_uses_waterfall = 1; 1113 bc->ar_loaded = 1; 1114 return 0; 1115} 1116 1117int r600_bytecode_add_alu_type(struct r600_bytecode *bc, 1118 const struct r600_bytecode_alu *alu, unsigned type) 1119{ 1120 struct r600_bytecode_alu *nalu = r600_bytecode_alu(); 1121 struct r600_bytecode_alu *lalu; 1122 int i, r; 1123 1124 if (nalu == NULL) 1125 return -ENOMEM; 1126 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu)); 1127 1128 if (bc->cf_last != NULL && bc->cf_last->op != type) { 1129 /* check if we could add it anyway */ 1130 if (bc->cf_last->op == CF_OP_ALU && 1131 type == CF_OP_ALU_PUSH_BEFORE) { 1132 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) { 1133 if (lalu->execute_mask) { 1134 bc->force_add_cf = 1; 1135 break; 1136 } 1137 } 1138 } else 1139 bc->force_add_cf = 1; 1140 } 1141 1142 /* cf can contains only alu or only vtx or only tex */ 1143 if (bc->cf_last == NULL || bc->force_add_cf) { 1144 r = r600_bytecode_add_cf(bc); 1145 if (r) { 1146 free(nalu); 1147 return r; 1148 } 1149 } 1150 bc->cf_last->op = type; 1151 1152 /* Check AR usage and load it if required */ 1153 for (i = 0; i < 3; i++) 1154 if (nalu->src[i].rel && !bc->ar_loaded) 1155 load_ar(bc); 1156 1157 if (nalu->dst.rel && !bc->ar_loaded) 1158 load_ar(bc); 1159 1160 /* Setup the kcache for this ALU instruction. This will start a new 1161 * ALU clause if needed. */ 1162 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) { 1163 free(nalu); 1164 return r; 1165 } 1166 1167 if (!bc->cf_last->curr_bs_head) { 1168 bc->cf_last->curr_bs_head = nalu; 1169 } 1170 /* number of gpr == the last gpr used in any alu */ 1171 for (i = 0; i < 3; i++) { 1172 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) { 1173 bc->ngpr = nalu->src[i].sel + 1; 1174 } 1175 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL) 1176 r600_bytecode_special_constants(nalu->src[i].value, 1177 &nalu->src[i].sel, &nalu->src[i].neg); 1178 } 1179 if (nalu->dst.sel >= bc->ngpr) { 1180 bc->ngpr = nalu->dst.sel + 1; 1181 } 1182 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu); 1183 /* each alu use 2 dwords */ 1184 bc->cf_last->ndw += 2; 1185 bc->ndw += 2; 1186 1187 /* process cur ALU instructions for bank swizzle */ 1188 if (nalu->last) { 1189 uint32_t literal[4]; 1190 unsigned nliteral; 1191 struct r600_bytecode_alu *slots[5]; 1192 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; 1193 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots); 1194 if (r) 1195 return r; 1196 1197 if (bc->cf_last->prev_bs_head) { 1198 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head); 1199 if (r) 1200 return r; 1201 } 1202 1203 if (bc->cf_last->prev_bs_head) { 1204 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head); 1205 if (r) 1206 return r; 1207 } 1208 1209 r = check_and_set_bank_swizzle(bc, slots); 1210 if (r) 1211 return r; 1212 1213 for (i = 0, nliteral = 0; i < max_slots; i++) { 1214 if (slots[i]) { 1215 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral); 1216 if (r) 1217 return r; 1218 } 1219 } 1220 bc->cf_last->ndw += align(nliteral, 2); 1221 1222 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots) 1223 * worst case */ 1224 if ((bc->cf_last->ndw >> 1) >= 120) { 1225 bc->force_add_cf = 1; 1226 } 1227 1228 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head; 1229 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head; 1230 bc->cf_last->curr_bs_head = NULL; 1231 } 1232 1233 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst) 1234 insert_nop_r6xx(bc); 1235 1236 return 0; 1237} 1238 1239int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu) 1240{ 1241 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU); 1242} 1243 1244static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc) 1245{ 1246 switch (bc->chip_class) { 1247 case R600: 1248 return 8; 1249 1250 case R700: 1251 case EVERGREEN: 1252 case CAYMAN: 1253 return 16; 1254 1255 default: 1256 R600_ERR("Unknown chip class %d.\n", bc->chip_class); 1257 return 8; 1258 } 1259} 1260 1261static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc) 1262{ 1263 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) && 1264 (bc->chip_class == CAYMAN || 1265 bc->cf_last->op != CF_OP_TEX)); 1266} 1267 1268int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx) 1269{ 1270 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx(); 1271 int r; 1272 1273 if (nvtx == NULL) 1274 return -ENOMEM; 1275 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx)); 1276 1277 /* cf can contains only alu or only vtx or only tex */ 1278 if (bc->cf_last == NULL || 1279 last_inst_was_not_vtx_fetch(bc) || 1280 bc->force_add_cf) { 1281 r = r600_bytecode_add_cf(bc); 1282 if (r) { 1283 free(nvtx); 1284 return r; 1285 } 1286 switch (bc->chip_class) { 1287 case R600: 1288 case R700: 1289 case EVERGREEN: 1290 bc->cf_last->op = CF_OP_VTX; 1291 break; 1292 case CAYMAN: 1293 bc->cf_last->op = CF_OP_TEX; 1294 break; 1295 default: 1296 R600_ERR("Unknown chip class %d.\n", bc->chip_class); 1297 free(nvtx); 1298 return -EINVAL; 1299 } 1300 } 1301 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx); 1302 /* each fetch use 4 dwords */ 1303 bc->cf_last->ndw += 4; 1304 bc->ndw += 4; 1305 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc)) 1306 bc->force_add_cf = 1; 1307 1308 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1); 1309 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1); 1310 1311 return 0; 1312} 1313 1314int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex) 1315{ 1316 struct r600_bytecode_tex *ntex = r600_bytecode_tex(); 1317 int r; 1318 1319 if (ntex == NULL) 1320 return -ENOMEM; 1321 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex)); 1322 1323 /* we can't fetch data und use it as texture lookup address in the same TEX clause */ 1324 if (bc->cf_last != NULL && 1325 bc->cf_last->op == CF_OP_TEX) { 1326 struct r600_bytecode_tex *ttex; 1327 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) { 1328 if (ttex->dst_gpr == ntex->src_gpr) { 1329 bc->force_add_cf = 1; 1330 break; 1331 } 1332 } 1333 /* slight hack to make gradients always go into same cf */ 1334 if (ntex->op == FETCH_OP_SET_GRADIENTS_H) 1335 bc->force_add_cf = 1; 1336 } 1337 1338 /* cf can contains only alu or only vtx or only tex */ 1339 if (bc->cf_last == NULL || 1340 bc->cf_last->op != CF_OP_TEX || 1341 bc->force_add_cf) { 1342 r = r600_bytecode_add_cf(bc); 1343 if (r) { 1344 free(ntex); 1345 return r; 1346 } 1347 bc->cf_last->op = CF_OP_TEX; 1348 } 1349 if (ntex->src_gpr >= bc->ngpr) { 1350 bc->ngpr = ntex->src_gpr + 1; 1351 } 1352 if (ntex->dst_gpr >= bc->ngpr) { 1353 bc->ngpr = ntex->dst_gpr + 1; 1354 } 1355 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex); 1356 /* each texture fetch use 4 dwords */ 1357 bc->cf_last->ndw += 4; 1358 bc->ndw += 4; 1359 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc)) 1360 bc->force_add_cf = 1; 1361 return 0; 1362} 1363 1364int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op) 1365{ 1366 int r; 1367 r = r600_bytecode_add_cf(bc); 1368 if (r) 1369 return r; 1370 1371 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE; 1372 bc->cf_last->op = op; 1373 return 0; 1374} 1375 1376int cm_bytecode_add_cf_end(struct r600_bytecode *bc) 1377{ 1378 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END); 1379} 1380 1381/* common to all 3 families */ 1382static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id) 1383{ 1384 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) | 1385 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) | 1386 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) | 1387 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x); 1388 if (bc->chip_class < CAYMAN) 1389 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count); 1390 id++; 1391 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) | 1392 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) | 1393 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) | 1394 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) | 1395 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) | 1396 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) | 1397 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) | 1398 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) | 1399 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) | 1400 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr); 1401 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)| 1402 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian); 1403 if (bc->chip_class < CAYMAN) 1404 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1); 1405 id++; 1406 bc->bytecode[id++] = 0; 1407 return 0; 1408} 1409 1410/* common to all 3 families */ 1411static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id) 1412{ 1413 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST( 1414 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) | 1415 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) | 1416 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) | 1417 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) | 1418 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel); 1419 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) | 1420 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) | 1421 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) | 1422 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) | 1423 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) | 1424 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) | 1425 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) | 1426 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) | 1427 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) | 1428 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) | 1429 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w); 1430 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) | 1431 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) | 1432 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) | 1433 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) | 1434 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) | 1435 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) | 1436 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) | 1437 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w); 1438 bc->bytecode[id++] = 0; 1439 return 0; 1440} 1441 1442/* r600 only, r700/eg bits in r700_asm.c */ 1443static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id) 1444{ 1445 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op); 1446 1447 /* don't replace gpr by pv or ps for destination register */ 1448 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | 1449 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | 1450 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | 1451 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | 1452 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | 1453 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | 1454 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | 1455 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | 1456 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) | 1457 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | 1458 S_SQ_ALU_WORD0_LAST(alu->last); 1459 1460 if (alu->is_op3) { 1461 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 1462 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 1463 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 1464 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 1465 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | 1466 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | 1467 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | 1468 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | 1469 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) | 1470 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); 1471 } else { 1472 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 1473 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 1474 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 1475 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 1476 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) | 1477 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | 1478 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | 1479 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) | 1480 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) | 1481 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | 1482 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) | 1483 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); 1484 } 1485 return 0; 1486} 1487 1488static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf) 1489{ 1490 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1); 1491 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) | 1492 S_SQ_CF_WORD1_BARRIER(1) | 1493 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1); 1494} 1495 1496/* common for r600/r700 - eg in eg_asm.c */ 1497static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) 1498{ 1499 unsigned id = cf->id; 1500 const struct cf_op_info *cfop = r600_isa_cf(cf->op); 1501 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op); 1502 1503 1504 if (cf->op == CF_NATIVE) { 1505 bc->bytecode[id++] = cf->isa[0]; 1506 bc->bytecode[id++] = cf->isa[1]; 1507 } else if (cfop->flags & CF_ALU) { 1508 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) | 1509 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) | 1510 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) | 1511 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank); 1512 1513 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) | 1514 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) | 1515 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) | 1516 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) | 1517 S_SQ_CF_ALU_WORD1_BARRIER(1) | 1518 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) | 1519 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); 1520 } else if (cfop->flags & CF_FETCH) { 1521 if (bc->chip_class == R700) 1522 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf); 1523 else 1524 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf); 1525 } else if (cfop->flags & CF_EXP) { 1526 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) | 1527 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) | 1528 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) | 1529 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) | 1530 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr); 1531 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) | 1532 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) | 1533 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) | 1534 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) | 1535 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) | 1536 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) | 1537 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) | 1538 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); 1539 } else if (cfop->flags & CF_MEM) { 1540 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) | 1541 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) | 1542 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) | 1543 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) | 1544 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr); 1545 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) | 1546 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) | 1547 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) | 1548 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) | 1549 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) | 1550 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask); 1551 } else { 1552 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1); 1553 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) | 1554 S_SQ_CF_WORD1_BARRIER(1) | 1555 S_SQ_CF_WORD1_COND(cf->cond) | 1556 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) | 1557 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program); 1558 } 1559 return 0; 1560} 1561 1562int r600_bytecode_build(struct r600_bytecode *bc) 1563{ 1564 struct r600_bytecode_cf *cf; 1565 struct r600_bytecode_alu *alu; 1566 struct r600_bytecode_vtx *vtx; 1567 struct r600_bytecode_tex *tex; 1568 uint32_t literal[4]; 1569 unsigned nliteral; 1570 unsigned addr; 1571 int i, r; 1572 1573 if (!bc->nstack) // If not 0, Stack_size already provided by llvm 1574 bc->nstack = bc->stack.max_entries; 1575 1576 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) { 1577 bc->nstack = 1; 1578 } 1579 1580 /* first path compute addr of each CF block */ 1581 /* addr start after all the CF instructions */ 1582 addr = bc->cf_last->id + 2; 1583 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) { 1584 if (r600_isa_cf(cf->op)->flags & CF_FETCH) { 1585 addr += 3; 1586 addr &= 0xFFFFFFFCUL; 1587 } 1588 cf->addr = addr; 1589 addr += cf->ndw; 1590 bc->ndw = cf->addr + cf->ndw; 1591 } 1592 free(bc->bytecode); 1593 bc->bytecode = calloc(1, bc->ndw * 4); 1594 if (bc->bytecode == NULL) 1595 return -ENOMEM; 1596 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) { 1597 const struct cf_op_info *cfop = r600_isa_cf(cf->op); 1598 addr = cf->addr; 1599 if (bc->chip_class >= EVERGREEN) 1600 r = eg_bytecode_cf_build(bc, cf); 1601 else 1602 r = r600_bytecode_cf_build(bc, cf); 1603 if (r) 1604 return r; 1605 if (cfop->flags & CF_ALU) { 1606 nliteral = 0; 1607 memset(literal, 0, sizeof(literal)); 1608 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) { 1609 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral); 1610 if (r) 1611 return r; 1612 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral); 1613 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache); 1614 1615 switch(bc->chip_class) { 1616 case R600: 1617 r = r600_bytecode_alu_build(bc, alu, addr); 1618 break; 1619 case R700: 1620 case EVERGREEN: /* eg alu is same encoding as r700 */ 1621 case CAYMAN: 1622 r = r700_bytecode_alu_build(bc, alu, addr); 1623 break; 1624 default: 1625 R600_ERR("unknown chip class %d.\n", bc->chip_class); 1626 return -EINVAL; 1627 } 1628 if (r) 1629 return r; 1630 addr += 2; 1631 if (alu->last) { 1632 for (i = 0; i < align(nliteral, 2); ++i) { 1633 bc->bytecode[addr++] = literal[i]; 1634 } 1635 nliteral = 0; 1636 memset(literal, 0, sizeof(literal)); 1637 } 1638 } 1639 } else if (cf->op == CF_OP_VTX) { 1640 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) { 1641 r = r600_bytecode_vtx_build(bc, vtx, addr); 1642 if (r) 1643 return r; 1644 addr += 4; 1645 } 1646 } else if (cf->op == CF_OP_TEX) { 1647 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) { 1648 assert(bc->chip_class >= EVERGREEN); 1649 r = r600_bytecode_vtx_build(bc, vtx, addr); 1650 if (r) 1651 return r; 1652 addr += 4; 1653 } 1654 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) { 1655 r = r600_bytecode_tex_build(bc, tex, addr); 1656 if (r) 1657 return r; 1658 addr += 4; 1659 } 1660 } 1661 } 1662 return 0; 1663} 1664 1665void r600_bytecode_clear(struct r600_bytecode *bc) 1666{ 1667 struct r600_bytecode_cf *cf = NULL, *next_cf; 1668 1669 free(bc->bytecode); 1670 bc->bytecode = NULL; 1671 1672 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) { 1673 struct r600_bytecode_alu *alu = NULL, *next_alu; 1674 struct r600_bytecode_tex *tex = NULL, *next_tex; 1675 struct r600_bytecode_tex *vtx = NULL, *next_vtx; 1676 1677 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) { 1678 free(alu); 1679 } 1680 1681 LIST_INITHEAD(&cf->alu); 1682 1683 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) { 1684 free(tex); 1685 } 1686 1687 LIST_INITHEAD(&cf->tex); 1688 1689 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) { 1690 free(vtx); 1691 } 1692 1693 LIST_INITHEAD(&cf->vtx); 1694 1695 free(cf); 1696 } 1697 1698 LIST_INITHEAD(&cf->list); 1699} 1700 1701static int print_swizzle(unsigned swz) 1702{ 1703 const char * swzchars = "xyzw01?_"; 1704 assert(swz<8 && swz != 6); 1705 return fprintf(stderr, "%c", swzchars[swz]); 1706} 1707 1708static int print_sel(unsigned sel, unsigned rel, unsigned index_mode, 1709 unsigned need_brackets) 1710{ 1711 int o = 0; 1712 if (rel && index_mode >= 5 && sel < 128) 1713 o += fprintf(stderr, "G"); 1714 if (rel || need_brackets) { 1715 o += fprintf(stderr, "["); 1716 } 1717 o += fprintf(stderr, "%d", sel); 1718 if (rel) { 1719 if (index_mode == 0 || index_mode == 6) 1720 o += fprintf(stderr, "+AR"); 1721 else if (index_mode == 4) 1722 o += fprintf(stderr, "+AL"); 1723 } 1724 if (rel || need_brackets) { 1725 o += fprintf(stderr, "]"); 1726 } 1727 return o; 1728} 1729 1730static int print_dst(struct r600_bytecode_alu *alu) 1731{ 1732 int o = 0; 1733 unsigned sel = alu->dst.sel; 1734 char reg_char = 'R'; 1735 if (sel > 128 - 4) { /* clause temporary gpr */ 1736 sel -= 128 - 4; 1737 reg_char = 'T'; 1738 } 1739 1740 if (alu->dst.write || alu->is_op3) { 1741 o += fprintf(stderr, "%c", reg_char); 1742 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0); 1743 } else { 1744 o += fprintf(stderr, "__"); 1745 } 1746 o += fprintf(stderr, "."); 1747 o += print_swizzle(alu->dst.chan); 1748 return o; 1749} 1750 1751static int print_src(struct r600_bytecode_alu *alu, unsigned idx) 1752{ 1753 int o = 0; 1754 struct r600_bytecode_alu_src *src = &alu->src[idx]; 1755 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0; 1756 1757 if (src->neg) 1758 o += fprintf(stderr,"-"); 1759 if (src->abs) 1760 o += fprintf(stderr,"|"); 1761 1762 if (sel < 128 - 4) { 1763 o += fprintf(stderr, "R"); 1764 } else if (sel < 128) { 1765 o += fprintf(stderr, "T"); 1766 sel -= 128 - 4; 1767 } else if (sel < 160) { 1768 o += fprintf(stderr, "KC0"); 1769 need_brackets = 1; 1770 sel -= 128; 1771 } else if (sel < 192) { 1772 o += fprintf(stderr, "KC1"); 1773 need_brackets = 1; 1774 sel -= 160; 1775 } else if (sel >= 512) { 1776 o += fprintf(stderr, "C%d", src->kc_bank); 1777 need_brackets = 1; 1778 sel -= 512; 1779 } else if (sel >= 448) { 1780 o += fprintf(stderr, "Param"); 1781 sel -= 448; 1782 need_chan = 0; 1783 } else if (sel >= 288) { 1784 o += fprintf(stderr, "KC3"); 1785 need_brackets = 1; 1786 sel -= 288; 1787 } else if (sel >= 256) { 1788 o += fprintf(stderr, "KC2"); 1789 need_brackets = 1; 1790 sel -= 256; 1791 } else { 1792 need_sel = 0; 1793 need_chan = 0; 1794 switch (sel) { 1795 case V_SQ_ALU_SRC_PS: 1796 o += fprintf(stderr, "PS"); 1797 break; 1798 case V_SQ_ALU_SRC_PV: 1799 o += fprintf(stderr, "PV"); 1800 need_chan = 1; 1801 break; 1802 case V_SQ_ALU_SRC_LITERAL: 1803 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value); 1804 break; 1805 case V_SQ_ALU_SRC_0_5: 1806 o += fprintf(stderr, "0.5"); 1807 break; 1808 case V_SQ_ALU_SRC_M_1_INT: 1809 o += fprintf(stderr, "-1"); 1810 break; 1811 case V_SQ_ALU_SRC_1_INT: 1812 o += fprintf(stderr, "1"); 1813 break; 1814 case V_SQ_ALU_SRC_1: 1815 o += fprintf(stderr, "1.0"); 1816 break; 1817 case V_SQ_ALU_SRC_0: 1818 o += fprintf(stderr, "0"); 1819 break; 1820 default: 1821 o += fprintf(stderr, "??IMM_%d", sel); 1822 break; 1823 } 1824 } 1825 1826 if (need_sel) 1827 o += print_sel(sel, src->rel, alu->index_mode, need_brackets); 1828 1829 if (need_chan) { 1830 o += fprintf(stderr, "."); 1831 o += print_swizzle(src->chan); 1832 } 1833 1834 if (src->abs) 1835 o += fprintf(stderr,"|"); 1836 1837 return o; 1838} 1839 1840static int print_indent(int p, int c) 1841{ 1842 int o = 0; 1843 while (p++ < c) 1844 o += fprintf(stderr, " "); 1845 return o; 1846} 1847 1848void r600_bytecode_disasm(struct r600_bytecode *bc) 1849{ 1850 static int index = 0; 1851 struct r600_bytecode_cf *cf = NULL; 1852 struct r600_bytecode_alu *alu = NULL; 1853 struct r600_bytecode_vtx *vtx = NULL; 1854 struct r600_bytecode_tex *tex = NULL; 1855 1856 unsigned i, id, ngr = 0, last; 1857 uint32_t literal[4]; 1858 unsigned nliteral; 1859 char chip = '6'; 1860 1861 switch (bc->chip_class) { 1862 case R700: 1863 chip = '7'; 1864 break; 1865 case EVERGREEN: 1866 chip = 'E'; 1867 break; 1868 case CAYMAN: 1869 chip = 'C'; 1870 break; 1871 case R600: 1872 default: 1873 chip = '6'; 1874 break; 1875 } 1876 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n", 1877 bc->ndw, bc->ngpr, bc->nstack); 1878 fprintf(stderr, "shader %d -- %c\n", index++, chip); 1879 1880 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) { 1881 id = cf->id; 1882 if (cf->op == CF_NATIVE) { 1883 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id], 1884 bc->bytecode[id + 1]); 1885 } else { 1886 const struct cf_op_info *cfop = r600_isa_cf(cf->op); 1887 if (cfop->flags & CF_ALU) { 1888 if (cf->eg_alu_extended) { 1889 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id], 1890 bc->bytecode[id + 1], "ALU_EXT"); 1891 id += 2; 1892 } 1893 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id], 1894 bc->bytecode[id + 1], cfop->name); 1895 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr); 1896 for (i = 0; i < 4; ++i) { 1897 if (cf->kcache[i].mode) { 1898 int c_start = (cf->kcache[i].addr << 4); 1899 int c_end = c_start + (cf->kcache[i].mode << 4); 1900 fprintf(stderr, "KC%d[CB%d:%d-%d] ", 1901 i, cf->kcache[i].bank, c_start, c_end); 1902 } 1903 } 1904 fprintf(stderr, "\n"); 1905 } else if (cfop->flags & CF_FETCH) { 1906 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id], 1907 bc->bytecode[id + 1], cfop->name); 1908 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr); 1909 fprintf(stderr, "\n"); 1910 } else if (cfop->flags & CF_EXP) { 1911 int o = 0; 1912 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"}; 1913 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id], 1914 bc->bytecode[id + 1], cfop->name); 1915 o += print_indent(o, 43); 1916 o += fprintf(stderr, "%s ", exp_type[cf->output.type]); 1917 if (cf->output.burst_count > 1) { 1918 o += fprintf(stderr, "%d-%d ", cf->output.array_base, 1919 cf->output.array_base + cf->output.burst_count - 1); 1920 1921 o += print_indent(o, 55); 1922 o += fprintf(stderr, "R%d-%d.", cf->output.gpr, 1923 cf->output.gpr + cf->output.burst_count - 1); 1924 } else { 1925 o += fprintf(stderr, "%d ", cf->output.array_base); 1926 o += print_indent(o, 55); 1927 o += fprintf(stderr, "R%d.", cf->output.gpr); 1928 } 1929 1930 o += print_swizzle(cf->output.swizzle_x); 1931 o += print_swizzle(cf->output.swizzle_y); 1932 o += print_swizzle(cf->output.swizzle_z); 1933 o += print_swizzle(cf->output.swizzle_w); 1934 1935 print_indent(o, 67); 1936 1937 fprintf(stderr, " ES:%X ", cf->output.elem_size); 1938 if (!cf->barrier) 1939 fprintf(stderr, "NO_BARRIER "); 1940 if (cf->end_of_program) 1941 fprintf(stderr, "EOP "); 1942 fprintf(stderr, "\n"); 1943 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) { 1944 int o = 0; 1945 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK", 1946 "WRITE_IND_ACK"}; 1947 o += fprintf(stderr, "%04d %08X %08X %s ", id, 1948 bc->bytecode[id], bc->bytecode[id + 1], cfop->name); 1949 o += print_indent(o, 43); 1950 o += fprintf(stderr, "%s ", exp_type[cf->output.type]); 1951 if (cf->output.burst_count > 1) { 1952 o += fprintf(stderr, "%d-%d ", cf->output.array_base, 1953 cf->output.array_base + cf->output.burst_count - 1); 1954 o += print_indent(o, 55); 1955 o += fprintf(stderr, "R%d-%d.", cf->output.gpr, 1956 cf->output.gpr + cf->output.burst_count - 1); 1957 } else { 1958 o += fprintf(stderr, "%d ", cf->output.array_base); 1959 o += print_indent(o, 55); 1960 o += fprintf(stderr, "R%d.", cf->output.gpr); 1961 } 1962 for (i = 0; i < 4; ++i) { 1963 if (cf->output.comp_mask & (1 << i)) 1964 o += print_swizzle(i); 1965 else 1966 o += print_swizzle(7); 1967 } 1968 1969 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND) 1970 o += fprintf(stderr, " R%d", cf->output.index_gpr); 1971 1972 o += print_indent(o, 67); 1973 1974 fprintf(stderr, " ES:%i ", cf->output.elem_size); 1975 if (cf->output.array_size != 0xFFF) 1976 fprintf(stderr, "AS:%i ", cf->output.array_size); 1977 if (!cf->barrier) 1978 fprintf(stderr, "NO_BARRIER "); 1979 if (cf->end_of_program) 1980 fprintf(stderr, "EOP "); 1981 fprintf(stderr, "\n"); 1982 } else { 1983 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id], 1984 bc->bytecode[id + 1], cfop->name); 1985 fprintf(stderr, "@%d ", cf->cf_addr); 1986 if (cf->cond) 1987 fprintf(stderr, "CND:%X ", cf->cond); 1988 if (cf->pop_count) 1989 fprintf(stderr, "POP:%X ", cf->pop_count); 1990 fprintf(stderr, "\n"); 1991 } 1992 } 1993 1994 id = cf->addr; 1995 nliteral = 0; 1996 last = 1; 1997 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) { 1998 const char *omod_str[] = {"","*2","*4","/2"}; 1999 const struct alu_op_info *aop = r600_isa_alu(alu->op); 2000 int o = 0; 2001 2002 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral); 2003 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]); 2004 if (last) 2005 o += fprintf(stderr, "%4d ", ++ngr); 2006 else 2007 o += fprintf(stderr, " "); 2008 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ', 2009 alu->update_pred ? 'P':' ', 2010 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' '); 2011 2012 o += fprintf(stderr, "%s%s%s ", aop->name, 2013 omod_str[alu->omod], alu->dst.clamp ? "_sat":""); 2014 2015 o += print_indent(o,60); 2016 o += print_dst(alu); 2017 for (i = 0; i < aop->src_count; ++i) { 2018 o += fprintf(stderr, i == 0 ? ", ": ", "); 2019 o += print_src(alu, i); 2020 } 2021 2022 if (alu->bank_swizzle) { 2023 o += print_indent(o,75); 2024 o += fprintf(stderr, " BS:%d", alu->bank_swizzle); 2025 } 2026 2027 fprintf(stderr, "\n"); 2028 id += 2; 2029 2030 if (alu->last) { 2031 for (i = 0; i < nliteral; i++, id++) { 2032 float *f = (float*)(bc->bytecode + id); 2033 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]); 2034 print_indent(o, 60); 2035 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id)); 2036 } 2037 id += nliteral & 1; 2038 nliteral = 0; 2039 } 2040 last = alu->last; 2041 } 2042 2043 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) { 2044 int o = 0; 2045 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id], 2046 bc->bytecode[id + 1], bc->bytecode[id + 2]); 2047 2048 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name); 2049 2050 o += print_indent(o, 50); 2051 2052 o += fprintf(stderr, "R%d.", tex->dst_gpr); 2053 o += print_swizzle(tex->dst_sel_x); 2054 o += print_swizzle(tex->dst_sel_y); 2055 o += print_swizzle(tex->dst_sel_z); 2056 o += print_swizzle(tex->dst_sel_w); 2057 2058 o += fprintf(stderr, ", R%d.", tex->src_gpr); 2059 o += print_swizzle(tex->src_sel_x); 2060 o += print_swizzle(tex->src_sel_y); 2061 o += print_swizzle(tex->src_sel_z); 2062 o += print_swizzle(tex->src_sel_w); 2063 2064 o += fprintf(stderr, ", RID:%d", tex->resource_id); 2065 o += fprintf(stderr, ", SID:%d ", tex->sampler_id); 2066 2067 if (tex->lod_bias) 2068 fprintf(stderr, "LB:%d ", tex->lod_bias); 2069 2070 fprintf(stderr, "CT:%c%c%c%c ", 2071 tex->coord_type_x ? 'N' : 'U', 2072 tex->coord_type_y ? 'N' : 'U', 2073 tex->coord_type_z ? 'N' : 'U', 2074 tex->coord_type_w ? 'N' : 'U'); 2075 2076 if (tex->offset_x) 2077 fprintf(stderr, "OX:%d ", tex->offset_x); 2078 if (tex->offset_y) 2079 fprintf(stderr, "OY:%d ", tex->offset_y); 2080 if (tex->offset_z) 2081 fprintf(stderr, "OZ:%d ", tex->offset_z); 2082 2083 id += 4; 2084 fprintf(stderr, "\n"); 2085 } 2086 2087 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) { 2088 int o = 0; 2089 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""}; 2090 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id], 2091 bc->bytecode[id + 1], bc->bytecode[id + 2]); 2092 2093 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name); 2094 2095 o += print_indent(o, 50); 2096 2097 o += fprintf(stderr, "R%d.", vtx->dst_gpr); 2098 o += print_swizzle(vtx->dst_sel_x); 2099 o += print_swizzle(vtx->dst_sel_y); 2100 o += print_swizzle(vtx->dst_sel_z); 2101 o += print_swizzle(vtx->dst_sel_w); 2102 2103 o += fprintf(stderr, ", R%d.", vtx->src_gpr); 2104 o += print_swizzle(vtx->src_sel_x); 2105 2106 if (vtx->offset) 2107 fprintf(stderr, " +%db", vtx->offset); 2108 2109 o += print_indent(o, 55); 2110 2111 fprintf(stderr, ", RID:%d ", vtx->buffer_id); 2112 2113 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]); 2114 2115 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count) 2116 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count); 2117 2118 fprintf(stderr, "UCF:%d ", vtx->use_const_fields); 2119 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format); 2120 fprintf(stderr, "NUM:%d ", vtx->num_format_all); 2121 fprintf(stderr, "COMP:%d ", vtx->format_comp_all); 2122 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all); 2123 2124 id += 4; 2125 } 2126 } 2127 2128 fprintf(stderr, "--------------------------------------\n"); 2129} 2130 2131void r600_vertex_data_type(enum pipe_format pformat, 2132 unsigned *format, 2133 unsigned *num_format, unsigned *format_comp, unsigned *endian) 2134{ 2135 const struct util_format_description *desc; 2136 unsigned i; 2137 2138 *format = 0; 2139 *num_format = 0; 2140 *format_comp = 0; 2141 *endian = ENDIAN_NONE; 2142 2143 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) { 2144 *format = FMT_10_11_11_FLOAT; 2145 *endian = r600_endian_swap(32); 2146 return; 2147 } 2148 2149 desc = util_format_description(pformat); 2150 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) { 2151 goto out_unknown; 2152 } 2153 2154 /* Find the first non-VOID channel. */ 2155 for (i = 0; i < 4; i++) { 2156 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 2157 break; 2158 } 2159 } 2160 2161 *endian = r600_endian_swap(desc->channel[i].size); 2162 2163 switch (desc->channel[i].type) { 2164 /* Half-floats, floats, ints */ 2165 case UTIL_FORMAT_TYPE_FLOAT: 2166 switch (desc->channel[i].size) { 2167 case 16: 2168 switch (desc->nr_channels) { 2169 case 1: 2170 *format = FMT_16_FLOAT; 2171 break; 2172 case 2: 2173 *format = FMT_16_16_FLOAT; 2174 break; 2175 case 3: 2176 case 4: 2177 *format = FMT_16_16_16_16_FLOAT; 2178 break; 2179 } 2180 break; 2181 case 32: 2182 switch (desc->nr_channels) { 2183 case 1: 2184 *format = FMT_32_FLOAT; 2185 break; 2186 case 2: 2187 *format = FMT_32_32_FLOAT; 2188 break; 2189 case 3: 2190 *format = FMT_32_32_32_FLOAT; 2191 break; 2192 case 4: 2193 *format = FMT_32_32_32_32_FLOAT; 2194 break; 2195 } 2196 break; 2197 default: 2198 goto out_unknown; 2199 } 2200 break; 2201 /* Unsigned ints */ 2202 case UTIL_FORMAT_TYPE_UNSIGNED: 2203 /* Signed ints */ 2204 case UTIL_FORMAT_TYPE_SIGNED: 2205 switch (desc->channel[i].size) { 2206 case 8: 2207 switch (desc->nr_channels) { 2208 case 1: 2209 *format = FMT_8; 2210 break; 2211 case 2: 2212 *format = FMT_8_8; 2213 break; 2214 case 3: 2215 case 4: 2216 *format = FMT_8_8_8_8; 2217 break; 2218 } 2219 break; 2220 case 10: 2221 if (desc->nr_channels != 4) 2222 goto out_unknown; 2223 2224 *format = FMT_2_10_10_10; 2225 break; 2226 case 16: 2227 switch (desc->nr_channels) { 2228 case 1: 2229 *format = FMT_16; 2230 break; 2231 case 2: 2232 *format = FMT_16_16; 2233 break; 2234 case 3: 2235 case 4: 2236 *format = FMT_16_16_16_16; 2237 break; 2238 } 2239 break; 2240 case 32: 2241 switch (desc->nr_channels) { 2242 case 1: 2243 *format = FMT_32; 2244 break; 2245 case 2: 2246 *format = FMT_32_32; 2247 break; 2248 case 3: 2249 *format = FMT_32_32_32; 2250 break; 2251 case 4: 2252 *format = FMT_32_32_32_32; 2253 break; 2254 } 2255 break; 2256 default: 2257 goto out_unknown; 2258 } 2259 break; 2260 default: 2261 goto out_unknown; 2262 } 2263 2264 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 2265 *format_comp = 1; 2266 } 2267 2268 *num_format = 0; 2269 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED || 2270 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 2271 if (!desc->channel[i].normalized) { 2272 if (desc->channel[i].pure_integer) 2273 *num_format = 1; 2274 else 2275 *num_format = 2; 2276 } 2277 } 2278 return; 2279out_unknown: 2280 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat)); 2281} 2282 2283void *r600_create_vertex_fetch_shader(struct pipe_context *ctx, 2284 unsigned count, 2285 const struct pipe_vertex_element *elements) 2286{ 2287 struct r600_context *rctx = (struct r600_context *)ctx; 2288 struct r600_bytecode bc; 2289 struct r600_bytecode_vtx vtx; 2290 const struct util_format_description *desc; 2291 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160; 2292 unsigned format, num_format, format_comp, endian; 2293 uint32_t *bytecode; 2294 int i, j, r, fs_size; 2295 struct r600_fetch_shader *shader; 2296 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB; 2297 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM); 2298 2299 assert(count < 32); 2300 2301 memset(&bc, 0, sizeof(bc)); 2302 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family, 2303 rctx->screen->has_compressed_msaa_texturing); 2304 2305 bc.isa = rctx->isa; 2306 2307 for (i = 0; i < count; i++) { 2308 if (elements[i].instance_divisor > 1) { 2309 if (rctx->b.chip_class == CAYMAN) { 2310 for (j = 0; j < 4; j++) { 2311 struct r600_bytecode_alu alu; 2312 memset(&alu, 0, sizeof(alu)); 2313 alu.op = ALU_OP2_MULHI_UINT; 2314 alu.src[0].sel = 0; 2315 alu.src[0].chan = 3; 2316 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; 2317 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1; 2318 alu.dst.sel = i + 1; 2319 alu.dst.chan = j; 2320 alu.dst.write = j == 3; 2321 alu.last = j == 3; 2322 if ((r = r600_bytecode_add_alu(&bc, &alu))) { 2323 r600_bytecode_clear(&bc); 2324 return NULL; 2325 } 2326 } 2327 } else { 2328 struct r600_bytecode_alu alu; 2329 memset(&alu, 0, sizeof(alu)); 2330 alu.op = ALU_OP2_MULHI_UINT; 2331 alu.src[0].sel = 0; 2332 alu.src[0].chan = 3; 2333 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL; 2334 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1; 2335 alu.dst.sel = i + 1; 2336 alu.dst.chan = 3; 2337 alu.dst.write = 1; 2338 alu.last = 1; 2339 if ((r = r600_bytecode_add_alu(&bc, &alu))) { 2340 r600_bytecode_clear(&bc); 2341 return NULL; 2342 } 2343 } 2344 } 2345 } 2346 2347 for (i = 0; i < count; i++) { 2348 r600_vertex_data_type(elements[i].src_format, 2349 &format, &num_format, &format_comp, &endian); 2350 2351 desc = util_format_description(elements[i].src_format); 2352 if (desc == NULL) { 2353 r600_bytecode_clear(&bc); 2354 R600_ERR("unknown format %d\n", elements[i].src_format); 2355 return NULL; 2356 } 2357 2358 if (elements[i].src_offset > 65535) { 2359 r600_bytecode_clear(&bc); 2360 R600_ERR("too big src_offset: %u\n", elements[i].src_offset); 2361 return NULL; 2362 } 2363 2364 memset(&vtx, 0, sizeof(vtx)); 2365 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start; 2366 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0; 2367 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0; 2368 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0; 2369 vtx.mega_fetch_count = 0x1F; 2370 vtx.dst_gpr = i + 1; 2371 vtx.dst_sel_x = desc->swizzle[0]; 2372 vtx.dst_sel_y = desc->swizzle[1]; 2373 vtx.dst_sel_z = desc->swizzle[2]; 2374 vtx.dst_sel_w = desc->swizzle[3]; 2375 vtx.data_format = format; 2376 vtx.num_format_all = num_format; 2377 vtx.format_comp_all = format_comp; 2378 vtx.offset = elements[i].src_offset; 2379 vtx.endian = endian; 2380 2381 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) { 2382 r600_bytecode_clear(&bc); 2383 return NULL; 2384 } 2385 } 2386 2387 r600_bytecode_add_cfinst(&bc, CF_OP_RET); 2388 2389 if ((r = r600_bytecode_build(&bc))) { 2390 r600_bytecode_clear(&bc); 2391 return NULL; 2392 } 2393 2394 if (rctx->screen->b.debug_flags & DBG_FS) { 2395 fprintf(stderr, "--------------------------------------------------------------\n"); 2396 fprintf(stderr, "Vertex elements state:\n"); 2397 for (i = 0; i < count; i++) { 2398 fprintf(stderr, " "); 2399 util_dump_vertex_element(stderr, elements+i); 2400 fprintf(stderr, "\n"); 2401 } 2402 2403 if (!sb_disasm) { 2404 r600_bytecode_disasm(&bc); 2405 2406 fprintf(stderr, "______________________________________________________________\n"); 2407 } else { 2408 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/); 2409 } 2410 } 2411 2412 fs_size = bc.ndw*4; 2413 2414 /* Allocate the CSO. */ 2415 shader = CALLOC_STRUCT(r600_fetch_shader); 2416 if (!shader) { 2417 r600_bytecode_clear(&bc); 2418 return NULL; 2419 } 2420 2421 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset, 2422 (struct pipe_resource**)&shader->buffer); 2423 if (!shader->buffer) { 2424 r600_bytecode_clear(&bc); 2425 FREE(shader); 2426 return NULL; 2427 } 2428 2429 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED); 2430 bytecode += shader->offset / 4; 2431 2432 if (R600_BIG_ENDIAN) { 2433 for (i = 0; i < fs_size / 4; ++i) { 2434 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]); 2435 } 2436 } else { 2437 memcpy(bytecode, bc.bytecode, fs_size); 2438 } 2439 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf); 2440 2441 r600_bytecode_clear(&bc); 2442 return shader; 2443} 2444 2445void r600_bytecode_alu_read(struct r600_bytecode *bc, 2446 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1) 2447{ 2448 /* WORD0 */ 2449 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0); 2450 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0); 2451 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0); 2452 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0); 2453 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0); 2454 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0); 2455 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0); 2456 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0); 2457 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0); 2458 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0); 2459 alu->last = G_SQ_ALU_WORD0_LAST(word0); 2460 2461 /* WORD1 */ 2462 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1); 2463 if (alu->bank_swizzle) 2464 alu->bank_swizzle_force = alu->bank_swizzle; 2465 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1); 2466 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1); 2467 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1); 2468 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1); 2469 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/ 2470 { 2471 alu->is_op3 = 1; 2472 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1); 2473 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1); 2474 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1); 2475 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1); 2476 alu->op = r600_isa_alu_by_opcode(bc->isa, 2477 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1); 2478 2479 } 2480 else /*ALU_DWORD1_OP2*/ 2481 { 2482 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1); 2483 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1); 2484 alu->op = r600_isa_alu_by_opcode(bc->isa, 2485 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0); 2486 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1); 2487 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1); 2488 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1); 2489 alu->execute_mask = 2490 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1); 2491 } 2492} 2493 2494#if 0 2495void r600_bytecode_export_read(struct r600_bytecode *bc, 2496 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1) 2497{ 2498 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0); 2499 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0); 2500 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0); 2501 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0); 2502 2503 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1); 2504 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1); 2505 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1); 2506 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1); 2507 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1); 2508 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1); 2509 output->op = r600_isa_cf_by_opcode(bc->isa, 2510 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0); 2511 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1); 2512 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1); 2513 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1); 2514} 2515#endif 2516