1848b8605Smrg/*
2848b8605Smrg * Copyright 2012 Vadim Girlin <vadimgirlin@gmail.com>
3848b8605Smrg *
4848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5848b8605Smrg * copy of this software and associated documentation files (the "Software"),
6848b8605Smrg * to deal in the Software without restriction, including without limitation
7848b8605Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub
8848b8605Smrg * license, and/or sell copies of the Software, and to permit persons to whom
9848b8605Smrg * the Software is furnished to do so, subject to the following conditions:
10848b8605Smrg *
11848b8605Smrg * The above copyright notice and this permission notice (including the next
12848b8605Smrg * paragraph) shall be included in all copies or substantial portions of the
13848b8605Smrg * Software.
14848b8605Smrg *
15848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16848b8605Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17848b8605Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18848b8605Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19848b8605Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20848b8605Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21848b8605Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE.
22848b8605Smrg *
23848b8605Smrg * Authors:
24848b8605Smrg *      Vadim Girlin
25848b8605Smrg */
26848b8605Smrg
27848b8605Smrg#ifndef R600_ISA_H_
28848b8605Smrg#define R600_ISA_H_
29848b8605Smrg
30848b8605Smrg#include "util/u_debug.h"
31848b8605Smrg
32b8e80941Smrg#ifdef __cplusplus
33b8e80941Smrgextern "C" {
34b8e80941Smrg#endif
35b8e80941Smrg
36848b8605Smrg/* ALU flags */
37848b8605Smrgenum alu_op_flags
38848b8605Smrg{
39848b8605Smrg	AF_V		= (1<<0),    /* allowed in vector slots */
40848b8605Smrg
41848b8605Smrg	/* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated
42848b8605Smrg	 * to w) */
43848b8605Smrg	AF_S		= (1<<1),
44848b8605Smrg
45848b8605Smrg	AF_4SLOT	= (1<<2),            /* uses four vector slots (e.g. DOT4) */
46848b8605Smrg	AF_4V		= (AF_V | AF_4SLOT),
47848b8605Smrg	AF_VS		= (AF_V | AF_S),     /* allowed in any slot */
48848b8605Smrg
49848b8605Smrg	AF_KILL		= (1<<4),
50848b8605Smrg	AF_PRED		= (1<<5),
51848b8605Smrg	AF_SET		= (1<<6),
52848b8605Smrg
53848b8605Smrg	/* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */
54848b8605Smrg	AF_PREV_INTERLEAVE	= (1<<7),
55848b8605Smrg
56848b8605Smrg	AF_MOVA		= (1<<8),    /* all MOVA instructions */
57848b8605Smrg	AF_IEEE		= (1<<10),
58848b8605Smrg
59848b8605Smrg	AF_DST_TYPE_MASK = (3<<11),
60848b8605Smrg	AF_FLOAT_DST	= 0,
61848b8605Smrg	AF_INT_DST		= (1<<11),
62848b8605Smrg	AF_UINT_DST		= (3<<11),
63848b8605Smrg
64848b8605Smrg	/* DP instructions, 2-slot pairs */
65848b8605Smrg	AF_64		= (1<<13),
66848b8605Smrg	/* 24 bit instructions */
67848b8605Smrg	AF_24		= (1<<14),
68848b8605Smrg	/* DX10 variants */
69848b8605Smrg	AF_DX10		= (1<<15),
70848b8605Smrg
71848b8605Smrg	/* result is replicated to all channels (only if AF_4V is also set -
72848b8605Smrg	 * for special handling of MULLO_INT on CM) */
73848b8605Smrg	AF_REPL		= (1<<16),
74848b8605Smrg
75848b8605Smrg	/* interpolation instructions */
76848b8605Smrg	AF_INTERP	= (1<<17),
77848b8605Smrg
78848b8605Smrg	/* LDS instructions */
79848b8605Smrg	AF_LDS		= (1<<20),
80848b8605Smrg
81848b8605Smrg	/* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */
82848b8605Smrg	AF_PREV_NEXT	= (1<<21),
83848b8605Smrg
84848b8605Smrg	/* int<->flt conversions */
85848b8605Smrg	AF_CVT = (1<<22),
86848b8605Smrg
87848b8605Smrg	/* commutative operation on src0 and src1 ( a op b = b op a),
88848b8605Smrg	 * includes MULADDs (considering the MUL part on src0 and src1 only) */
89848b8605Smrg	AF_M_COMM = (1 << 23),
90848b8605Smrg
91848b8605Smrg	/* associative operation ((a op b) op c) == (a op (b op c)),
92848b8605Smrg	 * includes MULADDs (considering the MUL part on src0 and src1 only) */
93848b8605Smrg	AF_M_ASSOC = (1 << 24),
94848b8605Smrg
95848b8605Smrg	AF_PRED_PUSH = (1 << 25),
96848b8605Smrg
97848b8605Smrg	AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),
98848b8605Smrg
99848b8605Smrg	AF_CMOV = (1 << 26),
100848b8605Smrg
101848b8605Smrg	// for SETcc, PREDSETcc, ... - type of comparison
102848b8605Smrg	AF_CMP_TYPE_MASK = (3 << 27),
103848b8605Smrg	AF_FLOAT_CMP = 0,
104848b8605Smrg	AF_INT_CMP = (1 << 27),
105848b8605Smrg	AF_UINT_CMP = (3 << 27),
106848b8605Smrg
107848b8605Smrg	/* condition codes - 3 bits */
108848b8605Smrg	AF_CC_SHIFT = 29,
109b8e80941Smrg	AF_CC_MASK	= (7U << AF_CC_SHIFT),
110b8e80941Smrg	AF_CC_E		= (0U << AF_CC_SHIFT),
111b8e80941Smrg	AF_CC_GT	= (1U << AF_CC_SHIFT),
112b8e80941Smrg	AF_CC_GE	= (2U << AF_CC_SHIFT),
113b8e80941Smrg	AF_CC_NE	= (3U << AF_CC_SHIFT),
114b8e80941Smrg	AF_CC_LT	= (4U << AF_CC_SHIFT),
115b8e80941Smrg	AF_CC_LE	= (5U << AF_CC_SHIFT),
116848b8605Smrg};
117848b8605Smrg
118b8e80941Smrg/* flags for FETCH instructions (TEX/VTX/GDS) */
119848b8605Smrgenum fetch_op_flags
120848b8605Smrg{
121848b8605Smrg	FF_GDS		= (1<<0),
122848b8605Smrg	FF_TEX		= (1<<1),
123848b8605Smrg
124848b8605Smrg	FF_SETGRAD	= (1<<2),
125848b8605Smrg	FF_GETGRAD	= (1<<3),
126848b8605Smrg	FF_USEGRAD	= (1<<4),
127848b8605Smrg
128848b8605Smrg	FF_VTX		= (1<<5),
129848b8605Smrg	FF_MEM		= (1<<6),
130848b8605Smrg
131848b8605Smrg	FF_SET_TEXTURE_OFFSETS = (1<<7),
132848b8605Smrg	FF_USE_TEXTURE_OFFSETS = (1<<8),
133848b8605Smrg};
134848b8605Smrg
135848b8605Smrg/* flags for CF instructions */
136848b8605Smrgenum cf_op_flags
137848b8605Smrg{
138848b8605Smrg	CF_CLAUSE	= (1<<0), 	/* execute clause (alu/fetch ...) */
139848b8605Smrg	CF_ACK		= (1<<1),	/* acked versions of some instructions */
140848b8605Smrg	CF_ALU		= (1<<2),	/* alu clause execution */
141848b8605Smrg	CF_ALU_EXT	= (1<<3),	/* ALU_EXTENDED */
142848b8605Smrg	CF_EXP		= (1<<4),	/* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */
143848b8605Smrg	CF_BRANCH	= (1<<5),   /* branch instructions */
144848b8605Smrg	CF_LOOP		= (1<<6),   /* loop instructions */
145848b8605Smrg	CF_CALL		= (1<<7),   /* call instructions */
146848b8605Smrg	CF_MEM		= (1<<8),	/* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */
147848b8605Smrg	CF_FETCH	= (1<<9),	/* fetch clause */
148848b8605Smrg
149848b8605Smrg	CF_UNCOND	= (1<<10),	/* COND = ACTIVE required */
150848b8605Smrg	CF_EMIT		= (1<<11),
151848b8605Smrg	CF_STRM		= (1<<12),	/* MEM_STREAM* */
152848b8605Smrg
153848b8605Smrg	CF_RAT		= (1<<13),  /* MEM_RAT* */
154848b8605Smrg
155848b8605Smrg	CF_LOOP_START = (1<<14)
156848b8605Smrg};
157848b8605Smrg
158848b8605Smrg/* ALU instruction info */
159848b8605Smrgstruct alu_op_info
160848b8605Smrg{
161848b8605Smrg	/* instruction name */
162848b8605Smrg	const char	*name;
163848b8605Smrg	/* number of source operands */
164848b8605Smrg	int	src_count;
165848b8605Smrg	/* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman
166848b8605Smrg	 * (-1) if instruction doesn't exist (more precise info in "slots") */
167848b8605Smrg	int opcode[2];
168848b8605Smrg	/* slots for r6xx, r7xx, evergreen, cayman
169848b8605Smrg	 * (0 if instruction doesn't exist for chip class) */
170848b8605Smrg	int	slots[4];
171848b8605Smrg	/* flags (mostly autogenerated from instruction name) */
172b8e80941Smrg	unsigned int flags;
173848b8605Smrg};
174848b8605Smrg
175848b8605Smrg/* FETCH instruction info */
176848b8605Smrgstruct fetch_op_info
177848b8605Smrg{
178848b8605Smrg	const char * name;
179848b8605Smrg	/* for every chip class */
180848b8605Smrg	int opcode[4];
181848b8605Smrg	int flags;
182848b8605Smrg};
183848b8605Smrg
184848b8605Smrg/* CF instruction info */
185848b8605Smrgstruct cf_op_info
186848b8605Smrg{
187848b8605Smrg	const char * name;
188848b8605Smrg	/* for every chip class */
189848b8605Smrg	int opcode[4];
190848b8605Smrg	int flags;
191848b8605Smrg};
192848b8605Smrg
193848b8605Smrg
194848b8605Smrg#define ALU_OP2_ADD                             0
195848b8605Smrg#define ALU_OP2_MUL                             1
196848b8605Smrg#define ALU_OP2_MUL_IEEE                        2
197848b8605Smrg#define ALU_OP2_MAX                             3
198848b8605Smrg#define ALU_OP2_MIN                             4
199848b8605Smrg#define ALU_OP2_MAX_DX10                        5
200848b8605Smrg#define ALU_OP2_MIN_DX10                        6
201848b8605Smrg#define ALU_OP2_SETE                            7
202848b8605Smrg#define ALU_OP2_SETGT                           8
203848b8605Smrg#define ALU_OP2_SETGE                           9
204848b8605Smrg#define ALU_OP2_SETNE                          10
205848b8605Smrg#define ALU_OP2_SETE_DX10                      11
206848b8605Smrg#define ALU_OP2_SETGT_DX10                     12
207848b8605Smrg#define ALU_OP2_SETGE_DX10                     13
208848b8605Smrg#define ALU_OP2_SETNE_DX10                     14
209848b8605Smrg#define ALU_OP1_FRACT                          15
210848b8605Smrg#define ALU_OP1_TRUNC                          16
211848b8605Smrg#define ALU_OP1_CEIL                           17
212848b8605Smrg#define ALU_OP1_RNDNE                          18
213848b8605Smrg#define ALU_OP1_FLOOR                          19
214848b8605Smrg#define ALU_OP2_ASHR_INT                       20
215848b8605Smrg#define ALU_OP2_LSHR_INT                       21
216848b8605Smrg#define ALU_OP2_LSHL_INT                       22
217848b8605Smrg#define ALU_OP1_MOV                            23
218848b8605Smrg#define ALU_OP0_NOP                            24
219848b8605Smrg#define ALU_OP2_PRED_SETGT_UINT                25
220848b8605Smrg#define ALU_OP2_PRED_SETGE_UINT                26
221848b8605Smrg#define ALU_OP2_PRED_SETE                      27
222848b8605Smrg#define ALU_OP2_PRED_SETGT                     28
223848b8605Smrg#define ALU_OP2_PRED_SETGE                     29
224848b8605Smrg#define ALU_OP2_PRED_SETNE                     30
225848b8605Smrg#define ALU_OP1_PRED_SET_INV                   31
226848b8605Smrg#define ALU_OP2_PRED_SET_POP                   32
227848b8605Smrg#define ALU_OP0_PRED_SET_CLR                   33
228848b8605Smrg#define ALU_OP1_PRED_SET_RESTORE               34
229848b8605Smrg#define ALU_OP2_PRED_SETE_PUSH                 35
230848b8605Smrg#define ALU_OP2_PRED_SETGT_PUSH                36
231848b8605Smrg#define ALU_OP2_PRED_SETGE_PUSH                37
232848b8605Smrg#define ALU_OP2_PRED_SETNE_PUSH                38
233848b8605Smrg#define ALU_OP2_KILLE                          39
234848b8605Smrg#define ALU_OP2_KILLGT                         40
235848b8605Smrg#define ALU_OP2_KILLGE                         41
236848b8605Smrg#define ALU_OP2_KILLNE                         42
237848b8605Smrg#define ALU_OP2_AND_INT                        43
238848b8605Smrg#define ALU_OP2_OR_INT                         44
239848b8605Smrg#define ALU_OP2_XOR_INT                        45
240848b8605Smrg#define ALU_OP1_NOT_INT                        46
241848b8605Smrg#define ALU_OP2_ADD_INT                        47
242848b8605Smrg#define ALU_OP2_SUB_INT                        48
243848b8605Smrg#define ALU_OP2_MAX_INT                        49
244848b8605Smrg#define ALU_OP2_MIN_INT                        50
245848b8605Smrg#define ALU_OP2_MAX_UINT                       51
246848b8605Smrg#define ALU_OP2_MIN_UINT                       52
247848b8605Smrg#define ALU_OP2_SETE_INT                       53
248848b8605Smrg#define ALU_OP2_SETGT_INT                      54
249848b8605Smrg#define ALU_OP2_SETGE_INT                      55
250848b8605Smrg#define ALU_OP2_SETNE_INT                      56
251848b8605Smrg#define ALU_OP2_SETGT_UINT                     57
252848b8605Smrg#define ALU_OP2_SETGE_UINT                     58
253848b8605Smrg#define ALU_OP2_KILLGT_UINT                    59
254848b8605Smrg#define ALU_OP2_KILLGE_UINT                    60
255848b8605Smrg#define ALU_OP2_PRED_SETE_INT                  61
256848b8605Smrg#define ALU_OP2_PRED_SETGT_INT                 62
257848b8605Smrg#define ALU_OP2_PRED_SETGE_INT                 63
258848b8605Smrg#define ALU_OP2_PRED_SETNE_INT                 64
259848b8605Smrg#define ALU_OP2_KILLE_INT                      65
260848b8605Smrg#define ALU_OP2_KILLGT_INT                     66
261848b8605Smrg#define ALU_OP2_KILLGE_INT                     67
262848b8605Smrg#define ALU_OP2_KILLNE_INT                     68
263848b8605Smrg#define ALU_OP2_PRED_SETE_PUSH_INT             69
264848b8605Smrg#define ALU_OP2_PRED_SETGT_PUSH_INT            70
265848b8605Smrg#define ALU_OP2_PRED_SETGE_PUSH_INT            71
266848b8605Smrg#define ALU_OP2_PRED_SETNE_PUSH_INT            72
267848b8605Smrg#define ALU_OP2_PRED_SETLT_PUSH_INT            73
268848b8605Smrg#define ALU_OP2_PRED_SETLE_PUSH_INT            74
269848b8605Smrg#define ALU_OP1_FLT_TO_INT                     75
270848b8605Smrg#define ALU_OP1_BFREV_INT                      76
271848b8605Smrg#define ALU_OP2_ADDC_UINT                      77
272848b8605Smrg#define ALU_OP2_SUBB_UINT                      78
273848b8605Smrg#define ALU_OP0_GROUP_BARRIER                  79
274848b8605Smrg#define ALU_OP0_GROUP_SEQ_BEGIN                80
275848b8605Smrg#define ALU_OP0_GROUP_SEQ_END                  81
276848b8605Smrg#define ALU_OP2_SET_MODE                       82
277848b8605Smrg#define ALU_OP0_SET_CF_IDX0                    83
278848b8605Smrg#define ALU_OP0_SET_CF_IDX1                    84
279848b8605Smrg#define ALU_OP2_SET_LDS_SIZE                   85
280848b8605Smrg#define ALU_OP2_MUL_INT24                      86
281848b8605Smrg#define ALU_OP2_MULHI_INT24                    87
282848b8605Smrg#define ALU_OP1_FLT_TO_INT_TRUNC               88
283848b8605Smrg#define ALU_OP1_EXP_IEEE                       89
284848b8605Smrg#define ALU_OP1_LOG_CLAMPED                    90
285848b8605Smrg#define ALU_OP1_LOG_IEEE                       91
286848b8605Smrg#define ALU_OP1_RECIP_CLAMPED                  92
287848b8605Smrg#define ALU_OP1_RECIP_FF                       93
288848b8605Smrg#define ALU_OP1_RECIP_IEEE                     94
289848b8605Smrg#define ALU_OP1_RECIPSQRT_CLAMPED              95
290848b8605Smrg#define ALU_OP1_RECIPSQRT_FF                   96
291848b8605Smrg#define ALU_OP1_RECIPSQRT_IEEE                 97
292848b8605Smrg#define ALU_OP1_SQRT_IEEE                      98
293848b8605Smrg#define ALU_OP1_SIN                            99
294848b8605Smrg#define ALU_OP1_COS                           100
295848b8605Smrg#define ALU_OP2_MULLO_INT                     101
296848b8605Smrg#define ALU_OP2_MULHI_INT                     102
297848b8605Smrg#define ALU_OP2_MULLO_UINT                    103
298848b8605Smrg#define ALU_OP2_MULHI_UINT                    104
299848b8605Smrg#define ALU_OP1_RECIP_INT                     105
300848b8605Smrg#define ALU_OP1_RECIP_UINT                    106
301848b8605Smrg#define ALU_OP2_RECIP_64                      107
302848b8605Smrg#define ALU_OP2_RECIP_CLAMPED_64              108
303848b8605Smrg#define ALU_OP2_RECIPSQRT_64                  109
304848b8605Smrg#define ALU_OP2_RECIPSQRT_CLAMPED_64          110
305848b8605Smrg#define ALU_OP2_SQRT_64                       111
306848b8605Smrg#define ALU_OP1_FLT_TO_UINT                   112
307848b8605Smrg#define ALU_OP1_INT_TO_FLT                    113
308848b8605Smrg#define ALU_OP1_UINT_TO_FLT                   114
309848b8605Smrg#define ALU_OP2_BFM_INT                       115
310848b8605Smrg#define ALU_OP1_FLT32_TO_FLT16                116
311848b8605Smrg#define ALU_OP1_FLT16_TO_FLT32                117
312848b8605Smrg#define ALU_OP1_UBYTE0_FLT                    118
313848b8605Smrg#define ALU_OP1_UBYTE1_FLT                    119
314848b8605Smrg#define ALU_OP1_UBYTE2_FLT                    120
315848b8605Smrg#define ALU_OP1_UBYTE3_FLT                    121
316848b8605Smrg#define ALU_OP1_BCNT_INT                      122
317848b8605Smrg#define ALU_OP1_FFBH_UINT                     123
318848b8605Smrg#define ALU_OP1_FFBL_INT                      124
319848b8605Smrg#define ALU_OP1_FFBH_INT                      125
320848b8605Smrg#define ALU_OP1_FLT_TO_UINT4                  126
321848b8605Smrg#define ALU_OP2_DOT_IEEE                      127
322848b8605Smrg#define ALU_OP1_FLT_TO_INT_RPI                128
323848b8605Smrg#define ALU_OP1_FLT_TO_INT_FLOOR              129
324848b8605Smrg#define ALU_OP2_MULHI_UINT24                  130
325848b8605Smrg#define ALU_OP1_MBCNT_32HI_INT                131
326848b8605Smrg#define ALU_OP1_OFFSET_TO_FLT                 132
327848b8605Smrg#define ALU_OP2_MUL_UINT24                    133
328848b8605Smrg#define ALU_OP1_BCNT_ACCUM_PREV_INT           134
329848b8605Smrg#define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT     135
330848b8605Smrg#define ALU_OP2_SETE_64                       136
331848b8605Smrg#define ALU_OP2_SETNE_64                      137
332848b8605Smrg#define ALU_OP2_SETGT_64                      138
333848b8605Smrg#define ALU_OP2_SETGE_64                      139
334848b8605Smrg#define ALU_OP2_MIN_64                        140
335848b8605Smrg#define ALU_OP2_MAX_64                        141
336848b8605Smrg#define ALU_OP2_DOT4                          142
337848b8605Smrg#define ALU_OP2_DOT4_IEEE                     143
338848b8605Smrg#define ALU_OP2_CUBE                          144
339848b8605Smrg#define ALU_OP1_MAX4                          145
340848b8605Smrg#define ALU_OP1_FREXP_64                      146
341848b8605Smrg#define ALU_OP2_LDEXP_64                      147
342848b8605Smrg#define ALU_OP1_FRACT_64                      148
343848b8605Smrg#define ALU_OP2_PRED_SETGT_64                 149
344848b8605Smrg#define ALU_OP2_PRED_SETE_64                  150
345848b8605Smrg#define ALU_OP2_PRED_SETGE_64                 151
346848b8605Smrg#define ALU_OP2_MUL_64                        152
347848b8605Smrg#define ALU_OP2_ADD_64                        153
348848b8605Smrg#define ALU_OP1_MOVA_INT                      154
349848b8605Smrg#define ALU_OP1_FLT64_TO_FLT32                155
350848b8605Smrg#define ALU_OP1_FLT32_TO_FLT64                156
351848b8605Smrg#define ALU_OP2_SAD_ACCUM_PREV_UINT           157
352848b8605Smrg#define ALU_OP2_DOT                           158
353848b8605Smrg#define ALU_OP1_MUL_PREV                      159
354848b8605Smrg#define ALU_OP1_MUL_IEEE_PREV                 160
355848b8605Smrg#define ALU_OP1_ADD_PREV                      161
356848b8605Smrg#define ALU_OP2_MULADD_PREV                   162
357848b8605Smrg#define ALU_OP2_MULADD_IEEE_PREV              163
358848b8605Smrg#define ALU_OP2_INTERP_XY                     164
359848b8605Smrg#define ALU_OP2_INTERP_ZW                     165
360848b8605Smrg#define ALU_OP2_INTERP_X                      166
361848b8605Smrg#define ALU_OP2_INTERP_Z                      167
362848b8605Smrg#define ALU_OP1_STORE_FLAGS                   168
363848b8605Smrg#define ALU_OP1_LOAD_STORE_FLAGS              169
364848b8605Smrg#define ALU_OP2_LDS_1A                        170
365848b8605Smrg#define ALU_OP2_LDS_1A1D                      171
366848b8605Smrg#define ALU_OP2_LDS_2A                        172
367848b8605Smrg#define ALU_OP1_INTERP_LOAD_P0                173
368848b8605Smrg#define ALU_OP1_INTERP_LOAD_P10               174
369848b8605Smrg#define ALU_OP1_INTERP_LOAD_P20               175
370848b8605Smrg#define ALU_OP3_BFE_UINT                      176
371848b8605Smrg#define ALU_OP3_BFE_INT                       177
372848b8605Smrg#define ALU_OP3_BFI_INT                       178
373848b8605Smrg#define ALU_OP3_FMA                           179
374848b8605Smrg#define ALU_OP3_MULADD_INT24                  180
375848b8605Smrg#define ALU_OP3_CNDNE_64                      181
376848b8605Smrg#define ALU_OP3_FMA_64                        182
377848b8605Smrg#define ALU_OP3_LERP_UINT                     183
378848b8605Smrg#define ALU_OP3_BIT_ALIGN_INT                 184
379848b8605Smrg#define ALU_OP3_BYTE_ALIGN_INT                185
380848b8605Smrg#define ALU_OP3_SAD_ACCUM_UINT                186
381848b8605Smrg#define ALU_OP3_SAD_ACCUM_HI_UINT             187
382848b8605Smrg#define ALU_OP3_MULADD_UINT24                 188
383848b8605Smrg#define ALU_OP3_LDS_IDX_OP                    189
384848b8605Smrg#define ALU_OP3_MULADD                        190
385848b8605Smrg#define ALU_OP3_MULADD_M2                     191
386848b8605Smrg#define ALU_OP3_MULADD_M4                     192
387848b8605Smrg#define ALU_OP3_MULADD_D2                     193
388848b8605Smrg#define ALU_OP3_MULADD_IEEE                   194
389848b8605Smrg#define ALU_OP3_CNDE                          195
390848b8605Smrg#define ALU_OP3_CNDGT                         196
391848b8605Smrg#define ALU_OP3_CNDGE                         197
392848b8605Smrg#define ALU_OP3_CNDE_INT                      198
393848b8605Smrg#define ALU_OP3_CNDGT_INT                     199
394848b8605Smrg#define ALU_OP3_CNDGE_INT                     200
395848b8605Smrg#define ALU_OP3_MUL_LIT                       201
396848b8605Smrg#define ALU_OP1_MOVA                          202
397848b8605Smrg#define ALU_OP1_MOVA_FLOOR                    203
398848b8605Smrg#define ALU_OP1_MOVA_GPR_INT                  204
399848b8605Smrg#define ALU_OP3_MULADD_64                     205
400848b8605Smrg#define ALU_OP3_MULADD_64_M2                  206
401848b8605Smrg#define ALU_OP3_MULADD_64_M4                  207
402848b8605Smrg#define ALU_OP3_MULADD_64_D2                  208
403848b8605Smrg#define ALU_OP3_MUL_LIT_M2                    209
404848b8605Smrg#define ALU_OP3_MUL_LIT_M4                    210
405848b8605Smrg#define ALU_OP3_MUL_LIT_D2                    211
406848b8605Smrg#define ALU_OP3_MULADD_IEEE_M2                212
407848b8605Smrg#define ALU_OP3_MULADD_IEEE_M4                213
408848b8605Smrg#define ALU_OP3_MULADD_IEEE_D2                214
409848b8605Smrg
410848b8605Smrg#define LDS_OP2_LDS_ADD                       215
411848b8605Smrg#define LDS_OP2_LDS_SUB                       216
412848b8605Smrg#define LDS_OP2_LDS_RSUB                      217
413848b8605Smrg#define LDS_OP2_LDS_INC                       218
414848b8605Smrg#define LDS_OP2_LDS_DEC                       219
415848b8605Smrg#define LDS_OP2_LDS_MIN_INT                   220
416848b8605Smrg#define LDS_OP2_LDS_MAX_INT                   221
417848b8605Smrg#define LDS_OP2_LDS_MIN_UINT                  222
418848b8605Smrg#define LDS_OP2_LDS_MAX_UINT                  223
419848b8605Smrg#define LDS_OP2_LDS_AND                       224
420848b8605Smrg#define LDS_OP2_LDS_OR                        225
421848b8605Smrg#define LDS_OP2_LDS_XOR                       226
422848b8605Smrg#define LDS_OP3_LDS_MSKOR                     227
423848b8605Smrg#define LDS_OP2_LDS_WRITE                     228
424848b8605Smrg#define LDS_OP3_LDS_WRITE_REL                 229
425848b8605Smrg#define LDS_OP3_LDS_WRITE2                    230
426848b8605Smrg#define LDS_OP3_LDS_CMP_STORE                 231
427848b8605Smrg#define LDS_OP3_LDS_CMP_STORE_SPF             232
428848b8605Smrg#define LDS_OP2_LDS_BYTE_WRITE                233
429848b8605Smrg#define LDS_OP2_LDS_SHORT_WRITE               234
430848b8605Smrg#define LDS_OP2_LDS_ADD_RET                   235
431848b8605Smrg#define LDS_OP2_LDS_SUB_RET                   236
432848b8605Smrg#define LDS_OP2_LDS_RSUB_RET                  237
433848b8605Smrg#define LDS_OP2_LDS_INC_RET                   238
434848b8605Smrg#define LDS_OP2_LDS_DEC_RET                   239
435848b8605Smrg#define LDS_OP2_LDS_MIN_INT_RET               240
436848b8605Smrg#define LDS_OP2_LDS_MAX_INT_RET               241
437848b8605Smrg#define LDS_OP2_LDS_MIN_UINT_RET              242
438848b8605Smrg#define LDS_OP2_LDS_MAX_UINT_RET              243
439848b8605Smrg#define LDS_OP2_LDS_AND_RET                   244
440848b8605Smrg#define LDS_OP2_LDS_OR_RET                    245
441848b8605Smrg#define LDS_OP2_LDS_XOR_RET                   246
442848b8605Smrg#define LDS_OP3_LDS_MSKOR_RET                 247
443848b8605Smrg#define LDS_OP2_LDS_XCHG_RET                  248
444848b8605Smrg#define LDS_OP3_LDS_XCHG_REL_RET              249
445848b8605Smrg#define LDS_OP3_LDS_XCHG2_RET                 250
446848b8605Smrg#define LDS_OP3_LDS_CMP_XCHG_RET              251
447848b8605Smrg#define LDS_OP3_LDS_CMP_XCHG_SPF_RET          252
448848b8605Smrg#define LDS_OP1_LDS_READ_RET                  253
449848b8605Smrg#define LDS_OP1_LDS_READ_REL_RET              254
450848b8605Smrg#define LDS_OP2_LDS_READ2_RET                 255
451848b8605Smrg#define LDS_OP3_LDS_READWRITE_RET             256
452848b8605Smrg#define LDS_OP1_LDS_BYTE_READ_RET             257
453848b8605Smrg#define LDS_OP1_LDS_UBYTE_READ_RET            258
454848b8605Smrg#define LDS_OP1_LDS_SHORT_READ_RET            259
455848b8605Smrg#define LDS_OP1_LDS_USHORT_READ_RET           260
456848b8605Smrg
457848b8605Smrg#define FETCH_OP_VFETCH                           0
458848b8605Smrg#define FETCH_OP_SEMFETCH                         1
459848b8605Smrg#define FETCH_OP_READ_SCRATCH                     2
460848b8605Smrg#define FETCH_OP_READ_REDUCT                      3
461848b8605Smrg#define FETCH_OP_READ_MEM                         4
462848b8605Smrg#define FETCH_OP_DS_LOCAL_WRITE                   5
463848b8605Smrg#define FETCH_OP_DS_LOCAL_READ                    6
464848b8605Smrg#define FETCH_OP_GDS_ADD                          7
465848b8605Smrg#define FETCH_OP_GDS_SUB                          8
466848b8605Smrg#define FETCH_OP_GDS_RSUB                         9
467848b8605Smrg#define FETCH_OP_GDS_INC                         10
468848b8605Smrg#define FETCH_OP_GDS_DEC                         11
469848b8605Smrg#define FETCH_OP_GDS_MIN_INT                     12
470848b8605Smrg#define FETCH_OP_GDS_MAX_INT                     13
471848b8605Smrg#define FETCH_OP_GDS_MIN_UINT                    14
472848b8605Smrg#define FETCH_OP_GDS_MAX_UINT                    15
473848b8605Smrg#define FETCH_OP_GDS_AND                         16
474848b8605Smrg#define FETCH_OP_GDS_OR                          17
475848b8605Smrg#define FETCH_OP_GDS_XOR                         18
476848b8605Smrg#define FETCH_OP_GDS_MSKOR                       19
477848b8605Smrg#define FETCH_OP_GDS_WRITE                       20
478848b8605Smrg#define FETCH_OP_GDS_WRITE_REL                   21
479848b8605Smrg#define FETCH_OP_GDS_WRITE2                      22
480848b8605Smrg#define FETCH_OP_GDS_CMP_STORE                   23
481848b8605Smrg#define FETCH_OP_GDS_CMP_STORE_SPF               24
482848b8605Smrg#define FETCH_OP_GDS_BYTE_WRITE                  25
483848b8605Smrg#define FETCH_OP_GDS_SHORT_WRITE                 26
484848b8605Smrg#define FETCH_OP_GDS_ADD_RET                     27
485848b8605Smrg#define FETCH_OP_GDS_SUB_RET                     28
486848b8605Smrg#define FETCH_OP_GDS_RSUB_RET                    29
487848b8605Smrg#define FETCH_OP_GDS_INC_RET                     30
488848b8605Smrg#define FETCH_OP_GDS_DEC_RET                     31
489848b8605Smrg#define FETCH_OP_GDS_MIN_INT_RET                 32
490848b8605Smrg#define FETCH_OP_GDS_MAX_INT_RET                 33
491848b8605Smrg#define FETCH_OP_GDS_MIN_UINT_RET                34
492848b8605Smrg#define FETCH_OP_GDS_MAX_UINT_RET                35
493848b8605Smrg#define FETCH_OP_GDS_AND_RET                     36
494848b8605Smrg#define FETCH_OP_GDS_OR_RET                      37
495848b8605Smrg#define FETCH_OP_GDS_XOR_RET                     38
496848b8605Smrg#define FETCH_OP_GDS_MSKOR_RET                   39
497848b8605Smrg#define FETCH_OP_GDS_XCHG_RET                    40
498848b8605Smrg#define FETCH_OP_GDS_XCHG_REL_RET                41
499848b8605Smrg#define FETCH_OP_GDS_XCHG2_RET                   42
500848b8605Smrg#define FETCH_OP_GDS_CMP_XCHG_RET                43
501848b8605Smrg#define FETCH_OP_GDS_CMP_XCHG_SPF_RET            44
502848b8605Smrg#define FETCH_OP_GDS_READ_RET                    45
503848b8605Smrg#define FETCH_OP_GDS_READ_REL_RET                46
504848b8605Smrg#define FETCH_OP_GDS_READ2_RET                   47
505848b8605Smrg#define FETCH_OP_GDS_READWRITE_RET               48
506848b8605Smrg#define FETCH_OP_GDS_BYTE_READ_RET               49
507848b8605Smrg#define FETCH_OP_GDS_UBYTE_READ_RET              50
508848b8605Smrg#define FETCH_OP_GDS_SHORT_READ_RET              51
509848b8605Smrg#define FETCH_OP_GDS_USHORT_READ_RET             52
510848b8605Smrg#define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC        53
511848b8605Smrg#define FETCH_OP_TF_WRITE                        54
512848b8605Smrg#define FETCH_OP_DS_GLOBAL_WRITE                 55
513848b8605Smrg#define FETCH_OP_DS_GLOBAL_READ                  56
514848b8605Smrg#define FETCH_OP_LD                              57
515848b8605Smrg#define FETCH_OP_LDFPTR                          58
516848b8605Smrg#define FETCH_OP_GET_TEXTURE_RESINFO             59
517848b8605Smrg#define FETCH_OP_GET_NUMBER_OF_SAMPLES           60
518848b8605Smrg#define FETCH_OP_GET_LOD                         61
519848b8605Smrg#define FETCH_OP_GET_GRADIENTS_H                 62
520848b8605Smrg#define FETCH_OP_GET_GRADIENTS_V                 63
521848b8605Smrg#define FETCH_OP_GET_GRADIENTS_H_FINE            64
522848b8605Smrg#define FETCH_OP_GET_GRADIENTS_V_FINE            65
523848b8605Smrg#define FETCH_OP_GET_LERP                        66
524848b8605Smrg#define FETCH_OP_SET_TEXTURE_OFFSETS             67
525848b8605Smrg#define FETCH_OP_KEEP_GRADIENTS                  68
526848b8605Smrg#define FETCH_OP_SET_GRADIENTS_H                 69
527848b8605Smrg#define FETCH_OP_SET_GRADIENTS_V                 70
528848b8605Smrg#define FETCH_OP_SET_GRADIENTS_H_COARSE          71
529848b8605Smrg#define FETCH_OP_SET_GRADIENTS_V_COARSE          72
530848b8605Smrg#define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE     73
531848b8605Smrg#define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE     74
532848b8605Smrg#define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE   75
533848b8605Smrg#define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE   76
534848b8605Smrg#define FETCH_OP_PASS                            77
535848b8605Smrg#define FETCH_OP_PASS1                           78
536848b8605Smrg#define FETCH_OP_PASS2                           79
537848b8605Smrg#define FETCH_OP_PASS3                           80
538848b8605Smrg#define FETCH_OP_SET_CUBEMAP_INDEX               81
539848b8605Smrg#define FETCH_OP_GET_BUFFER_RESINFO              82
540848b8605Smrg#define FETCH_OP_FETCH4                          83
541848b8605Smrg#define FETCH_OP_SAMPLE                          84
542848b8605Smrg#define FETCH_OP_SAMPLE_L                        85
543848b8605Smrg#define FETCH_OP_SAMPLE_LB                       86
544848b8605Smrg#define FETCH_OP_SAMPLE_LZ                       87
545848b8605Smrg#define FETCH_OP_SAMPLE_G                        88
546848b8605Smrg#define FETCH_OP_SAMPLE_G_L                      89
547848b8605Smrg#define FETCH_OP_GATHER4                         90
548848b8605Smrg#define FETCH_OP_SAMPLE_G_LB                     91
549848b8605Smrg#define FETCH_OP_SAMPLE_G_LZ                     92
550848b8605Smrg#define FETCH_OP_GATHER4_O                       93
551848b8605Smrg#define FETCH_OP_SAMPLE_C                        94
552848b8605Smrg#define FETCH_OP_SAMPLE_C_L                      95
553848b8605Smrg#define FETCH_OP_SAMPLE_C_LB                     96
554848b8605Smrg#define FETCH_OP_SAMPLE_C_LZ                     97
555848b8605Smrg#define FETCH_OP_SAMPLE_C_G                      98
556848b8605Smrg#define FETCH_OP_SAMPLE_C_G_L                    99
557848b8605Smrg#define FETCH_OP_GATHER4_C                      100
558848b8605Smrg#define FETCH_OP_SAMPLE_C_G_LB                  101
559848b8605Smrg#define FETCH_OP_SAMPLE_C_G_LZ                  102
560848b8605Smrg#define FETCH_OP_GATHER4_C_O                    103
561848b8605Smrg
562848b8605Smrg#define CF_OP_NOP                           0
563848b8605Smrg#define CF_OP_TEX                           1
564848b8605Smrg#define CF_OP_VTX                           2
565848b8605Smrg#define CF_OP_VTX_TC                        3
566848b8605Smrg#define CF_OP_GDS                           4
567848b8605Smrg#define CF_OP_LOOP_START                    5
568848b8605Smrg#define CF_OP_LOOP_END                      6
569848b8605Smrg#define CF_OP_LOOP_START_DX10               7
570848b8605Smrg#define CF_OP_LOOP_START_NO_AL              8
571848b8605Smrg#define CF_OP_LOOP_CONTINUE                 9
572848b8605Smrg#define CF_OP_LOOP_BREAK                   10
573848b8605Smrg#define CF_OP_JUMP                         11
574848b8605Smrg#define CF_OP_PUSH                         12
575848b8605Smrg#define CF_OP_PUSH_ELSE                    13
576848b8605Smrg#define CF_OP_ELSE                         14
577848b8605Smrg#define CF_OP_POP                          15
578848b8605Smrg#define CF_OP_POP_JUMP                     16
579848b8605Smrg#define CF_OP_POP_PUSH                     17
580848b8605Smrg#define CF_OP_POP_PUSH_ELSE                18
581848b8605Smrg#define CF_OP_CALL                         19
582848b8605Smrg#define CF_OP_CALL_FS                      20
583848b8605Smrg#define CF_OP_RET                          21
584848b8605Smrg#define CF_OP_EMIT_VERTEX                  22
585848b8605Smrg#define CF_OP_EMIT_CUT_VERTEX              23
586848b8605Smrg#define CF_OP_CUT_VERTEX                   24
587848b8605Smrg#define CF_OP_KILL                         25
588848b8605Smrg#define CF_OP_END_PROGRAM                  26
589848b8605Smrg#define CF_OP_WAIT_ACK                     27
590848b8605Smrg#define CF_OP_TEX_ACK                      28
591848b8605Smrg#define CF_OP_VTX_ACK                      29
592848b8605Smrg#define CF_OP_VTX_TC_ACK                   30
593848b8605Smrg#define CF_OP_JUMPTABLE                    31
594848b8605Smrg#define CF_OP_WAVE_SYNC                    32
595848b8605Smrg#define CF_OP_HALT                         33
596848b8605Smrg#define CF_OP_CF_END                       34
597848b8605Smrg#define CF_OP_LDS_DEALLOC                  35
598848b8605Smrg#define CF_OP_PUSH_WQM                     36
599848b8605Smrg#define CF_OP_POP_WQM                      37
600848b8605Smrg#define CF_OP_ELSE_WQM                     38
601848b8605Smrg#define CF_OP_JUMP_ANY                     39
602848b8605Smrg#define CF_OP_REACTIVATE                   40
603848b8605Smrg#define CF_OP_REACTIVATE_WQM               41
604848b8605Smrg#define CF_OP_INTERRUPT                    42
605848b8605Smrg#define CF_OP_INTERRUPT_AND_SLEEP          43
606848b8605Smrg#define CF_OP_SET_PRIORITY                 44
607848b8605Smrg#define CF_OP_MEM_STREAM0_BUF0             45
608848b8605Smrg#define CF_OP_MEM_STREAM0_BUF1             46
609848b8605Smrg#define CF_OP_MEM_STREAM0_BUF2             47
610848b8605Smrg#define CF_OP_MEM_STREAM0_BUF3             48
611848b8605Smrg#define CF_OP_MEM_STREAM1_BUF0             49
612848b8605Smrg#define CF_OP_MEM_STREAM1_BUF1             50
613848b8605Smrg#define CF_OP_MEM_STREAM1_BUF2             51
614848b8605Smrg#define CF_OP_MEM_STREAM1_BUF3             52
615848b8605Smrg#define CF_OP_MEM_STREAM2_BUF0             53
616848b8605Smrg#define CF_OP_MEM_STREAM2_BUF1             54
617848b8605Smrg#define CF_OP_MEM_STREAM2_BUF2             55
618848b8605Smrg#define CF_OP_MEM_STREAM2_BUF3             56
619848b8605Smrg#define CF_OP_MEM_STREAM3_BUF0             57
620848b8605Smrg#define CF_OP_MEM_STREAM3_BUF1             58
621848b8605Smrg#define CF_OP_MEM_STREAM3_BUF2             59
622848b8605Smrg#define CF_OP_MEM_STREAM3_BUF3             60
623848b8605Smrg#define CF_OP_MEM_STREAM0                  61
624848b8605Smrg#define CF_OP_MEM_STREAM1                  62
625848b8605Smrg#define CF_OP_MEM_STREAM2                  63
626848b8605Smrg#define CF_OP_MEM_STREAM3                  64
627848b8605Smrg#define CF_OP_MEM_SCRATCH                  65
628848b8605Smrg#define CF_OP_MEM_REDUCT                   66
629848b8605Smrg#define CF_OP_MEM_RING                     67
630848b8605Smrg#define CF_OP_EXPORT                       68
631848b8605Smrg#define CF_OP_EXPORT_DONE                  69
632848b8605Smrg#define CF_OP_MEM_EXPORT                   70
633848b8605Smrg#define CF_OP_MEM_RAT                      71
634848b8605Smrg#define CF_OP_MEM_RAT_NOCACHE              72
635848b8605Smrg#define CF_OP_MEM_RING1                    73
636848b8605Smrg#define CF_OP_MEM_RING2                    74
637848b8605Smrg#define CF_OP_MEM_RING3                    75
638848b8605Smrg#define CF_OP_MEM_MEM_COMBINED             76
639848b8605Smrg#define CF_OP_MEM_RAT_COMBINED_NOCACHE     77
640848b8605Smrg#define CF_OP_MEM_RAT_COMBINED             78
641848b8605Smrg#define CF_OP_EXPORT_DONE_END              79
642848b8605Smrg#define CF_OP_ALU                          80
643848b8605Smrg#define CF_OP_ALU_PUSH_BEFORE              81
644848b8605Smrg#define CF_OP_ALU_POP_AFTER                82
645848b8605Smrg#define CF_OP_ALU_POP2_AFTER               83
646848b8605Smrg#define CF_OP_ALU_EXT                      84
647848b8605Smrg#define CF_OP_ALU_CONTINUE                 85
648848b8605Smrg#define CF_OP_ALU_BREAK                    86
649b8e80941Smrg#define CF_OP_ALU_VALID_PIXEL_MODE         87
650b8e80941Smrg#define CF_OP_ALU_ELSE_AFTER               88
651848b8605Smrg
652848b8605Smrg/* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
653b8e80941Smrg#define CF_NATIVE                          89
654848b8605Smrg
655848b8605Smrgenum r600_chip_class {
656848b8605Smrg	ISA_CC_R600,
657848b8605Smrg	ISA_CC_R700,
658848b8605Smrg	ISA_CC_EVERGREEN,
659848b8605Smrg	ISA_CC_CAYMAN
660848b8605Smrg};
661848b8605Smrg
662848b8605Smrgstruct r600_isa {
663848b8605Smrg	enum r600_chip_class hw_class;
664848b8605Smrg
665848b8605Smrg	/* these arrays provide reverse mapping - opcode => table_index,
666848b8605Smrg	 * typically we don't need such lookup, unless we are decoding the native
667848b8605Smrg	 * bytecode (e.g. when reading the bytestream from llvm backend) */
668848b8605Smrg	unsigned *alu_op2_map;
669848b8605Smrg	unsigned *alu_op3_map;
670848b8605Smrg	unsigned *fetch_map;
671848b8605Smrg	unsigned *cf_map;
672848b8605Smrg};
673848b8605Smrg
674848b8605Smrgstruct r600_context;
675848b8605Smrg
676848b8605Smrgint r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);
677848b8605Smrgint r600_isa_destroy(struct r600_isa *isa);
678848b8605Smrg
679b8e80941Smrgextern const struct alu_op_info r600_alu_op_table[];
680848b8605Smrg
681b8e80941Smrgunsigned
682b8e80941Smrgr600_alu_op_table_size(void);
683848b8605Smrg
684b8e80941Smrgconst struct alu_op_info *
685b8e80941Smrgr600_isa_alu(unsigned op);
686848b8605Smrg
687b8e80941Smrgconst struct fetch_op_info *
688b8e80941Smrgr600_isa_fetch(unsigned op);
689b8e80941Smrg
690b8e80941Smrgconst struct cf_op_info *
691b8e80941Smrgr600_isa_cf(unsigned op);
692848b8605Smrg
693848b8605Smrgstatic inline unsigned
694848b8605Smrgr600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
695848b8605Smrg	int opc =  r600_isa_alu(op)->opcode[chip_class >> 1];
696848b8605Smrg	assert(opc != -1);
697848b8605Smrg	return opc;
698848b8605Smrg}
699848b8605Smrg
700848b8605Smrgstatic inline unsigned
701848b8605Smrgr600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {
702848b8605Smrg	unsigned slots = r600_isa_alu(op)->slots[chip_class];
703848b8605Smrg	assert(slots != 0);
704848b8605Smrg	return slots;
705848b8605Smrg}
706848b8605Smrg
707848b8605Smrgstatic inline unsigned
708848b8605Smrgr600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {
709848b8605Smrg	int opc = r600_isa_fetch(op)->opcode[chip_class];
710848b8605Smrg	assert(opc != -1);
711848b8605Smrg	return opc;
712848b8605Smrg}
713848b8605Smrg
714848b8605Smrgstatic inline unsigned
715848b8605Smrgr600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
716848b8605Smrg	int opc = r600_isa_cf(op)->opcode[chip_class];
717848b8605Smrg	assert(opc != -1);
718848b8605Smrg	return opc;
719848b8605Smrg}
720848b8605Smrg
721848b8605Smrgstatic inline unsigned
722848b8605Smrgr600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
723848b8605Smrg	unsigned op;
724848b8605Smrg	if (is_op3) {
725848b8605Smrg		assert(isa->alu_op3_map);
726848b8605Smrg		op = isa->alu_op3_map[opcode];
727848b8605Smrg	} else {
728848b8605Smrg		assert(isa->alu_op2_map);
729848b8605Smrg		op = isa->alu_op2_map[opcode];
730848b8605Smrg	}
731848b8605Smrg	assert(op);
732848b8605Smrg	return op - 1;
733848b8605Smrg}
734848b8605Smrg
735848b8605Smrgstatic inline unsigned
736848b8605Smrgr600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
737848b8605Smrg	unsigned op;
738848b8605Smrg	assert(isa->fetch_map);
739848b8605Smrg	op = isa->fetch_map[opcode];
740848b8605Smrg	assert(op);
741848b8605Smrg	return op - 1;
742848b8605Smrg}
743848b8605Smrg
744848b8605Smrgstatic inline unsigned
745848b8605Smrgr600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
746848b8605Smrg	unsigned op;
747848b8605Smrg	assert(isa->cf_map);
748848b8605Smrg	/* using offset for CF_ALU_xxx opcodes because they overlap with other
749848b8605Smrg	 * CF opcodes (they use different encoding in hw) */
750848b8605Smrg	op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];
751848b8605Smrg	assert(op);
752848b8605Smrg	return op - 1;
753848b8605Smrg}
754848b8605Smrg
755b8e80941Smrg#ifdef __cplusplus
756b8e80941Smrg} /* extern "C" */
757b8e80941Smrg#endif
758b8e80941Smrg
759848b8605Smrg#endif /* R600_ISA_H_ */
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