si_get.c revision b8e80941
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#include "si_pipe.h" 26#include "radeon/radeon_video.h" 27#include "radeon/radeon_vce.h" 28#include "radeon/radeon_uvd_enc.h" 29#include "ac_llvm_util.h" 30#include "vl/vl_decoder.h" 31#include "vl/vl_video_buffer.h" 32#include "util/u_screen.h" 33#include "util/u_video.h" 34#include "compiler/nir/nir.h" 35 36#include <sys/utsname.h> 37 38static const char *si_get_vendor(struct pipe_screen *pscreen) 39{ 40 /* Don't change this. Games such as Alien Isolation are broken if this 41 * returns "Advanced Micro Devices, Inc." 42 */ 43 return "X.Org"; 44} 45 46static const char *si_get_device_vendor(struct pipe_screen *pscreen) 47{ 48 return "AMD"; 49} 50 51static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 52{ 53 struct si_screen *sscreen = (struct si_screen *)pscreen; 54 55 switch (param) { 56 /* Supported features (boolean caps). */ 57 case PIPE_CAP_ACCELERATED: 58 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 59 case PIPE_CAP_ANISOTROPIC_FILTER: 60 case PIPE_CAP_POINT_SPRITE: 61 case PIPE_CAP_OCCLUSION_QUERY: 62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 63 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: 64 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 65 case PIPE_CAP_TEXTURE_SWIZZLE: 66 case PIPE_CAP_DEPTH_CLIP_DISABLE: 67 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 68 case PIPE_CAP_SHADER_STENCIL_EXPORT: 69 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 70 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 71 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 72 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 73 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 74 case PIPE_CAP_SM3: 75 case PIPE_CAP_SEAMLESS_CUBE_MAP: 76 case PIPE_CAP_PRIMITIVE_RESTART: 77 case PIPE_CAP_CONDITIONAL_RENDER: 78 case PIPE_CAP_TEXTURE_BARRIER: 79 case PIPE_CAP_INDEP_BLEND_ENABLE: 80 case PIPE_CAP_INDEP_BLEND_FUNC: 81 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 82 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 83 case PIPE_CAP_START_INSTANCE: 84 case PIPE_CAP_NPOT_TEXTURES: 85 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 86 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 87 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 88 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 89 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 90 case PIPE_CAP_TGSI_INSTANCEID: 91 case PIPE_CAP_COMPUTE: 92 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 93 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 94 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 96 case PIPE_CAP_CUBE_MAP_ARRAY: 97 case PIPE_CAP_SAMPLE_SHADING: 98 case PIPE_CAP_DRAW_INDIRECT: 99 case PIPE_CAP_CLIP_HALFZ: 100 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 101 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 102 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 103 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 104 case PIPE_CAP_TGSI_TEXCOORD: 105 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 106 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 107 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 108 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 109 case PIPE_CAP_SHAREABLE_SHADERS: 110 case PIPE_CAP_DEPTH_BOUNDS_TEST: 111 case PIPE_CAP_SAMPLER_VIEW_TARGET: 112 case PIPE_CAP_TEXTURE_QUERY_LOD: 113 case PIPE_CAP_TEXTURE_GATHER_SM5: 114 case PIPE_CAP_TGSI_TXQS: 115 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 116 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 117 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 118 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 119 case PIPE_CAP_INVALIDATE_BUFFER: 120 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 121 case PIPE_CAP_QUERY_BUFFER_OBJECT: 122 case PIPE_CAP_QUERY_MEMORY_INFO: 123 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 124 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 125 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 126 case PIPE_CAP_GENERATE_MIPMAP: 127 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 128 case PIPE_CAP_STRING_MARKER: 129 case PIPE_CAP_CLEAR_TEXTURE: 130 case PIPE_CAP_CULL_DISTANCE: 131 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 132 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 133 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 134 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 135 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 136 case PIPE_CAP_DOUBLES: 137 case PIPE_CAP_TGSI_TEX_TXF_LZ: 138 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 139 case PIPE_CAP_BINDLESS_TEXTURE: 140 case PIPE_CAP_QUERY_TIMESTAMP: 141 case PIPE_CAP_QUERY_TIME_ELAPSED: 142 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 143 case PIPE_CAP_QUERY_SO_OVERFLOW: 144 case PIPE_CAP_MEMOBJ: 145 case PIPE_CAP_LOAD_CONSTBUF: 146 case PIPE_CAP_INT64: 147 case PIPE_CAP_INT64_DIVMOD: 148 case PIPE_CAP_TGSI_CLOCK: 149 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 150 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 151 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 153 case PIPE_CAP_TGSI_BALLOT: 154 case PIPE_CAP_TGSI_VOTE: 155 case PIPE_CAP_TGSI_FS_FBFETCH: 156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK: 157 case PIPE_CAP_IMAGE_LOAD_FORMATTED: 158 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA: 159 case PIPE_CAP_TGSI_DIV: 160 return 1; 161 162 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 163 return !SI_BIG_ENDIAN && sscreen->info.has_userptr; 164 165 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 166 return sscreen->info.has_gpu_reset_status_query || 167 sscreen->info.has_gpu_reset_counter_query; 168 169 case PIPE_CAP_TEXTURE_MULTISAMPLE: 170 return sscreen->info.has_2d_tiling; 171 172 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 173 return SI_MAP_BUFFER_ALIGNMENT; 174 175 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 176 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 177 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 178 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 179 case PIPE_CAP_MAX_VERTEX_STREAMS: 180 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 181 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 182 return 4; 183 184 case PIPE_CAP_GLSL_FEATURE_LEVEL: 185 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 186 if (sscreen->info.has_indirect_compute_dispatch) 187 return 450; 188 return 420; 189 190 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: 191 /* Optimal number for good TexSubImage performance on Polaris10. */ 192 return 64 * 1024 * 1024; 193 194 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 195 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: 196 return MIN2(sscreen->info.max_alloc_size, INT_MAX); 197 198 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 199 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 200 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 201 return !sscreen->info.has_unaligned_shader_loads; 202 203 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 204 return sscreen->info.has_sparse_vm_mappings ? 205 RADEON_SPARSE_PAGE_SIZE : 0; 206 207 case PIPE_CAP_PACKED_UNIFORMS: 208 if (sscreen->options.enable_nir) 209 return 1; 210 return 0; 211 212 /* Unsupported features. */ 213 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 214 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 215 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 216 case PIPE_CAP_USER_VERTEX_BUFFERS: 217 case PIPE_CAP_FAKE_SW_MSAA: 218 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 219 case PIPE_CAP_VERTEXID_NOBASE: 220 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 221 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 222 case PIPE_CAP_UMA: 223 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 224 case PIPE_CAP_POST_DEPTH_COVERAGE: 225 case PIPE_CAP_TILE_RASTER_ORDER: 226 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 227 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 228 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: 229 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: 230 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: 231 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: 232 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: 233 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: 234 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: 235 return 0; 236 237 case PIPE_CAP_FENCE_SIGNAL: 238 return sscreen->info.has_syncobj; 239 240 case PIPE_CAP_CONSTBUF0_FLAGS: 241 return SI_RESOURCE_FLAG_32BIT; 242 243 case PIPE_CAP_NATIVE_FENCE_FD: 244 return sscreen->info.has_fence_to_handle; 245 246 case PIPE_CAP_DRAW_PARAMETERS: 247 case PIPE_CAP_MULTI_DRAW_INDIRECT: 248 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 249 return sscreen->has_draw_indirect_multi; 250 251 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 252 return 30; 253 254 case PIPE_CAP_MAX_VARYINGS: 255 return 32; 256 257 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 258 return sscreen->info.chip_class <= VI ? 259 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0; 260 261 /* Stream output. */ 262 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 263 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 264 return 32*4; 265 266 /* Geometry shader output. */ 267 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 268 return 1024; 269 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 270 return 4095; 271 case PIPE_CAP_MAX_GS_INVOCATIONS: 272 /* The closed driver exposes 127, but 125 is the greatest 273 * number that works. */ 274 return 125; 275 276 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 277 return 2048; 278 279 /* Texturing. */ 280 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 281 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 282 return 15; /* 16384 */ 283 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 284 /* textures support 8192, but layered rendering supports 2048 */ 285 return 12; 286 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 287 /* textures support 8192, but layered rendering supports 2048 */ 288 return 2048; 289 290 /* Viewports and render targets. */ 291 case PIPE_CAP_MAX_VIEWPORTS: 292 return SI_MAX_VIEWPORTS; 293 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 294 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS: 295 case PIPE_CAP_MAX_RENDER_TARGETS: 296 return 8; 297 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: 298 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0; 299 300 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 301 case PIPE_CAP_MIN_TEXEL_OFFSET: 302 return -32; 303 304 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 305 case PIPE_CAP_MAX_TEXEL_OFFSET: 306 return 31; 307 308 case PIPE_CAP_ENDIANNESS: 309 return PIPE_ENDIAN_LITTLE; 310 311 case PIPE_CAP_VENDOR_ID: 312 return ATI_VENDOR_ID; 313 case PIPE_CAP_DEVICE_ID: 314 return sscreen->info.pci_id; 315 case PIPE_CAP_VIDEO_MEMORY: 316 return sscreen->info.vram_size >> 20; 317 case PIPE_CAP_PCI_GROUP: 318 return sscreen->info.pci_domain; 319 case PIPE_CAP_PCI_BUS: 320 return sscreen->info.pci_bus; 321 case PIPE_CAP_PCI_DEVICE: 322 return sscreen->info.pci_dev; 323 case PIPE_CAP_PCI_FUNCTION: 324 return sscreen->info.pci_func; 325 326 default: 327 return u_pipe_screen_get_param_defaults(pscreen, param); 328 } 329} 330 331static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param) 332{ 333 switch (param) { 334 case PIPE_CAPF_MAX_LINE_WIDTH: 335 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 336 /* This depends on the quant mode, though the precise interactions 337 * are unknown. */ 338 return 2048; 339 case PIPE_CAPF_MAX_POINT_WIDTH: 340 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 341 return SI_MAX_POINT_SIZE; 342 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 343 return 16.0f; 344 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 345 return 16.0f; 346 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 347 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 348 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 349 return 0.0f; 350 } 351 return 0.0f; 352} 353 354static int si_get_shader_param(struct pipe_screen* pscreen, 355 enum pipe_shader_type shader, 356 enum pipe_shader_cap param) 357{ 358 struct si_screen *sscreen = (struct si_screen *)pscreen; 359 360 switch(shader) 361 { 362 case PIPE_SHADER_FRAGMENT: 363 case PIPE_SHADER_VERTEX: 364 case PIPE_SHADER_GEOMETRY: 365 case PIPE_SHADER_TESS_CTRL: 366 case PIPE_SHADER_TESS_EVAL: 367 break; 368 case PIPE_SHADER_COMPUTE: 369 switch (param) { 370 case PIPE_SHADER_CAP_SUPPORTED_IRS: { 371 int ir = 1 << PIPE_SHADER_IR_NATIVE; 372 373 if (sscreen->info.has_indirect_compute_dispatch) 374 ir |= 1 << PIPE_SHADER_IR_TGSI; 375 376 return ir; 377 } 378 379 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: { 380 uint64_t max_const_buffer_size; 381 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI, 382 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 383 &max_const_buffer_size); 384 return MIN2(max_const_buffer_size, INT_MAX); 385 } 386 default: 387 /* If compute shaders don't require a special value 388 * for this cap, we can return the same value we 389 * do for other shader types. */ 390 break; 391 } 392 break; 393 default: 394 return 0; 395 } 396 397 switch (param) { 398 /* Shader limits. */ 399 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 400 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 401 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 402 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 403 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 404 return 16384; 405 case PIPE_SHADER_CAP_MAX_INPUTS: 406 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32; 407 case PIPE_SHADER_CAP_MAX_OUTPUTS: 408 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32; 409 case PIPE_SHADER_CAP_MAX_TEMPS: 410 return 256; /* Max native temporaries. */ 411 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 412 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */ 413 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 414 return SI_NUM_CONST_BUFFERS; 415 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 416 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 417 return SI_NUM_SAMPLERS; 418 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 419 return SI_NUM_SHADER_BUFFERS; 420 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 421 return SI_NUM_IMAGES; 422 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 423 if (sscreen->options.enable_nir) 424 return 0; 425 return 32; 426 case PIPE_SHADER_CAP_PREFERRED_IR: 427 if (sscreen->options.enable_nir) 428 return PIPE_SHADER_IR_NIR; 429 return PIPE_SHADER_IR_TGSI; 430 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 431 return 4; 432 433 /* Supported boolean features. */ 434 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 435 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 436 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 437 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 438 case PIPE_SHADER_CAP_INTEGERS: 439 case PIPE_SHADER_CAP_INT64_ATOMICS: 440 case PIPE_SHADER_CAP_FP16: 441 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 442 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 443 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 444 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 445 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 446 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 447 return 1; 448 449 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 450 /* TODO: Indirect indexing of GS inputs is unimplemented. */ 451 if (shader == PIPE_SHADER_GEOMETRY) 452 return 0; 453 454 if (shader == PIPE_SHADER_VERTEX && 455 !sscreen->llvm_has_working_vgpr_indexing) 456 return 0; 457 458 /* TCS and TES load inputs directly from LDS or offchip 459 * memory, so indirect indexing is always supported. 460 * PS has to support indirect indexing, because we can't 461 * lower that to TEMPs for INTERP instructions. 462 */ 463 return 1; 464 465 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 466 return sscreen->llvm_has_working_vgpr_indexing || 467 /* TCS stores outputs directly to memory. */ 468 shader == PIPE_SHADER_TESS_CTRL; 469 470 /* Unsupported boolean features. */ 471 case PIPE_SHADER_CAP_SUBROUTINES: 472 case PIPE_SHADER_CAP_SUPPORTED_IRS: 473 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 474 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 475 return 0; 476 case PIPE_SHADER_CAP_SCALAR_ISA: 477 return 1; 478 } 479 return 0; 480} 481 482static const struct nir_shader_compiler_options nir_options = { 483 .lower_scmp = true, 484 .lower_flrp32 = true, 485 .lower_flrp64 = true, 486 .lower_fsat = true, 487 .lower_fdiv = true, 488 .lower_sub = true, 489 .lower_ffma = true, 490 .lower_pack_snorm_2x16 = true, 491 .lower_pack_snorm_4x8 = true, 492 .lower_pack_unorm_2x16 = true, 493 .lower_pack_unorm_4x8 = true, 494 .lower_unpack_snorm_2x16 = true, 495 .lower_unpack_snorm_4x8 = true, 496 .lower_unpack_unorm_2x16 = true, 497 .lower_unpack_unorm_4x8 = true, 498 .lower_extract_byte = true, 499 .lower_extract_word = true, 500 .optimize_sample_mask_in = true, 501 .max_unroll_iterations = 32, 502 .native_integers = true, 503}; 504 505static const void * 506si_get_compiler_options(struct pipe_screen *screen, 507 enum pipe_shader_ir ir, 508 enum pipe_shader_type shader) 509{ 510 assert(ir == PIPE_SHADER_IR_NIR); 511 return &nir_options; 512} 513 514static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid) 515{ 516 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE); 517} 518 519static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid) 520{ 521 struct si_screen *sscreen = (struct si_screen *)pscreen; 522 523 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE); 524} 525 526static const char* si_get_name(struct pipe_screen *pscreen) 527{ 528 struct si_screen *sscreen = (struct si_screen*)pscreen; 529 530 return sscreen->renderer_string; 531} 532 533static int si_get_video_param_no_decode(struct pipe_screen *screen, 534 enum pipe_video_profile profile, 535 enum pipe_video_entrypoint entrypoint, 536 enum pipe_video_cap param) 537{ 538 switch (param) { 539 case PIPE_VIDEO_CAP_SUPPORTED: 540 return vl_profile_supported(screen, profile, entrypoint); 541 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 542 return 1; 543 case PIPE_VIDEO_CAP_MAX_WIDTH: 544 case PIPE_VIDEO_CAP_MAX_HEIGHT: 545 return vl_video_buffer_max_size(screen); 546 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 547 return PIPE_FORMAT_NV12; 548 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 549 return false; 550 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 551 return false; 552 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 553 return true; 554 case PIPE_VIDEO_CAP_MAX_LEVEL: 555 return vl_level_supported(screen, profile); 556 default: 557 return 0; 558 } 559} 560 561static int si_get_video_param(struct pipe_screen *screen, 562 enum pipe_video_profile profile, 563 enum pipe_video_entrypoint entrypoint, 564 enum pipe_video_cap param) 565{ 566 struct si_screen *sscreen = (struct si_screen *)screen; 567 enum pipe_video_format codec = u_reduce_video_profile(profile); 568 569 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) { 570 switch (param) { 571 case PIPE_VIDEO_CAP_SUPPORTED: 572 return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && 573 (si_vce_is_fw_version_supported(sscreen) || 574 sscreen->info.family == CHIP_RAVEN || 575 sscreen->info.family == CHIP_RAVEN2)) || 576 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN && 577 (sscreen->info.family == CHIP_RAVEN || 578 sscreen->info.family == CHIP_RAVEN2 || 579 si_radeon_uvd_enc_supported(sscreen))); 580 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 581 return 1; 582 case PIPE_VIDEO_CAP_MAX_WIDTH: 583 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096; 584 case PIPE_VIDEO_CAP_MAX_HEIGHT: 585 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304; 586 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 587 return PIPE_FORMAT_NV12; 588 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 589 return false; 590 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 591 return false; 592 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 593 return true; 594 case PIPE_VIDEO_CAP_STACKED_FRAMES: 595 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2; 596 default: 597 return 0; 598 } 599 } 600 601 switch (param) { 602 case PIPE_VIDEO_CAP_SUPPORTED: 603 switch (codec) { 604 case PIPE_VIDEO_FORMAT_MPEG12: 605 return profile != PIPE_VIDEO_PROFILE_MPEG1; 606 case PIPE_VIDEO_FORMAT_MPEG4: 607 return 1; 608 case PIPE_VIDEO_FORMAT_MPEG4_AVC: 609 if ((sscreen->info.family == CHIP_POLARIS10 || 610 sscreen->info.family == CHIP_POLARIS11) && 611 sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) { 612 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n"); 613 return false; 614 } 615 return true; 616 case PIPE_VIDEO_FORMAT_VC1: 617 return true; 618 case PIPE_VIDEO_FORMAT_HEVC: 619 /* Carrizo only supports HEVC Main */ 620 if (sscreen->info.family >= CHIP_STONEY) 621 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN || 622 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10); 623 else if (sscreen->info.family >= CHIP_CARRIZO) 624 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN; 625 return false; 626 case PIPE_VIDEO_FORMAT_JPEG: 627 if (sscreen->info.family == CHIP_RAVEN || 628 sscreen->info.family == CHIP_RAVEN2) 629 return true; 630 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10) 631 return false; 632 if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) { 633 RVID_ERR("No MJPEG support for the kernel version\n"); 634 return false; 635 } 636 return true; 637 case PIPE_VIDEO_FORMAT_VP9: 638 if (sscreen->info.family < CHIP_RAVEN) 639 return false; 640 return true; 641 default: 642 return false; 643 } 644 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 645 return 1; 646 case PIPE_VIDEO_CAP_MAX_WIDTH: 647 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096; 648 case PIPE_VIDEO_CAP_MAX_HEIGHT: 649 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096; 650 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 651 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 || 652 profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) 653 return PIPE_FORMAT_P016; 654 else 655 return PIPE_FORMAT_NV12; 656 657 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 658 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: { 659 enum pipe_video_format format = u_reduce_video_profile(profile); 660 661 if (format == PIPE_VIDEO_FORMAT_HEVC) 662 return false; //The firmware doesn't support interlaced HEVC. 663 else if (format == PIPE_VIDEO_FORMAT_JPEG) 664 return false; 665 else if (format == PIPE_VIDEO_FORMAT_VP9) 666 return false; 667 return true; 668 } 669 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 670 return true; 671 case PIPE_VIDEO_CAP_MAX_LEVEL: 672 switch (profile) { 673 case PIPE_VIDEO_PROFILE_MPEG1: 674 return 0; 675 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE: 676 case PIPE_VIDEO_PROFILE_MPEG2_MAIN: 677 return 3; 678 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE: 679 return 3; 680 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE: 681 return 5; 682 case PIPE_VIDEO_PROFILE_VC1_SIMPLE: 683 return 1; 684 case PIPE_VIDEO_PROFILE_VC1_MAIN: 685 return 2; 686 case PIPE_VIDEO_PROFILE_VC1_ADVANCED: 687 return 4; 688 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE: 689 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN: 690 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH: 691 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52; 692 case PIPE_VIDEO_PROFILE_HEVC_MAIN: 693 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10: 694 return 186; 695 default: 696 return 0; 697 } 698 default: 699 return 0; 700 } 701} 702 703static boolean si_vid_is_format_supported(struct pipe_screen *screen, 704 enum pipe_format format, 705 enum pipe_video_profile profile, 706 enum pipe_video_entrypoint entrypoint) 707{ 708 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */ 709 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) 710 return (format == PIPE_FORMAT_NV12) || 711 (format == PIPE_FORMAT_P016); 712 713 /* we can only handle this one with UVD */ 714 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN) 715 return format == PIPE_FORMAT_NV12; 716 717 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint); 718} 719 720static unsigned get_max_threads_per_block(struct si_screen *screen, 721 enum pipe_shader_ir ir_type) 722{ 723 if (ir_type == PIPE_SHADER_IR_NATIVE) 724 return 256; 725 726 /* Only 16 waves per thread-group on gfx9. */ 727 if (screen->info.chip_class >= GFX9) 728 return 1024; 729 730 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice 731 * round number. 732 */ 733 return 2048; 734} 735 736static int si_get_compute_param(struct pipe_screen *screen, 737 enum pipe_shader_ir ir_type, 738 enum pipe_compute_cap param, 739 void *ret) 740{ 741 struct si_screen *sscreen = (struct si_screen *)screen; 742 743 //TODO: select these params by asic 744 switch (param) { 745 case PIPE_COMPUTE_CAP_IR_TARGET: { 746 const char *gpu, *triple; 747 748 triple = "amdgcn-mesa-mesa3d"; 749 gpu = ac_get_llvm_processor_name(sscreen->info.family); 750 if (ret) { 751 sprintf(ret, "%s-%s", gpu, triple); 752 } 753 /* +2 for dash and terminating NIL byte */ 754 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char); 755 } 756 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 757 if (ret) { 758 uint64_t *grid_dimension = ret; 759 grid_dimension[0] = 3; 760 } 761 return 1 * sizeof(uint64_t); 762 763 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 764 if (ret) { 765 uint64_t *grid_size = ret; 766 grid_size[0] = 65535; 767 grid_size[1] = 65535; 768 grid_size[2] = 65535; 769 } 770 return 3 * sizeof(uint64_t) ; 771 772 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 773 if (ret) { 774 uint64_t *block_size = ret; 775 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type); 776 block_size[0] = threads_per_block; 777 block_size[1] = threads_per_block; 778 block_size[2] = threads_per_block; 779 } 780 return 3 * sizeof(uint64_t); 781 782 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 783 if (ret) { 784 uint64_t *max_threads_per_block = ret; 785 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type); 786 } 787 return sizeof(uint64_t); 788 case PIPE_COMPUTE_CAP_ADDRESS_BITS: 789 if (ret) { 790 uint32_t *address_bits = ret; 791 address_bits[0] = 64; 792 } 793 return 1 * sizeof(uint32_t); 794 795 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 796 if (ret) { 797 uint64_t *max_global_size = ret; 798 uint64_t max_mem_alloc_size; 799 800 si_get_compute_param(screen, ir_type, 801 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 802 &max_mem_alloc_size); 803 804 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least 805 * 1/4 of the MAX_GLOBAL_SIZE. Since the 806 * MAX_MEM_ALLOC_SIZE is fixed for older kernels, 807 * make sure we never report more than 808 * 4 * MAX_MEM_ALLOC_SIZE. 809 */ 810 *max_global_size = MIN2(4 * max_mem_alloc_size, 811 MAX2(sscreen->info.gart_size, 812 sscreen->info.vram_size)); 813 } 814 return sizeof(uint64_t); 815 816 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 817 if (ret) { 818 uint64_t *max_local_size = ret; 819 /* Value reported by the closed source driver. */ 820 *max_local_size = 32768; 821 } 822 return sizeof(uint64_t); 823 824 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 825 if (ret) { 826 uint64_t *max_input_size = ret; 827 /* Value reported by the closed source driver. */ 828 *max_input_size = 1024; 829 } 830 return sizeof(uint64_t); 831 832 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: 833 if (ret) { 834 uint64_t *max_mem_alloc_size = ret; 835 836 *max_mem_alloc_size = sscreen->info.max_alloc_size; 837 } 838 return sizeof(uint64_t); 839 840 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: 841 if (ret) { 842 uint32_t *max_clock_frequency = ret; 843 *max_clock_frequency = sscreen->info.max_shader_clock; 844 } 845 return sizeof(uint32_t); 846 847 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: 848 if (ret) { 849 uint32_t *max_compute_units = ret; 850 *max_compute_units = sscreen->info.num_good_compute_units; 851 } 852 return sizeof(uint32_t); 853 854 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: 855 if (ret) { 856 uint32_t *images_supported = ret; 857 *images_supported = 0; 858 } 859 return sizeof(uint32_t); 860 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: 861 break; /* unused */ 862 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: 863 if (ret) { 864 uint32_t *subgroup_size = ret; 865 *subgroup_size = 64; 866 } 867 return sizeof(uint32_t); 868 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: 869 if (ret) { 870 uint64_t *max_variable_threads_per_block = ret; 871 if (ir_type == PIPE_SHADER_IR_NATIVE) 872 *max_variable_threads_per_block = 0; 873 else 874 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK; 875 } 876 return sizeof(uint64_t); 877 } 878 879 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); 880 return 0; 881} 882 883static uint64_t si_get_timestamp(struct pipe_screen *screen) 884{ 885 struct si_screen *sscreen = (struct si_screen*)screen; 886 887 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) / 888 sscreen->info.clock_crystal_freq; 889} 890 891static void si_query_memory_info(struct pipe_screen *screen, 892 struct pipe_memory_info *info) 893{ 894 struct si_screen *sscreen = (struct si_screen*)screen; 895 struct radeon_winsys *ws = sscreen->ws; 896 unsigned vram_usage, gtt_usage; 897 898 info->total_device_memory = sscreen->info.vram_size / 1024; 899 info->total_staging_memory = sscreen->info.gart_size / 1024; 900 901 /* The real TTM memory usage is somewhat random, because: 902 * 903 * 1) TTM delays freeing memory, because it can only free it after 904 * fences expire. 905 * 906 * 2) The memory usage can be really low if big VRAM evictions are 907 * taking place, but the real usage is well above the size of VRAM. 908 * 909 * Instead, return statistics of this process. 910 */ 911 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024; 912 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024; 913 914 info->avail_device_memory = 915 vram_usage <= info->total_device_memory ? 916 info->total_device_memory - vram_usage : 0; 917 info->avail_staging_memory = 918 gtt_usage <= info->total_staging_memory ? 919 info->total_staging_memory - gtt_usage : 0; 920 921 info->device_memory_evicted = 922 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024; 923 924 if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4) 925 info->nr_device_memory_evictions = 926 ws->query_value(ws, RADEON_NUM_EVICTIONS); 927 else 928 /* Just return the number of evicted 64KB pages. */ 929 info->nr_device_memory_evictions = info->device_memory_evicted / 64; 930} 931 932static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen) 933{ 934 struct si_screen *sscreen = (struct si_screen*)pscreen; 935 936 return sscreen->disk_shader_cache; 937} 938 939static void si_init_renderer_string(struct si_screen *sscreen) 940{ 941 char first_name[256], second_name[32] = {}, kernel_version[128] = {}; 942 struct utsname uname_data; 943 944 if (sscreen->info.marketing_name) { 945 snprintf(first_name, sizeof(first_name), "%s", 946 sscreen->info.marketing_name); 947 snprintf(second_name, sizeof(second_name), "%s, ", 948 sscreen->info.name); 949 } else { 950 snprintf(first_name, sizeof(first_name), "AMD %s", 951 sscreen->info.name); 952 } 953 954 if (uname(&uname_data) == 0) 955 snprintf(kernel_version, sizeof(kernel_version), 956 ", %s", uname_data.release); 957 958 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string), 959 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", 960 first_name, second_name, sscreen->info.drm_major, 961 sscreen->info.drm_minor, sscreen->info.drm_patchlevel, 962 kernel_version); 963} 964 965void si_init_screen_get_functions(struct si_screen *sscreen) 966{ 967 sscreen->b.get_name = si_get_name; 968 sscreen->b.get_vendor = si_get_vendor; 969 sscreen->b.get_device_vendor = si_get_device_vendor; 970 sscreen->b.get_param = si_get_param; 971 sscreen->b.get_paramf = si_get_paramf; 972 sscreen->b.get_compute_param = si_get_compute_param; 973 sscreen->b.get_timestamp = si_get_timestamp; 974 sscreen->b.get_shader_param = si_get_shader_param; 975 sscreen->b.get_compiler_options = si_get_compiler_options; 976 sscreen->b.get_device_uuid = si_get_device_uuid; 977 sscreen->b.get_driver_uuid = si_get_driver_uuid; 978 sscreen->b.query_memory_info = si_query_memory_info; 979 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache; 980 981 if (sscreen->info.has_hw_decode) { 982 sscreen->b.get_video_param = si_get_video_param; 983 sscreen->b.is_video_format_supported = si_vid_is_format_supported; 984 } else { 985 sscreen->b.get_video_param = si_get_video_param_no_decode; 986 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported; 987 } 988 989 si_init_renderer_string(sscreen); 990} 991