si_pm4.h revision 848b8605 
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *      Christian König <christian.koenig@amd.com>
25 */
26
27#ifndef SI_PM4_H
28#define SI_PM4_H
29
30#include "../../winsys/radeon/drm/radeon_winsys.h"
31
32#define SI_PM4_MAX_DW		256
33#define SI_PM4_MAX_BO		32
34#define SI_PM4_MAX_RELOCS	4
35
36// forward defines
37struct si_context;
38enum chip_class;
39
40struct si_pm4_state
41{
42	/* family specific handling */
43	enum chip_class chip_class;
44	/* PKT3_SET_*_REG handling */
45	unsigned	last_opcode;
46	unsigned	last_reg;
47	unsigned	last_pm4;
48
49	/* flush flags for SURFACE_SYNC */
50	uint32_t	cp_coher_cntl;
51
52	/* commands for the DE */
53	unsigned	ndw;
54	uint32_t	pm4[SI_PM4_MAX_DW];
55
56	/* BO's referenced by this state */
57	unsigned		nbo;
58	struct r600_resource	*bo[SI_PM4_MAX_BO];
59	enum radeon_bo_usage	bo_usage[SI_PM4_MAX_BO];
60	enum radeon_bo_priority	bo_priority[SI_PM4_MAX_BO];
61
62	/* relocs for shader data */
63	unsigned	nrelocs;
64	unsigned	relocs[SI_PM4_MAX_RELOCS];
65
66	bool compute_pkt;
67};
68
69void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
70void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
71void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
72
73void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
74void si_pm4_add_bo(struct si_pm4_state *state,
75		   struct r600_resource *bo,
76		   enum radeon_bo_usage usage,
77		   enum radeon_bo_priority priority);
78
79void si_pm4_inval_shader_cache(struct si_pm4_state *state);
80void si_pm4_inval_texture_cache(struct si_pm4_state *state);
81
82void si_pm4_free_state(struct si_context *sctx,
83		       struct si_pm4_state *state,
84		       unsigned idx);
85struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
86
87uint32_t si_pm4_sync_flags(struct si_context *sctx);
88unsigned si_pm4_dirty_dw(struct si_context *sctx);
89void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
90void si_pm4_emit_dirty(struct si_context *sctx);
91void si_pm4_reset_emitted(struct si_context *sctx);
92void si_pm4_cleanup(struct si_context *sctx);
93
94#endif
95