1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef SI_STATE_H
26#define SI_STATE_H
27
28#include "si_pm4.h"
29
30#include "pipebuffer/pb_slab.h"
31#include "util/u_blitter.h"
32
33#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
35
36#define SI_NUM_VERTEX_BUFFERS		SI_MAX_ATTRIBS
37#define SI_NUM_SAMPLERS			32 /* OpenGL textures units per shader */
38#define SI_NUM_CONST_BUFFERS		16
39#define SI_NUM_IMAGES			16
40#define SI_NUM_SHADER_BUFFERS		16
41
42struct si_screen;
43struct si_shader;
44struct si_shader_selector;
45struct si_texture;
46struct si_qbo_state;
47
48struct si_state_blend {
49	struct si_pm4_state	pm4;
50	uint32_t		cb_target_mask;
51	/* Set 0xf or 0x0 (4 bits) per render target if the following is
52	 * true. ANDed with spi_shader_col_format.
53	 */
54	unsigned		cb_target_enabled_4bit;
55	unsigned		blend_enable_4bit;
56	unsigned		need_src_alpha_4bit;
57	unsigned		commutative_4bit;
58	bool			alpha_to_coverage:1;
59	bool			alpha_to_one:1;
60	bool			dual_src_blend:1;
61	bool			logicop_enable:1;
62};
63
64struct si_state_rasterizer {
65	struct si_pm4_state	pm4;
66	/* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
67	struct si_pm4_state	*pm4_poly_offset;
68	unsigned		pa_sc_line_stipple;
69	unsigned		pa_cl_clip_cntl;
70	float			line_width;
71	float			max_point_size;
72	unsigned		sprite_coord_enable:8;
73	unsigned		clip_plane_enable:8;
74	unsigned		half_pixel_center:1;
75	unsigned		flatshade:1;
76	unsigned		two_side:1;
77	unsigned		multisample_enable:1;
78	unsigned		force_persample_interp:1;
79	unsigned		line_stipple_enable:1;
80	unsigned		poly_stipple_enable:1;
81	unsigned		line_smooth:1;
82	unsigned		poly_smooth:1;
83	unsigned		uses_poly_offset:1;
84	unsigned		clamp_fragment_color:1;
85	unsigned		clamp_vertex_color:1;
86	unsigned		rasterizer_discard:1;
87	unsigned		scissor_enable:1;
88	unsigned		clip_halfz:1;
89};
90
91struct si_dsa_stencil_ref_part {
92	uint8_t			valuemask[2];
93	uint8_t			writemask[2];
94};
95
96struct si_dsa_order_invariance {
97	/** Whether the final result in Z/S buffers is guaranteed to be
98	 * invariant under changes to the order in which fragments arrive. */
99	bool zs:1;
100
101	/** Whether the set of fragments that pass the combined Z/S test is
102	 * guaranteed to be invariant under changes to the order in which
103	 * fragments arrive. */
104	bool pass_set:1;
105
106	/** Whether the last fragment that passes the combined Z/S test at each
107	 * sample is guaranteed to be invariant under changes to the order in
108	 * which fragments arrive. */
109	bool pass_last:1;
110};
111
112struct si_state_dsa {
113	struct si_pm4_state		pm4;
114	struct si_dsa_stencil_ref_part	stencil_ref;
115
116	/* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
117	struct si_dsa_order_invariance	order_invariance[2];
118
119	ubyte				alpha_func:3;
120	bool				depth_enabled:1;
121	bool				depth_write_enabled:1;
122	bool				stencil_enabled:1;
123	bool				stencil_write_enabled:1;
124	bool				db_can_write:1;
125
126};
127
128struct si_stencil_ref {
129	struct pipe_stencil_ref		state;
130	struct si_dsa_stencil_ref_part	dsa_part;
131};
132
133struct si_vertex_elements
134{
135	struct si_resource		*instance_divisor_factor_buffer;
136	uint32_t			rsrc_word3[SI_MAX_ATTRIBS];
137	uint16_t			src_offset[SI_MAX_ATTRIBS];
138	uint8_t				fix_fetch[SI_MAX_ATTRIBS];
139	uint8_t				format_size[SI_MAX_ATTRIBS];
140	uint8_t				vertex_buffer_index[SI_MAX_ATTRIBS];
141
142	uint8_t				count;
143	bool				uses_instance_divisors;
144
145	uint16_t			first_vb_use_mask;
146	/* Vertex buffer descriptor list size aligned for optimal prefetch. */
147	uint16_t			desc_list_byte_size;
148	uint16_t			instance_divisor_is_one; /* bitmask of inputs */
149	uint16_t			instance_divisor_is_fetched;  /* bitmask of inputs */
150};
151
152union si_state {
153	struct {
154		struct si_state_blend		*blend;
155		struct si_state_rasterizer	*rasterizer;
156		struct si_state_dsa		*dsa;
157		struct si_pm4_state		*poly_offset;
158		struct si_pm4_state		*ls;
159		struct si_pm4_state		*hs;
160		struct si_pm4_state		*es;
161		struct si_pm4_state		*gs;
162		struct si_pm4_state		*vgt_shader_config;
163		struct si_pm4_state		*vs;
164		struct si_pm4_state		*ps;
165	} named;
166	struct si_pm4_state	*array[0];
167};
168
169#define SI_STATE_IDX(name) \
170	(offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
171#define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
172#define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
173
174static inline unsigned si_states_that_always_roll_context(void)
175{
176	return (SI_STATE_BIT(blend) |
177		SI_STATE_BIT(rasterizer) |
178		SI_STATE_BIT(dsa) |
179		SI_STATE_BIT(poly_offset) |
180		SI_STATE_BIT(vgt_shader_config));
181}
182
183union si_state_atoms {
184	struct {
185		/* The order matters. */
186		struct si_atom render_cond;
187		struct si_atom streamout_begin;
188		struct si_atom streamout_enable; /* must be after streamout_begin */
189		struct si_atom framebuffer;
190		struct si_atom msaa_sample_locs;
191		struct si_atom db_render_state;
192		struct si_atom dpbb_state;
193		struct si_atom msaa_config;
194		struct si_atom sample_mask;
195		struct si_atom cb_render_state;
196		struct si_atom blend_color;
197		struct si_atom clip_regs;
198		struct si_atom clip_state;
199		struct si_atom shader_pointers;
200		struct si_atom guardband;
201		struct si_atom scissors;
202		struct si_atom viewports;
203		struct si_atom stencil_ref;
204		struct si_atom spi_map;
205		struct si_atom scratch_state;
206		struct si_atom window_rectangles;
207	} s;
208	struct si_atom array[0];
209};
210
211#define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
212			         sizeof(struct si_atom)))
213#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
214
215static inline unsigned si_atoms_that_always_roll_context(void)
216{
217	return (SI_ATOM_BIT(streamout_begin) |
218		SI_ATOM_BIT(streamout_enable) |
219		SI_ATOM_BIT(framebuffer) |
220		SI_ATOM_BIT(msaa_sample_locs) |
221		SI_ATOM_BIT(sample_mask) |
222		SI_ATOM_BIT(blend_color) |
223		SI_ATOM_BIT(clip_state) |
224		SI_ATOM_BIT(scissors) |
225		SI_ATOM_BIT(viewports) |
226		SI_ATOM_BIT(stencil_ref) |
227		SI_ATOM_BIT(scratch_state) |
228		SI_ATOM_BIT(window_rectangles));
229}
230
231struct si_shader_data {
232	uint32_t		sh_base[SI_NUM_SHADERS];
233};
234
235/* The list of registers whose emitted values are remembered by si_context. */
236enum si_tracked_reg {
237	SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
238	SI_TRACKED_DB_COUNT_CONTROL,
239
240	SI_TRACKED_DB_RENDER_OVERRIDE2,
241	SI_TRACKED_DB_SHADER_CONTROL,
242
243	SI_TRACKED_CB_TARGET_MASK,
244	SI_TRACKED_CB_DCC_CONTROL,
245
246	SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
247	SI_TRACKED_SX_BLEND_OPT_EPSILON,
248	SI_TRACKED_SX_BLEND_OPT_CONTROL,
249
250	SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
251	SI_TRACKED_PA_SC_AA_CONFIG,
252
253	SI_TRACKED_DB_EQAA,
254	SI_TRACKED_PA_SC_MODE_CNTL_1,
255
256	SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
257	SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
258
259	SI_TRACKED_PA_CL_VS_OUT_CNTL,
260	SI_TRACKED_PA_CL_CLIP_CNTL,
261
262	SI_TRACKED_PA_SC_BINNER_CNTL_0,
263	SI_TRACKED_DB_DFSM_CONTROL,
264
265	SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
266	SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
267	SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
268	SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
269
270	SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
271	SI_TRACKED_PA_SU_VTX_CNTL,
272
273	SI_TRACKED_PA_SC_CLIPRECT_RULE,
274
275	SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
276
277	SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 4 consecutive registers */
278	SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
279	SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
280	SI_TRACKED_VGT_GS_OUT_PRIM_TYPE,
281
282	SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
283	SI_TRACKED_VGT_GS_MAX_VERT_OUT,
284
285	SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
286	SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
287	SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
288	SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
289
290	SI_TRACKED_VGT_GS_INSTANCE_CNT,
291	SI_TRACKED_VGT_GS_ONCHIP_CNTL,
292	SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
293	SI_TRACKED_VGT_GS_MODE,
294	SI_TRACKED_VGT_PRIMITIVEID_EN,
295	SI_TRACKED_VGT_REUSE_OFF,
296	SI_TRACKED_SPI_VS_OUT_CONFIG,
297	SI_TRACKED_SPI_SHADER_POS_FORMAT,
298	SI_TRACKED_PA_CL_VTE_CNTL,
299
300	SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
301	SI_TRACKED_SPI_PS_INPUT_ADDR,
302
303	SI_TRACKED_SPI_BARYC_CNTL,
304	SI_TRACKED_SPI_PS_IN_CONTROL,
305
306	SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
307	SI_TRACKED_SPI_SHADER_COL_FORMAT,
308
309	SI_TRACKED_CB_SHADER_MASK,
310	SI_TRACKED_VGT_TF_PARAM,
311	SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
312
313	SI_NUM_TRACKED_REGS,
314};
315
316struct si_tracked_regs {
317	uint64_t		reg_saved;
318	uint32_t		reg_value[SI_NUM_TRACKED_REGS];
319	uint32_t		spi_ps_input_cntl[32];
320};
321
322/* Private read-write buffer slots. */
323enum {
324	SI_ES_RING_ESGS,
325	SI_GS_RING_ESGS,
326
327	SI_RING_GSVS,
328
329	SI_VS_STREAMOUT_BUF0,
330	SI_VS_STREAMOUT_BUF1,
331	SI_VS_STREAMOUT_BUF2,
332	SI_VS_STREAMOUT_BUF3,
333
334	SI_HS_CONST_DEFAULT_TESS_LEVELS,
335	SI_VS_CONST_INSTANCE_DIVISORS,
336	SI_VS_CONST_CLIP_PLANES,
337	SI_PS_CONST_POLY_STIPPLE,
338	SI_PS_CONST_SAMPLE_POSITIONS,
339
340	/* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
341	SI_PS_IMAGE_COLORBUF0,
342	SI_PS_IMAGE_COLORBUF0_HI,
343	SI_PS_IMAGE_COLORBUF0_FMASK,
344	SI_PS_IMAGE_COLORBUF0_FMASK_HI,
345
346	SI_NUM_RW_BUFFERS,
347};
348
349/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
350 * are contiguous:
351 *
352 *  0 - rw buffers
353 *  1 - vertex const and shader buffers
354 *  2 - vertex samplers and images
355 *  3 - fragment const and shader buffer
356 *   ...
357 *  11 - compute const and shader buffers
358 *  12 - compute samplers and images
359 */
360enum {
361	SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
362	SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
363	SI_NUM_SHADER_DESCS,
364};
365
366#define SI_DESCS_RW_BUFFERS            0
367#define SI_DESCS_FIRST_SHADER          1
368#define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
369                                        PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
370#define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
371                                        SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
372
373#define SI_DESCS_SHADER_MASK(name) \
374	u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
375			  PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
376			  SI_NUM_SHADER_DESCS)
377
378/* This represents descriptors in memory, such as buffer resources,
379 * image resources, and sampler states.
380 */
381struct si_descriptors {
382	/* The list of descriptors in malloc'd memory. */
383	uint32_t *list;
384	/* The list in mapped GPU memory. */
385	uint32_t *gpu_list;
386
387	/* The buffer where the descriptors have been uploaded. */
388	struct si_resource *buffer;
389	uint64_t gpu_address;
390
391	/* The maximum number of descriptors. */
392	uint32_t num_elements;
393
394	/* Slots that are used by currently-bound shaders.
395	 * It determines which slots are uploaded.
396	 */
397	uint32_t first_active_slot;
398	uint32_t num_active_slots;
399
400	/* The SH register offset relative to USER_DATA*_0 where the pointer
401	 * to the descriptor array will be stored. */
402	short shader_userdata_offset;
403	/* The size of one descriptor. */
404	ubyte element_dw_size;
405	/* If there is only one slot enabled, bind it directly instead of
406	 * uploading descriptors. -1 if disabled. */
407	signed char slot_index_to_bind_directly;
408};
409
410struct si_buffer_resources {
411	struct pipe_resource		**buffers; /* this has num_buffers elements */
412	unsigned			*offsets; /* this has num_buffers elements */
413
414	enum radeon_bo_priority		priority:6;
415	enum radeon_bo_priority		priority_constbuf:6;
416
417	/* The i-th bit is set if that element is enabled (non-NULL resource). */
418	unsigned			enabled_mask;
419	unsigned			writable_mask;
420};
421
422#define si_pm4_state_changed(sctx, member) \
423	((sctx)->queued.named.member != (sctx)->emitted.named.member)
424
425#define si_pm4_state_enabled_and_changed(sctx, member) \
426	((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
427
428#define si_pm4_bind_state(sctx, member, value) \
429	do { \
430		(sctx)->queued.named.member = (value); \
431		(sctx)->dirty_states |= SI_STATE_BIT(member); \
432	} while(0)
433
434#define si_pm4_delete_state(sctx, member, value) \
435	do { \
436		if ((sctx)->queued.named.member == (value)) { \
437			(sctx)->queued.named.member = NULL; \
438		} \
439		si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
440				  SI_STATE_IDX(member)); \
441	} while(0)
442
443/* si_descriptors.c */
444void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
445				    struct si_texture *tex,
446				    const struct legacy_surf_level *base_level_info,
447				    unsigned base_level, unsigned first_level,
448				    unsigned block_width, bool is_stencil,
449				    uint32_t *state);
450void si_update_ps_colorbuf0_slot(struct si_context *sctx);
451void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
452				 uint slot, struct pipe_constant_buffer *cbuf);
453void si_get_shader_buffers(struct si_context *sctx,
454			   enum pipe_shader_type shader,
455			   uint start_slot, uint count,
456			   struct pipe_shader_buffer *sbuf);
457void si_set_ring_buffer(struct si_context *sctx, uint slot,
458			struct pipe_resource *buffer,
459			unsigned stride, unsigned num_records,
460			bool add_tid, bool swizzle,
461			unsigned element_size, unsigned index_stride, uint64_t offset);
462void si_init_all_descriptors(struct si_context *sctx);
463bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
464bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
465bool si_upload_compute_shader_descriptors(struct si_context *sctx);
466void si_release_all_descriptors(struct si_context *sctx);
467void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
468void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
469void si_all_descriptors_begin_new_cs(struct si_context *sctx);
470void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf,
471			    const uint8_t *ptr, unsigned size, uint32_t *const_offset);
472void si_update_all_texture_descriptors(struct si_context *sctx);
473void si_shader_change_notify(struct si_context *sctx);
474void si_update_needs_color_decompress_masks(struct si_context *sctx);
475void si_emit_graphics_shader_pointers(struct si_context *sctx);
476void si_emit_compute_shader_pointers(struct si_context *sctx);
477void si_set_rw_buffer(struct si_context *sctx,
478		      uint slot, const struct pipe_constant_buffer *input);
479void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
480			     const struct pipe_shader_buffer *sbuffer);
481void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
482			       uint64_t new_active_mask);
483void si_set_active_descriptors_for_shader(struct si_context *sctx,
484					  struct si_shader_selector *sel);
485bool si_bindless_descriptor_can_reclaim_slab(void *priv,
486					     struct pb_slab_entry *entry);
487struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
488						  unsigned entry_size,
489						  unsigned group_index);
490void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
491void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
492/* si_state.c */
493void si_init_state_compute_functions(struct si_context *sctx);
494void si_init_state_functions(struct si_context *sctx);
495void si_init_screen_state_functions(struct si_screen *sscreen);
496void
497si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
498			  enum pipe_format format,
499			  unsigned offset, unsigned size,
500			  uint32_t *state);
501void
502si_make_texture_descriptor(struct si_screen *screen,
503			   struct si_texture *tex,
504			   bool sampler,
505			   enum pipe_texture_target target,
506			   enum pipe_format pipe_format,
507			   const unsigned char state_swizzle[4],
508			   unsigned first_level, unsigned last_level,
509			   unsigned first_layer, unsigned last_layer,
510			   unsigned width, unsigned height, unsigned depth,
511			   uint32_t *state,
512			   uint32_t *fmask_state);
513struct pipe_sampler_view *
514si_create_sampler_view_custom(struct pipe_context *ctx,
515			      struct pipe_resource *texture,
516			      const struct pipe_sampler_view *state,
517			      unsigned width0, unsigned height0,
518			      unsigned force_level);
519void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
520void si_update_ps_iter_samples(struct si_context *sctx);
521void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
522void si_set_occlusion_query_state(struct si_context *sctx,
523				  bool old_perfect_enable);
524
525/* si_state_binning.c */
526void si_emit_dpbb_state(struct si_context *sctx);
527
528/* si_state_shaders.c */
529void *si_get_ir_binary(struct si_shader_selector *sel);
530bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
531				 struct si_shader *shader);
532bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
533				   struct si_shader *shader,
534				   bool insert_into_disk_cache);
535bool si_update_shaders(struct si_context *sctx);
536void si_init_shader_functions(struct si_context *sctx);
537bool si_init_shader_cache(struct si_screen *sscreen);
538void si_destroy_shader_cache(struct si_screen *sscreen);
539void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
540				 struct util_queue_fence *ready_fence,
541				 struct si_compiler_ctx_state *compiler_ctx_state,
542				 void *job, util_queue_execute_func execute);
543void si_get_active_slot_masks(const struct tgsi_shader_info *info,
544			      uint32_t *const_and_shader_buffers,
545			      uint64_t *samplers_and_images);
546
547/* si_state_draw.c */
548void si_emit_cache_flush(struct si_context *sctx);
549void si_trace_emit(struct si_context *sctx);
550void si_init_draw_functions(struct si_context *sctx);
551
552/* si_state_msaa.c */
553void si_init_msaa_functions(struct si_context *sctx);
554void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
555
556/* si_state_streamout.c */
557void si_streamout_buffers_dirty(struct si_context *sctx);
558void si_emit_streamout_end(struct si_context *sctx);
559void si_update_prims_generated_query_state(struct si_context *sctx,
560					   unsigned type, int diff);
561void si_init_streamout_functions(struct si_context *sctx);
562
563
564static inline unsigned si_get_constbuf_slot(unsigned slot)
565{
566	/* Constant buffers are in slots [16..31], ascending */
567	return SI_NUM_SHADER_BUFFERS + slot;
568}
569
570static inline unsigned si_get_shaderbuf_slot(unsigned slot)
571{
572	/* shader buffers are in slots [15..0], descending */
573	return SI_NUM_SHADER_BUFFERS - 1 - slot;
574}
575
576static inline unsigned si_get_sampler_slot(unsigned slot)
577{
578	/* samplers are in slots [8..39], ascending */
579	return SI_NUM_IMAGES / 2 + slot;
580}
581
582static inline unsigned si_get_image_slot(unsigned slot)
583{
584	/* images are in slots [15..0] (sampler slots [7..0]), descending */
585	return SI_NUM_IMAGES - 1 - slot;
586}
587
588#endif
589