1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#include "si_build_pm4.h" 26#include "gfx9d.h" 27 28#include "compiler/nir/nir_serialize.h" 29#include "tgsi/tgsi_parse.h" 30#include "util/hash_table.h" 31#include "util/crc32.h" 32#include "util/u_async_debug.h" 33#include "util/u_memory.h" 34#include "util/u_prim.h" 35 36#include "util/disk_cache.h" 37#include "util/mesa-sha1.h" 38#include "ac_exp_param.h" 39#include "ac_shader_util.h" 40 41/* SHADER_CACHE */ 42 43/** 44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its 45 * size as integer. 46 */ 47void *si_get_ir_binary(struct si_shader_selector *sel) 48{ 49 struct blob blob; 50 unsigned ir_size; 51 void *ir_binary; 52 53 if (sel->tokens) { 54 ir_binary = sel->tokens; 55 ir_size = tgsi_num_tokens(sel->tokens) * 56 sizeof(struct tgsi_token); 57 } else { 58 assert(sel->nir); 59 60 blob_init(&blob); 61 nir_serialize(&blob, sel->nir); 62 ir_binary = blob.data; 63 ir_size = blob.size; 64 } 65 66 unsigned size = 4 + ir_size + sizeof(sel->so); 67 char *result = (char*)MALLOC(size); 68 if (!result) 69 return NULL; 70 71 *((uint32_t*)result) = size; 72 memcpy(result + 4, ir_binary, ir_size); 73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so)); 74 75 if (sel->nir) 76 blob_finish(&blob); 77 78 return result; 79} 80 81/** Copy "data" to "ptr" and return the next dword following copied data. */ 82static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size) 83{ 84 /* data may be NULL if size == 0 */ 85 if (size) 86 memcpy(ptr, data, size); 87 ptr += DIV_ROUND_UP(size, 4); 88 return ptr; 89} 90 91/** Read data from "ptr". Return the next dword following the data. */ 92static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size) 93{ 94 memcpy(data, ptr, size); 95 ptr += DIV_ROUND_UP(size, 4); 96 return ptr; 97} 98 99/** 100 * Write the size as uint followed by the data. Return the next dword 101 * following the copied data. 102 */ 103static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size) 104{ 105 *ptr++ = size; 106 return write_data(ptr, data, size); 107} 108 109/** 110 * Read the size as uint followed by the data. Return both via parameters. 111 * Return the next dword following the data. 112 */ 113static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size) 114{ 115 *size = *ptr++; 116 assert(*data == NULL); 117 if (!*size) 118 return ptr; 119 *data = malloc(*size); 120 return read_data(ptr, *data, *size); 121} 122 123/** 124 * Return the shader binary in a buffer. The first 4 bytes contain its size 125 * as integer. 126 */ 127static void *si_get_shader_binary(struct si_shader *shader) 128{ 129 /* There is always a size of data followed by the data itself. */ 130 unsigned relocs_size = shader->binary.reloc_count * 131 sizeof(shader->binary.relocs[0]); 132 unsigned disasm_size = shader->binary.disasm_string ? 133 strlen(shader->binary.disasm_string) + 1 : 0; 134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ? 135 strlen(shader->binary.llvm_ir_string) + 1 : 0; 136 unsigned size = 137 4 + /* total size */ 138 4 + /* CRC32 of the data below */ 139 align(sizeof(shader->config), 4) + 140 align(sizeof(shader->info), 4) + 141 4 + align(shader->binary.code_size, 4) + 142 4 + align(shader->binary.rodata_size, 4) + 143 4 + align(relocs_size, 4) + 144 4 + align(disasm_size, 4) + 145 4 + align(llvm_ir_size, 4); 146 void *buffer = CALLOC(1, size); 147 uint32_t *ptr = (uint32_t*)buffer; 148 149 if (!buffer) 150 return NULL; 151 152 *ptr++ = size; 153 ptr++; /* CRC32 is calculated at the end. */ 154 155 ptr = write_data(ptr, &shader->config, sizeof(shader->config)); 156 ptr = write_data(ptr, &shader->info, sizeof(shader->info)); 157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size); 158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size); 159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size); 160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size); 161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size); 162 assert((char *)ptr - (char *)buffer == size); 163 164 /* Compute CRC32. */ 165 ptr = (uint32_t*)buffer; 166 ptr++; 167 *ptr = util_hash_crc32(ptr + 1, size - 8); 168 169 return buffer; 170} 171 172static bool si_load_shader_binary(struct si_shader *shader, void *binary) 173{ 174 uint32_t *ptr = (uint32_t*)binary; 175 uint32_t size = *ptr++; 176 uint32_t crc32 = *ptr++; 177 unsigned chunk_size; 178 179 if (util_hash_crc32(ptr, size - 8) != crc32) { 180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n"); 181 return false; 182 } 183 184 ptr = read_data(ptr, &shader->config, sizeof(shader->config)); 185 ptr = read_data(ptr, &shader->info, sizeof(shader->info)); 186 ptr = read_chunk(ptr, (void**)&shader->binary.code, 187 &shader->binary.code_size); 188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata, 189 &shader->binary.rodata_size); 190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size); 191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]); 192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size); 193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size); 194 195 return true; 196} 197 198/** 199 * Insert a shader into the cache. It's assumed the shader is not in the cache. 200 * Use si_shader_cache_load_shader before calling this. 201 * 202 * Returns false on failure, in which case the ir_binary should be freed. 203 */ 204bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary, 205 struct si_shader *shader, 206 bool insert_into_disk_cache) 207{ 208 void *hw_binary; 209 struct hash_entry *entry; 210 uint8_t key[CACHE_KEY_SIZE]; 211 212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary); 213 if (entry) 214 return false; /* already added */ 215 216 hw_binary = si_get_shader_binary(shader); 217 if (!hw_binary) 218 return false; 219 220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary, 221 hw_binary) == NULL) { 222 FREE(hw_binary); 223 return false; 224 } 225 226 if (sscreen->disk_shader_cache && insert_into_disk_cache) { 227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary, 228 *((uint32_t *)ir_binary), key); 229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, 230 *((uint32_t *) hw_binary), NULL); 231 } 232 233 return true; 234} 235 236bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary, 237 struct si_shader *shader) 238{ 239 struct hash_entry *entry = 240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary); 241 if (!entry) { 242 if (sscreen->disk_shader_cache) { 243 unsigned char sha1[CACHE_KEY_SIZE]; 244 size_t tg_size = *((uint32_t *) ir_binary); 245 246 disk_cache_compute_key(sscreen->disk_shader_cache, 247 ir_binary, tg_size, sha1); 248 249 size_t binary_size; 250 uint8_t *buffer = 251 disk_cache_get(sscreen->disk_shader_cache, 252 sha1, &binary_size); 253 if (!buffer) 254 return false; 255 256 if (binary_size < sizeof(uint32_t) || 257 *((uint32_t*)buffer) != binary_size) { 258 /* Something has gone wrong discard the item 259 * from the cache and rebuild/link from 260 * source. 261 */ 262 assert(!"Invalid radeonsi shader disk cache " 263 "item!"); 264 265 disk_cache_remove(sscreen->disk_shader_cache, 266 sha1); 267 free(buffer); 268 269 return false; 270 } 271 272 if (!si_load_shader_binary(shader, buffer)) { 273 free(buffer); 274 return false; 275 } 276 free(buffer); 277 278 if (!si_shader_cache_insert_shader(sscreen, ir_binary, 279 shader, false)) 280 FREE(ir_binary); 281 } else { 282 return false; 283 } 284 } else { 285 if (si_load_shader_binary(shader, entry->data)) 286 FREE(ir_binary); 287 else 288 return false; 289 } 290 p_atomic_inc(&sscreen->num_shader_cache_hits); 291 return true; 292} 293 294static uint32_t si_shader_cache_key_hash(const void *key) 295{ 296 /* The first dword is the key size. */ 297 return util_hash_crc32(key, *(uint32_t*)key); 298} 299 300static bool si_shader_cache_key_equals(const void *a, const void *b) 301{ 302 uint32_t *keya = (uint32_t*)a; 303 uint32_t *keyb = (uint32_t*)b; 304 305 /* The first dword is the key size. */ 306 if (*keya != *keyb) 307 return false; 308 309 return memcmp(keya, keyb, *keya) == 0; 310} 311 312static void si_destroy_shader_cache_entry(struct hash_entry *entry) 313{ 314 FREE((void*)entry->key); 315 FREE(entry->data); 316} 317 318bool si_init_shader_cache(struct si_screen *sscreen) 319{ 320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain); 321 sscreen->shader_cache = 322 _mesa_hash_table_create(NULL, 323 si_shader_cache_key_hash, 324 si_shader_cache_key_equals); 325 326 return sscreen->shader_cache != NULL; 327} 328 329void si_destroy_shader_cache(struct si_screen *sscreen) 330{ 331 if (sscreen->shader_cache) 332 _mesa_hash_table_destroy(sscreen->shader_cache, 333 si_destroy_shader_cache_entry); 334 mtx_destroy(&sscreen->shader_cache_mutex); 335} 336 337/* SHADER STATES */ 338 339static void si_set_tesseval_regs(struct si_screen *sscreen, 340 const struct si_shader_selector *tes, 341 struct si_pm4_state *pm4) 342{ 343 const struct tgsi_shader_info *info = &tes->info; 344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE]; 345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING]; 346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW]; 347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE]; 348 unsigned type, partitioning, topology, distribution_mode; 349 350 switch (tes_prim_mode) { 351 case PIPE_PRIM_LINES: 352 type = V_028B6C_TESS_ISOLINE; 353 break; 354 case PIPE_PRIM_TRIANGLES: 355 type = V_028B6C_TESS_TRIANGLE; 356 break; 357 case PIPE_PRIM_QUADS: 358 type = V_028B6C_TESS_QUAD; 359 break; 360 default: 361 assert(0); 362 return; 363 } 364 365 switch (tes_spacing) { 366 case PIPE_TESS_SPACING_FRACTIONAL_ODD: 367 partitioning = V_028B6C_PART_FRAC_ODD; 368 break; 369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN: 370 partitioning = V_028B6C_PART_FRAC_EVEN; 371 break; 372 case PIPE_TESS_SPACING_EQUAL: 373 partitioning = V_028B6C_PART_INTEGER; 374 break; 375 default: 376 assert(0); 377 return; 378 } 379 380 if (tes_point_mode) 381 topology = V_028B6C_OUTPUT_POINT; 382 else if (tes_prim_mode == PIPE_PRIM_LINES) 383 topology = V_028B6C_OUTPUT_LINE; 384 else if (tes_vertex_order_cw) 385 /* for some reason, this must be the other way around */ 386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW; 387 else 388 topology = V_028B6C_OUTPUT_TRIANGLE_CW; 389 390 if (sscreen->has_distributed_tess) { 391 if (sscreen->info.family == CHIP_FIJI || 392 sscreen->info.family >= CHIP_POLARIS10) 393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; 394 else 395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; 396 } else 397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; 398 399 assert(pm4->shader); 400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | 401 S_028B6C_PARTITIONING(partitioning) | 402 S_028B6C_TOPOLOGY(topology) | 403 S_028B6C_DISTRIBUTION_MODE(distribution_mode); 404} 405 406/* Polaris needs different VTX_REUSE_DEPTH settings depending on 407 * whether the "fractional odd" tessellation spacing is used. 408 * 409 * Possible VGT configurations and which state should set the register: 410 * 411 * Reg set in | VGT shader configuration | Value 412 * ------------------------------------------------------ 413 * VS as VS | VS | 30 414 * VS as ES | ES -> GS -> VS | 30 415 * TES as VS | LS -> HS -> VS | 14 or 30 416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30 417 * 418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader. 419 */ 420static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, 421 struct si_shader_selector *sel, 422 struct si_shader *shader, 423 struct si_pm4_state *pm4) 424{ 425 unsigned type = sel->type; 426 427 if (sscreen->info.family < CHIP_POLARIS10) 428 return; 429 430 /* VS as VS, or VS as ES: */ 431 if ((type == PIPE_SHADER_VERTEX && 432 (!shader || 433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) || 434 /* TES as VS, or TES as ES: */ 435 type == PIPE_SHADER_TESS_EVAL) { 436 unsigned vtx_reuse_depth = 30; 437 438 if (type == PIPE_SHADER_TESS_EVAL && 439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] == 440 PIPE_TESS_SPACING_FRACTIONAL_ODD) 441 vtx_reuse_depth = 14; 442 443 assert(pm4->shader); 444 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth; 445 } 446} 447 448static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader) 449{ 450 if (shader->pm4) 451 si_pm4_clear_state(shader->pm4); 452 else 453 shader->pm4 = CALLOC_STRUCT(si_pm4_state); 454 455 if (shader->pm4) { 456 shader->pm4->shader = shader; 457 return shader->pm4; 458 } else { 459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n"); 460 return NULL; 461 } 462} 463 464static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs) 465{ 466 /* Add the pointer to VBO descriptors. */ 467 return num_always_on_user_sgprs + 1; 468} 469 470static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) 471{ 472 struct si_pm4_state *pm4; 473 unsigned vgpr_comp_cnt; 474 uint64_t va; 475 476 assert(sscreen->info.chip_class <= VI); 477 478 pm4 = si_get_shader_pm4_state(shader); 479 if (!pm4) 480 return; 481 482 va = shader->bo->gpu_address; 483 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 484 485 /* We need at least 2 components for LS. 486 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). 487 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. 488 */ 489 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1; 490 491 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); 492 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40)); 493 494 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | 495 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | 496 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) | 497 S_00B528_DX10_CLAMP(1) | 498 S_00B528_FLOAT_MODE(shader->config.float_mode); 499 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) | 500 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 501} 502 503static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) 504{ 505 struct si_pm4_state *pm4; 506 uint64_t va; 507 unsigned ls_vgpr_comp_cnt = 0; 508 509 pm4 = si_get_shader_pm4_state(shader); 510 if (!pm4) 511 return; 512 513 va = shader->bo->gpu_address; 514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 515 516 if (sscreen->info.chip_class >= GFX9) { 517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); 518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40)); 519 520 /* We need at least 2 components for LS. 521 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). 522 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. 523 */ 524 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1; 525 526 unsigned num_user_sgprs = 527 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR); 528 529 shader->config.rsrc2 = 530 S_00B42C_USER_SGPR(num_user_sgprs) | 531 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) | 532 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 533 } else { 534 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8); 535 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40)); 536 537 shader->config.rsrc2 = 538 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | 539 S_00B42C_OC_LDS_EN(1) | 540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 541 } 542 543 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 544 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) | 545 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) | 546 S_00B428_DX10_CLAMP(1) | 547 S_00B428_FLOAT_MODE(shader->config.float_mode) | 548 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt)); 549 550 if (sscreen->info.chip_class <= VI) { 551 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, 552 shader->config.rsrc2); 553 } 554} 555 556static void si_emit_shader_es(struct si_context *sctx) 557{ 558 struct si_shader *shader = sctx->queued.named.es->shader; 559 unsigned initial_cdw = sctx->gfx_cs->current.cdw; 560 561 if (!shader) 562 return; 563 564 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 565 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 566 shader->selector->esgs_itemsize / 4); 567 568 if (shader->selector->type == PIPE_SHADER_TESS_EVAL) 569 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, 570 SI_TRACKED_VGT_TF_PARAM, 571 shader->vgt_tf_param); 572 573 if (shader->vgt_vertex_reuse_block_cntl) 574 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 575 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 576 shader->vgt_vertex_reuse_block_cntl); 577 578 if (initial_cdw != sctx->gfx_cs->current.cdw) 579 sctx->context_roll = true; 580} 581 582static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) 583{ 584 struct si_pm4_state *pm4; 585 unsigned num_user_sgprs; 586 unsigned vgpr_comp_cnt; 587 uint64_t va; 588 unsigned oc_lds_en; 589 590 assert(sscreen->info.chip_class <= VI); 591 592 pm4 = si_get_shader_pm4_state(shader); 593 if (!pm4) 594 return; 595 596 pm4->atom.emit = si_emit_shader_es; 597 va = shader->bo->gpu_address; 598 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 599 600 if (shader->selector->type == PIPE_SHADER_VERTEX) { 601 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ 602 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0; 603 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR); 604 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) { 605 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2; 606 num_user_sgprs = SI_TES_NUM_USER_SGPR; 607 } else 608 unreachable("invalid shader selector type"); 609 610 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0; 611 612 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); 613 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40)); 614 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES, 615 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) | 616 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) | 617 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | 618 S_00B328_DX10_CLAMP(1) | 619 S_00B328_FLOAT_MODE(shader->config.float_mode)); 620 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES, 621 S_00B32C_USER_SGPR(num_user_sgprs) | 622 S_00B32C_OC_LDS_EN(oc_lds_en) | 623 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 624 625 if (shader->selector->type == PIPE_SHADER_TESS_EVAL) 626 si_set_tesseval_regs(sscreen, shader->selector, pm4); 627 628 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4); 629} 630 631static unsigned si_conv_prim_to_gs_out(unsigned mode) 632{ 633 static const int prim_conv[] = { 634 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, 635 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, 636 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, 637 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, 638 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 639 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 640 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 641 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 642 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 643 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 644 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, 645 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, 646 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 647 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, 648 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST, 649 }; 650 assert(mode < ARRAY_SIZE(prim_conv)); 651 652 return prim_conv[mode]; 653} 654 655struct gfx9_gs_info { 656 unsigned es_verts_per_subgroup; 657 unsigned gs_prims_per_subgroup; 658 unsigned gs_inst_prims_in_subgroup; 659 unsigned max_prims_per_subgroup; 660 unsigned lds_size; 661}; 662 663static void gfx9_get_gs_info(struct si_shader_selector *es, 664 struct si_shader_selector *gs, 665 struct gfx9_gs_info *out) 666{ 667 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1); 668 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]; 669 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY && 670 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY; 671 672 /* All these are in dwords: */ 673 /* We can't allow using the whole LDS, because GS waves compete with 674 * other shader stages for LDS space. */ 675 const unsigned max_lds_size = 8 * 1024; 676 const unsigned esgs_itemsize = es->esgs_itemsize / 4; 677 unsigned esgs_lds_size; 678 679 /* All these are per subgroup: */ 680 const unsigned max_out_prims = 32 * 1024; 681 const unsigned max_es_verts = 255; 682 const unsigned ideal_gs_prims = 64; 683 unsigned max_gs_prims, gs_prims; 684 unsigned min_es_verts, es_verts, worst_case_es_verts; 685 686 if (uses_adjacency || gs_num_invocations > 1) 687 max_gs_prims = 127 / gs_num_invocations; 688 else 689 max_gs_prims = 255; 690 691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations. 692 * Make sure we don't go over the maximum value. 693 */ 694 if (gs->gs_max_out_vertices > 0) { 695 max_gs_prims = MIN2(max_gs_prims, 696 max_out_prims / 697 (gs->gs_max_out_vertices * gs_num_invocations)); 698 } 699 assert(max_gs_prims > 0); 700 701 /* If the primitive has adjacency, halve the number of vertices 702 * that will be reused in multiple primitives. 703 */ 704 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1); 705 706 gs_prims = MIN2(ideal_gs_prims, max_gs_prims); 707 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts); 708 709 /* Compute ESGS LDS size based on the worst case number of ES vertices 710 * needed to create the target number of GS prims per subgroup. 711 */ 712 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 713 714 /* If total LDS usage is too big, refactor partitions based on ratio 715 * of ESGS item sizes. 716 */ 717 if (esgs_lds_size > max_lds_size) { 718 /* Our target GS Prims Per Subgroup was too large. Calculate 719 * the maximum number of GS Prims Per Subgroup that will fit 720 * into LDS, capped by the maximum that the hardware can support. 721 */ 722 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), 723 max_gs_prims); 724 assert(gs_prims > 0); 725 worst_case_es_verts = MIN2(min_es_verts * gs_prims, 726 max_es_verts); 727 728 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 729 assert(esgs_lds_size <= max_lds_size); 730 } 731 732 /* Now calculate remaining ESGS information. */ 733 if (esgs_lds_size) 734 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts); 735 else 736 es_verts = max_es_verts; 737 738 /* Vertices for adjacency primitives are not always reused, so restore 739 * it for ES_VERTS_PER_SUBGRP. 740 */ 741 min_es_verts = gs->gs_input_verts_per_prim; 742 743 /* For normal primitives, the VGT only checks if they are past the ES 744 * verts per subgroup after allocating a full GS primitive and if they 745 * are, kick off a new subgroup. But if those additional ES verts are 746 * unique (e.g. not reused) we need to make sure there is enough LDS 747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP. 748 */ 749 es_verts -= min_es_verts - 1; 750 751 out->es_verts_per_subgroup = es_verts; 752 out->gs_prims_per_subgroup = gs_prims; 753 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations; 754 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * 755 gs->gs_max_out_vertices; 756 out->lds_size = align(esgs_lds_size, 128) / 128; 757 758 assert(out->max_prims_per_subgroup <= max_out_prims); 759} 760 761static void si_emit_shader_gs(struct si_context *sctx) 762{ 763 struct si_shader *shader = sctx->queued.named.gs->shader; 764 unsigned initial_cdw = sctx->gfx_cs->current.cdw; 765 766 if (!shader) 767 return; 768 769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2 770 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */ 771 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, 772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1, 773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, 774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2, 775 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3, 776 shader->ctx_reg.gs.vgt_gs_out_prim_type); 777 778 779 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */ 780 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE, 781 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, 782 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize); 783 784 /* R_028B38_VGT_GS_MAX_VERT_OUT */ 785 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, 786 SI_TRACKED_VGT_GS_MAX_VERT_OUT, 787 shader->ctx_reg.gs.vgt_gs_max_vert_out); 788 789 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1 790 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */ 791 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, 792 SI_TRACKED_VGT_GS_VERT_ITEMSIZE, 793 shader->ctx_reg.gs.vgt_gs_vert_itemsize, 794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1, 795 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, 796 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3); 797 798 /* R_028B90_VGT_GS_INSTANCE_CNT */ 799 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, 800 SI_TRACKED_VGT_GS_INSTANCE_CNT, 801 shader->ctx_reg.gs.vgt_gs_instance_cnt); 802 803 if (sctx->chip_class >= GFX9) { 804 /* R_028A44_VGT_GS_ONCHIP_CNTL */ 805 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, 806 SI_TRACKED_VGT_GS_ONCHIP_CNTL, 807 shader->ctx_reg.gs.vgt_gs_onchip_cntl); 808 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */ 809 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 810 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 811 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup); 812 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */ 813 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 814 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 815 shader->ctx_reg.gs.vgt_esgs_ring_itemsize); 816 817 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL) 818 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, 819 SI_TRACKED_VGT_TF_PARAM, 820 shader->vgt_tf_param); 821 if (shader->vgt_vertex_reuse_block_cntl) 822 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 823 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 824 shader->vgt_vertex_reuse_block_cntl); 825 } 826 827 if (initial_cdw != sctx->gfx_cs->current.cdw) 828 sctx->context_roll = true; 829} 830 831static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) 832{ 833 struct si_shader_selector *sel = shader->selector; 834 const ubyte *num_components = sel->info.num_stream_output_components; 835 unsigned gs_num_invocations = sel->gs_num_invocations; 836 struct si_pm4_state *pm4; 837 uint64_t va; 838 unsigned max_stream = sel->max_gs_stream; 839 unsigned offset; 840 841 pm4 = si_get_shader_pm4_state(shader); 842 if (!pm4) 843 return; 844 845 pm4->atom.emit = si_emit_shader_gs; 846 847 offset = num_components[0] * sel->gs_max_out_vertices; 848 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset; 849 850 if (max_stream >= 1) 851 offset += num_components[1] * sel->gs_max_out_vertices; 852 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset; 853 854 if (max_stream >= 2) 855 offset += num_components[2] * sel->gs_max_out_vertices; 856 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset; 857 858 shader->ctx_reg.gs.vgt_gs_out_prim_type = 859 si_conv_prim_to_gs_out(sel->gs_output_prim); 860 861 if (max_stream >= 3) 862 offset += num_components[3] * sel->gs_max_out_vertices; 863 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset; 864 865 /* The GSVS_RING_ITEMSIZE register takes 15 bits */ 866 assert(offset < (1 << 15)); 867 868 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices; 869 870 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0]; 871 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0; 872 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0; 873 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0; 874 875 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) | 876 S_028B90_ENABLE(gs_num_invocations > 0); 877 878 va = shader->bo->gpu_address; 879 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 880 881 if (sscreen->info.chip_class >= GFX9) { 882 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]; 883 unsigned es_type = shader->key.part.gs.es->type; 884 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt; 885 struct gfx9_gs_info gs_info; 886 887 if (es_type == PIPE_SHADER_VERTEX) 888 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ 889 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0; 890 else if (es_type == PIPE_SHADER_TESS_EVAL) 891 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2; 892 else 893 unreachable("invalid shader selector type"); 894 895 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and 896 * VGPR[0:4] are always loaded. 897 */ 898 if (sel->info.uses_invocationid) 899 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ 900 else if (sel->info.uses_primid) 901 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ 902 else if (input_prim >= PIPE_PRIM_TRIANGLES) 903 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ 904 else 905 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ 906 907 unsigned num_user_sgprs; 908 if (es_type == PIPE_SHADER_VERTEX) 909 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR); 910 else 911 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR; 912 913 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info); 914 915 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); 916 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40)); 917 918 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 919 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | 920 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | 921 S_00B228_DX10_CLAMP(1) | 922 S_00B228_FLOAT_MODE(shader->config.float_mode) | 923 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt)); 924 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, 925 S_00B22C_USER_SGPR(num_user_sgprs) | 926 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) | 927 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | 928 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) | 929 S_00B22C_LDS_SIZE(gs_info.lds_size) | 930 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 931 932 shader->ctx_reg.gs.vgt_gs_onchip_cntl = 933 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) | 934 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) | 935 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup); 936 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup = 937 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup); 938 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = 939 shader->key.part.gs.es->esgs_itemsize / 4; 940 941 if (es_type == PIPE_SHADER_TESS_EVAL) 942 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4); 943 944 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, 945 NULL, pm4); 946 } else { 947 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); 948 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40)); 949 950 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 951 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | 952 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | 953 S_00B228_DX10_CLAMP(1) | 954 S_00B228_FLOAT_MODE(shader->config.float_mode)); 955 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, 956 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) | 957 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 958 } 959} 960 961static void si_emit_shader_vs(struct si_context *sctx) 962{ 963 struct si_shader *shader = sctx->queued.named.vs->shader; 964 unsigned initial_cdw = sctx->gfx_cs->current.cdw; 965 966 if (!shader) 967 return; 968 969 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, 970 SI_TRACKED_VGT_GS_MODE, 971 shader->ctx_reg.vs.vgt_gs_mode); 972 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, 973 SI_TRACKED_VGT_PRIMITIVEID_EN, 974 shader->ctx_reg.vs.vgt_primitiveid_en); 975 976 if (sctx->chip_class <= VI) { 977 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, 978 SI_TRACKED_VGT_REUSE_OFF, 979 shader->ctx_reg.vs.vgt_reuse_off); 980 } 981 982 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, 983 SI_TRACKED_SPI_VS_OUT_CONFIG, 984 shader->ctx_reg.vs.spi_vs_out_config); 985 986 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT, 987 SI_TRACKED_SPI_SHADER_POS_FORMAT, 988 shader->ctx_reg.vs.spi_shader_pos_format); 989 990 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, 991 SI_TRACKED_PA_CL_VTE_CNTL, 992 shader->ctx_reg.vs.pa_cl_vte_cntl); 993 994 if (shader->selector->type == PIPE_SHADER_TESS_EVAL) 995 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, 996 SI_TRACKED_VGT_TF_PARAM, 997 shader->vgt_tf_param); 998 999 if (shader->vgt_vertex_reuse_block_cntl) 1000 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 1001 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 1002 shader->vgt_vertex_reuse_block_cntl); 1003 1004 if (initial_cdw != sctx->gfx_cs->current.cdw) 1005 sctx->context_roll = true; 1006} 1007 1008/** 1009 * Compute the state for \p shader, which will run as a vertex shader on the 1010 * hardware. 1011 * 1012 * If \p gs is non-NULL, it points to the geometry shader for which this shader 1013 * is the copy shader. 1014 */ 1015static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, 1016 struct si_shader_selector *gs) 1017{ 1018 const struct tgsi_shader_info *info = &shader->selector->info; 1019 struct si_pm4_state *pm4; 1020 unsigned num_user_sgprs, vgpr_comp_cnt; 1021 uint64_t va; 1022 unsigned nparams, oc_lds_en; 1023 unsigned window_space = 1024 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION]; 1025 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid; 1026 1027 pm4 = si_get_shader_pm4_state(shader); 1028 if (!pm4) 1029 return; 1030 1031 pm4->atom.emit = si_emit_shader_vs; 1032 1033 /* We always write VGT_GS_MODE in the VS state, because every switch 1034 * between different shader pipelines involving a different GS or no 1035 * GS at all involves a switch of the VS (different GS use different 1036 * copy shaders). On the other hand, when the API switches from a GS to 1037 * no GS and then back to the same GS used originally, the GS state is 1038 * not sent again. 1039 */ 1040 if (!gs) { 1041 unsigned mode = V_028A40_GS_OFF; 1042 1043 /* PrimID needs GS scenario A. */ 1044 if (enable_prim_id) 1045 mode = V_028A40_GS_SCENARIO_A; 1046 1047 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode); 1048 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id; 1049 } else { 1050 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices, 1051 sscreen->info.chip_class); 1052 shader->ctx_reg.vs.vgt_primitiveid_en = 0; 1053 } 1054 1055 if (sscreen->info.chip_class <= VI) { 1056 /* Reuse needs to be set off if we write oViewport. */ 1057 shader->ctx_reg.vs.vgt_reuse_off = 1058 S_028AB4_REUSE_OFF(info->writes_viewport_index); 1059 } 1060 1061 va = shader->bo->gpu_address; 1062 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 1063 1064 if (gs) { 1065 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */ 1066 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR; 1067 } else if (shader->selector->type == PIPE_SHADER_VERTEX) { 1068 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID) 1069 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead. 1070 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. 1071 */ 1072 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0); 1073 1074 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) { 1075 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + 1076 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]; 1077 } else { 1078 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR); 1079 } 1080 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) { 1081 vgpr_comp_cnt = enable_prim_id ? 3 : 2; 1082 num_user_sgprs = SI_TES_NUM_USER_SGPR; 1083 } else 1084 unreachable("invalid shader selector type"); 1085 1086 /* VS is required to export at least one param. */ 1087 nparams = MAX2(shader->info.nr_param_exports, 1); 1088 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); 1089 1090 shader->ctx_reg.vs.spi_shader_pos_format = 1091 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 1092 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? 1093 V_02870C_SPI_SHADER_4COMP : 1094 V_02870C_SPI_SHADER_NONE) | 1095 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? 1096 V_02870C_SPI_SHADER_4COMP : 1097 V_02870C_SPI_SHADER_NONE) | 1098 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? 1099 V_02870C_SPI_SHADER_4COMP : 1100 V_02870C_SPI_SHADER_NONE); 1101 1102 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0; 1103 1104 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); 1105 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40)); 1106 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, 1107 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) | 1108 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) | 1109 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | 1110 S_00B128_DX10_CLAMP(1) | 1111 S_00B128_FLOAT_MODE(shader->config.float_mode)); 1112 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 1113 S_00B12C_USER_SGPR(num_user_sgprs) | 1114 S_00B12C_OC_LDS_EN(oc_lds_en) | 1115 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) | 1116 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) | 1117 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) | 1118 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) | 1119 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) | 1120 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 1121 1122 if (window_space) 1123 shader->ctx_reg.vs.pa_cl_vte_cntl = 1124 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1); 1125 else 1126 shader->ctx_reg.vs.pa_cl_vte_cntl = 1127 S_028818_VTX_W0_FMT(1) | 1128 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 1129 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 1130 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1); 1131 1132 if (shader->selector->type == PIPE_SHADER_TESS_EVAL) 1133 si_set_tesseval_regs(sscreen, shader->selector, pm4); 1134 1135 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4); 1136} 1137 1138static unsigned si_get_ps_num_interp(struct si_shader *ps) 1139{ 1140 struct tgsi_shader_info *info = &ps->selector->info; 1141 unsigned num_colors = !!(info->colors_read & 0x0f) + 1142 !!(info->colors_read & 0xf0); 1143 unsigned num_interp = ps->selector->info.num_inputs + 1144 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0); 1145 1146 assert(num_interp <= 32); 1147 return MIN2(num_interp, 32); 1148} 1149 1150static unsigned si_get_spi_shader_col_format(struct si_shader *shader) 1151{ 1152 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format; 1153 unsigned i, num_targets = (util_last_bit(value) + 3) / 4; 1154 1155 /* If the i-th target format is set, all previous target formats must 1156 * be non-zero to avoid hangs. 1157 */ 1158 for (i = 0; i < num_targets; i++) 1159 if (!(value & (0xf << (i * 4)))) 1160 value |= V_028714_SPI_SHADER_32_R << (i * 4); 1161 1162 return value; 1163} 1164 1165static void si_emit_shader_ps(struct si_context *sctx) 1166{ 1167 struct si_shader *shader = sctx->queued.named.ps->shader; 1168 unsigned initial_cdw = sctx->gfx_cs->current.cdw; 1169 1170 if (!shader) 1171 return; 1172 1173 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/ 1174 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, 1175 SI_TRACKED_SPI_PS_INPUT_ENA, 1176 shader->ctx_reg.ps.spi_ps_input_ena, 1177 shader->ctx_reg.ps.spi_ps_input_addr); 1178 1179 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, 1180 SI_TRACKED_SPI_BARYC_CNTL, 1181 shader->ctx_reg.ps.spi_baryc_cntl); 1182 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, 1183 SI_TRACKED_SPI_PS_IN_CONTROL, 1184 shader->ctx_reg.ps.spi_ps_in_control); 1185 1186 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */ 1187 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, 1188 SI_TRACKED_SPI_SHADER_Z_FORMAT, 1189 shader->ctx_reg.ps.spi_shader_z_format, 1190 shader->ctx_reg.ps.spi_shader_col_format); 1191 1192 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, 1193 SI_TRACKED_CB_SHADER_MASK, 1194 shader->ctx_reg.ps.cb_shader_mask); 1195 1196 if (initial_cdw != sctx->gfx_cs->current.cdw) 1197 sctx->context_roll = true; 1198} 1199 1200static void si_shader_ps(struct si_shader *shader) 1201{ 1202 struct tgsi_shader_info *info = &shader->selector->info; 1203 struct si_pm4_state *pm4; 1204 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask; 1205 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); 1206 uint64_t va; 1207 unsigned input_ena = shader->config.spi_ps_input_ena; 1208 1209 /* we need to enable at least one of them, otherwise we hang the GPU */ 1210 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || 1211 G_0286CC_PERSP_CENTER_ENA(input_ena) || 1212 G_0286CC_PERSP_CENTROID_ENA(input_ena) || 1213 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) || 1214 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || 1215 G_0286CC_LINEAR_CENTER_ENA(input_ena) || 1216 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || 1217 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena)); 1218 /* POS_W_FLOAT_ENA requires one of the perspective weights. */ 1219 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || 1220 G_0286CC_PERSP_SAMPLE_ENA(input_ena) || 1221 G_0286CC_PERSP_CENTER_ENA(input_ena) || 1222 G_0286CC_PERSP_CENTROID_ENA(input_ena) || 1223 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena)); 1224 1225 /* Validate interpolation optimization flags (read as implications). */ 1226 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp || 1227 (G_0286CC_PERSP_CENTER_ENA(input_ena) && 1228 G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1229 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear || 1230 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && 1231 G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1232 assert(!shader->key.part.ps.prolog.force_persp_center_interp || 1233 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && 1234 !G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1235 assert(!shader->key.part.ps.prolog.force_linear_center_interp || 1236 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && 1237 !G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1238 assert(!shader->key.part.ps.prolog.force_persp_sample_interp || 1239 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && 1240 !G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1241 assert(!shader->key.part.ps.prolog.force_linear_sample_interp || 1242 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && 1243 !G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1244 1245 /* Validate cases when the optimizations are off (read as implications). */ 1246 assert(shader->key.part.ps.prolog.bc_optimize_for_persp || 1247 !G_0286CC_PERSP_CENTER_ENA(input_ena) || 1248 !G_0286CC_PERSP_CENTROID_ENA(input_ena)); 1249 assert(shader->key.part.ps.prolog.bc_optimize_for_linear || 1250 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || 1251 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)); 1252 1253 pm4 = si_get_shader_pm4_state(shader); 1254 if (!pm4) 1255 return; 1256 1257 pm4->atom.emit = si_emit_shader_ps; 1258 1259 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION 1260 * Possible vaules: 1261 * 0 -> Position = pixel center 1262 * 1 -> Position = pixel centroid 1263 * 2 -> Position = at sample position 1264 * 1265 * From GLSL 4.5 specification, section 7.1: 1266 * "The variable gl_FragCoord is available as an input variable from 1267 * within fragment shaders and it holds the window relative coordinates 1268 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this 1269 * value can be for any location within the pixel, or one of the 1270 * fragment samples. The use of centroid does not further restrict 1271 * this value to be inside the current primitive." 1272 * 1273 * Meaning that centroid has no effect and we can return anything within 1274 * the pixel. Thus, return the value at sample position, because that's 1275 * the most accurate one shaders can get. 1276 */ 1277 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); 1278 1279 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] == 1280 TGSI_FS_COORD_PIXEL_CENTER_INTEGER) 1281 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1); 1282 1283 spi_shader_col_format = si_get_spi_shader_col_format(shader); 1284 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format); 1285 1286 /* Ensure that some export memory is always allocated, for two reasons: 1287 * 1288 * 1) Correctness: The hardware ignores the EXEC mask if no export 1289 * memory is allocated, so KILL and alpha test do not work correctly 1290 * without this. 1291 * 2) Performance: Every shader needs at least a NULL export, even when 1292 * it writes no color/depth output. The NULL export instruction 1293 * stalls without this setting. 1294 * 1295 * Don't add this to CB_SHADER_MASK. 1296 */ 1297 if (!spi_shader_col_format && 1298 !info->writes_z && !info->writes_stencil && !info->writes_samplemask) 1299 spi_shader_col_format = V_028714_SPI_SHADER_32_R; 1300 1301 shader->ctx_reg.ps.spi_ps_input_ena = input_ena; 1302 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr; 1303 1304 /* Set interpolation controls. */ 1305 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)); 1306 1307 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl; 1308 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control; 1309 shader->ctx_reg.ps.spi_shader_z_format = 1310 ac_get_spi_shader_z_format(info->writes_z, 1311 info->writes_stencil, 1312 info->writes_samplemask); 1313 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format; 1314 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask; 1315 1316 va = shader->bo->gpu_address; 1317 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); 1318 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); 1319 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40)); 1320 1321 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, 1322 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) | 1323 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) | 1324 S_00B028_DX10_CLAMP(1) | 1325 S_00B028_FLOAT_MODE(shader->config.float_mode)); 1326 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 1327 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) | 1328 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) | 1329 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 1330} 1331 1332static void si_shader_init_pm4_state(struct si_screen *sscreen, 1333 struct si_shader *shader) 1334{ 1335 switch (shader->selector->type) { 1336 case PIPE_SHADER_VERTEX: 1337 if (shader->key.as_ls) 1338 si_shader_ls(sscreen, shader); 1339 else if (shader->key.as_es) 1340 si_shader_es(sscreen, shader); 1341 else 1342 si_shader_vs(sscreen, shader, NULL); 1343 break; 1344 case PIPE_SHADER_TESS_CTRL: 1345 si_shader_hs(sscreen, shader); 1346 break; 1347 case PIPE_SHADER_TESS_EVAL: 1348 if (shader->key.as_es) 1349 si_shader_es(sscreen, shader); 1350 else 1351 si_shader_vs(sscreen, shader, NULL); 1352 break; 1353 case PIPE_SHADER_GEOMETRY: 1354 si_shader_gs(sscreen, shader); 1355 break; 1356 case PIPE_SHADER_FRAGMENT: 1357 si_shader_ps(shader); 1358 break; 1359 default: 1360 assert(0); 1361 } 1362} 1363 1364static unsigned si_get_alpha_test_func(struct si_context *sctx) 1365{ 1366 /* Alpha-test should be disabled if colorbuffer 0 is integer. */ 1367 if (sctx->queued.named.dsa) 1368 return sctx->queued.named.dsa->alpha_func; 1369 1370 return PIPE_FUNC_ALWAYS; 1371} 1372 1373static void si_shader_selector_key_vs(struct si_context *sctx, 1374 struct si_shader_selector *vs, 1375 struct si_shader_key *key, 1376 struct si_vs_prolog_bits *prolog_key) 1377{ 1378 if (!sctx->vertex_elements || 1379 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) 1380 return; 1381 1382 prolog_key->instance_divisor_is_one = 1383 sctx->vertex_elements->instance_divisor_is_one; 1384 prolog_key->instance_divisor_is_fetched = 1385 sctx->vertex_elements->instance_divisor_is_fetched; 1386 1387 /* Prefer a monolithic shader to allow scheduling divisions around 1388 * VBO loads. */ 1389 if (prolog_key->instance_divisor_is_fetched) 1390 key->opt.prefer_mono = 1; 1391 1392 unsigned count = MIN2(vs->info.num_inputs, 1393 sctx->vertex_elements->count); 1394 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count); 1395} 1396 1397static void si_shader_selector_key_hw_vs(struct si_context *sctx, 1398 struct si_shader_selector *vs, 1399 struct si_shader_key *key) 1400{ 1401 struct si_shader_selector *ps = sctx->ps_shader.cso; 1402 1403 key->opt.clip_disable = 1404 sctx->queued.named.rasterizer->clip_plane_enable == 0 && 1405 (vs->info.clipdist_writemask || 1406 vs->info.writes_clipvertex) && 1407 !vs->info.culldist_writemask; 1408 1409 /* Find out if PS is disabled. */ 1410 bool ps_disabled = true; 1411 if (ps) { 1412 const struct si_state_blend *blend = sctx->queued.named.blend; 1413 bool alpha_to_coverage = blend && blend->alpha_to_coverage; 1414 bool ps_modifies_zs = ps->info.uses_kill || 1415 ps->info.writes_z || 1416 ps->info.writes_stencil || 1417 ps->info.writes_samplemask || 1418 alpha_to_coverage || 1419 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS; 1420 unsigned ps_colormask = si_get_total_colormask(sctx); 1421 1422 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard || 1423 (!ps_colormask && 1424 !ps_modifies_zs && 1425 !ps->info.writes_memory); 1426 } 1427 1428 /* Find out which VS outputs aren't used by the PS. */ 1429 uint64_t outputs_written = vs->outputs_written_before_ps; 1430 uint64_t inputs_read = 0; 1431 1432 /* Ignore outputs that are not passed from VS to PS. */ 1433 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) | 1434 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) | 1435 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true))); 1436 1437 if (!ps_disabled) { 1438 inputs_read = ps->inputs_read; 1439 } 1440 1441 uint64_t linked = outputs_written & inputs_read; 1442 1443 key->opt.kill_outputs = ~linked & outputs_written; 1444} 1445 1446/* Compute the key for the hw shader variant */ 1447static inline void si_shader_selector_key(struct pipe_context *ctx, 1448 struct si_shader_selector *sel, 1449 struct si_shader_key *key) 1450{ 1451 struct si_context *sctx = (struct si_context *)ctx; 1452 1453 memset(key, 0, sizeof(*key)); 1454 1455 switch (sel->type) { 1456 case PIPE_SHADER_VERTEX: 1457 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog); 1458 1459 if (sctx->tes_shader.cso) 1460 key->as_ls = 1; 1461 else if (sctx->gs_shader.cso) 1462 key->as_es = 1; 1463 else { 1464 si_shader_selector_key_hw_vs(sctx, sel, key); 1465 1466 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid) 1467 key->mono.u.vs_export_prim_id = 1; 1468 } 1469 break; 1470 case PIPE_SHADER_TESS_CTRL: 1471 if (sctx->chip_class >= GFX9) { 1472 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, 1473 key, &key->part.tcs.ls_prolog); 1474 key->part.tcs.ls = sctx->vs_shader.cso; 1475 1476 /* When the LS VGPR fix is needed, monolithic shaders 1477 * can: 1478 * - avoid initializing EXEC in both the LS prolog 1479 * and the LS main part when !vs_needs_prolog 1480 * - remove the fixup for unused input VGPRs 1481 */ 1482 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix; 1483 1484 /* The LS output / HS input layout can be communicated 1485 * directly instead of via user SGPRs for merged LS-HS. 1486 * The LS VGPR fix prefers this too. 1487 */ 1488 key->opt.prefer_mono = 1; 1489 } 1490 1491 key->part.tcs.epilog.prim_mode = 1492 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]; 1493 key->part.tcs.epilog.invoc0_tess_factors_are_def = 1494 sel->tcs_info.tessfactors_are_def_in_all_invocs; 1495 key->part.tcs.epilog.tes_reads_tess_factors = 1496 sctx->tes_shader.cso->info.reads_tess_factors; 1497 1498 if (sel == sctx->fixed_func_tcs_shader.cso) 1499 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written; 1500 break; 1501 case PIPE_SHADER_TESS_EVAL: 1502 if (sctx->gs_shader.cso) 1503 key->as_es = 1; 1504 else { 1505 si_shader_selector_key_hw_vs(sctx, sel, key); 1506 1507 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid) 1508 key->mono.u.vs_export_prim_id = 1; 1509 } 1510 break; 1511 case PIPE_SHADER_GEOMETRY: 1512 if (sctx->chip_class >= GFX9) { 1513 if (sctx->tes_shader.cso) { 1514 key->part.gs.es = sctx->tes_shader.cso; 1515 } else { 1516 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, 1517 key, &key->part.gs.vs_prolog); 1518 key->part.gs.es = sctx->vs_shader.cso; 1519 key->part.gs.prolog.gfx9_prev_is_vs = 1; 1520 } 1521 1522 /* Merged ES-GS can have unbalanced wave usage. 1523 * 1524 * ES threads are per-vertex, while GS threads are 1525 * per-primitive. So without any amplification, there 1526 * are fewer GS threads than ES threads, which can result 1527 * in empty (no-op) GS waves. With too much amplification, 1528 * there are more GS threads than ES threads, which 1529 * can result in empty (no-op) ES waves. 1530 * 1531 * Non-monolithic shaders are implemented by setting EXEC 1532 * at the beginning of shader parts, and don't jump to 1533 * the end if EXEC is 0. 1534 * 1535 * Monolithic shaders use conditional blocks, so they can 1536 * jump and skip empty waves of ES or GS. So set this to 1537 * always use optimized variants, which are monolithic. 1538 */ 1539 key->opt.prefer_mono = 1; 1540 } 1541 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix; 1542 break; 1543 case PIPE_SHADER_FRAGMENT: { 1544 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 1545 struct si_state_blend *blend = sctx->queued.named.blend; 1546 1547 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] && 1548 sel->info.colors_written == 0x1) 1549 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1; 1550 1551 if (blend) { 1552 /* Select the shader color format based on whether 1553 * blending or alpha are needed. 1554 */ 1555 key->part.ps.epilog.spi_shader_col_format = 1556 (blend->blend_enable_4bit & blend->need_src_alpha_4bit & 1557 sctx->framebuffer.spi_shader_col_format_blend_alpha) | 1558 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit & 1559 sctx->framebuffer.spi_shader_col_format_blend) | 1560 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit & 1561 sctx->framebuffer.spi_shader_col_format_alpha) | 1562 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit & 1563 sctx->framebuffer.spi_shader_col_format); 1564 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit; 1565 1566 /* The output for dual source blending should have 1567 * the same format as the first output. 1568 */ 1569 if (blend->dual_src_blend) 1570 key->part.ps.epilog.spi_shader_col_format |= 1571 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4; 1572 } else 1573 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format; 1574 1575 /* If alpha-to-coverage is enabled, we have to export alpha 1576 * even if there is no color buffer. 1577 */ 1578 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && 1579 blend && blend->alpha_to_coverage) 1580 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR; 1581 1582 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs 1583 * to the range supported by the type if a channel has less 1584 * than 16 bits and the export format is 16_ABGR. 1585 */ 1586 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) { 1587 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8; 1588 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10; 1589 } 1590 1591 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */ 1592 if (!key->part.ps.epilog.last_cbuf) { 1593 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit; 1594 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written; 1595 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written; 1596 } 1597 1598 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim); 1599 bool is_line = util_prim_is_lines(sctx->current_rast_prim); 1600 1601 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read; 1602 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read; 1603 1604 if (sctx->queued.named.blend) { 1605 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one && 1606 rs->multisample_enable; 1607 } 1608 1609 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly; 1610 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) || 1611 (is_line && rs->line_smooth)) && 1612 sctx->framebuffer.nr_samples <= 1; 1613 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color; 1614 1615 if (sctx->ps_iter_samples > 1 && 1616 sel->info.reads_samplemask) { 1617 key->part.ps.prolog.samplemask_log_ps_iter = 1618 util_logbase2(sctx->ps_iter_samples); 1619 } 1620 1621 if (rs->force_persample_interp && 1622 rs->multisample_enable && 1623 sctx->framebuffer.nr_samples > 1 && 1624 sctx->ps_iter_samples > 1) { 1625 key->part.ps.prolog.force_persp_sample_interp = 1626 sel->info.uses_persp_center || 1627 sel->info.uses_persp_centroid; 1628 1629 key->part.ps.prolog.force_linear_sample_interp = 1630 sel->info.uses_linear_center || 1631 sel->info.uses_linear_centroid; 1632 } else if (rs->multisample_enable && 1633 sctx->framebuffer.nr_samples > 1) { 1634 key->part.ps.prolog.bc_optimize_for_persp = 1635 sel->info.uses_persp_center && 1636 sel->info.uses_persp_centroid; 1637 key->part.ps.prolog.bc_optimize_for_linear = 1638 sel->info.uses_linear_center && 1639 sel->info.uses_linear_centroid; 1640 } else { 1641 /* Make sure SPI doesn't compute more than 1 pair 1642 * of (i,j), which is the optimization here. */ 1643 key->part.ps.prolog.force_persp_center_interp = 1644 sel->info.uses_persp_center + 1645 sel->info.uses_persp_centroid + 1646 sel->info.uses_persp_sample > 1; 1647 1648 key->part.ps.prolog.force_linear_center_interp = 1649 sel->info.uses_linear_center + 1650 sel->info.uses_linear_centroid + 1651 sel->info.uses_linear_sample > 1; 1652 1653 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]) 1654 key->mono.u.ps.interpolate_at_sample_force_center = 1; 1655 } 1656 1657 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx); 1658 1659 /* ps_uses_fbfetch is true only if the color buffer is bound. */ 1660 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) { 1661 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0]; 1662 struct pipe_resource *tex = cb0->texture; 1663 1664 /* 1D textures are allocated and used as 2D on GFX9. */ 1665 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1; 1666 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 && 1667 (tex->target == PIPE_TEXTURE_1D || 1668 tex->target == PIPE_TEXTURE_1D_ARRAY); 1669 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY || 1670 tex->target == PIPE_TEXTURE_2D_ARRAY || 1671 tex->target == PIPE_TEXTURE_CUBE || 1672 tex->target == PIPE_TEXTURE_CUBE_ARRAY || 1673 tex->target == PIPE_TEXTURE_3D; 1674 } 1675 break; 1676 } 1677 default: 1678 assert(0); 1679 } 1680 1681 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT))) 1682 memset(&key->opt, 0, sizeof(key->opt)); 1683} 1684 1685static void si_build_shader_variant(struct si_shader *shader, 1686 int thread_index, 1687 bool low_priority) 1688{ 1689 struct si_shader_selector *sel = shader->selector; 1690 struct si_screen *sscreen = sel->screen; 1691 struct ac_llvm_compiler *compiler; 1692 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug; 1693 int r; 1694 1695 if (thread_index >= 0) { 1696 if (low_priority) { 1697 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp)); 1698 compiler = &sscreen->compiler_lowp[thread_index]; 1699 } else { 1700 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); 1701 compiler = &sscreen->compiler[thread_index]; 1702 } 1703 if (!debug->async) 1704 debug = NULL; 1705 } else { 1706 assert(!low_priority); 1707 compiler = shader->compiler_ctx_state.compiler; 1708 } 1709 1710 r = si_shader_create(sscreen, compiler, shader, debug); 1711 if (unlikely(r)) { 1712 PRINT_ERR("Failed to build shader variant (type=%u) %d\n", 1713 sel->type, r); 1714 shader->compilation_failed = true; 1715 return; 1716 } 1717 1718 if (shader->compiler_ctx_state.is_debug_context) { 1719 FILE *f = open_memstream(&shader->shader_log, 1720 &shader->shader_log_size); 1721 if (f) { 1722 si_shader_dump(sscreen, shader, NULL, sel->type, f, false); 1723 fclose(f); 1724 } 1725 } 1726 1727 si_shader_init_pm4_state(sscreen, shader); 1728} 1729 1730static void si_build_shader_variant_low_priority(void *job, int thread_index) 1731{ 1732 struct si_shader *shader = (struct si_shader *)job; 1733 1734 assert(thread_index >= 0); 1735 1736 si_build_shader_variant(shader, thread_index, true); 1737} 1738 1739static const struct si_shader_key zeroed; 1740 1741static bool si_check_missing_main_part(struct si_screen *sscreen, 1742 struct si_shader_selector *sel, 1743 struct si_compiler_ctx_state *compiler_state, 1744 struct si_shader_key *key) 1745{ 1746 struct si_shader **mainp = si_get_main_shader_part(sel, key); 1747 1748 if (!*mainp) { 1749 struct si_shader *main_part = CALLOC_STRUCT(si_shader); 1750 1751 if (!main_part) 1752 return false; 1753 1754 /* We can leave the fence as permanently signaled because the 1755 * main part becomes visible globally only after it has been 1756 * compiled. */ 1757 util_queue_fence_init(&main_part->ready); 1758 1759 main_part->selector = sel; 1760 main_part->key.as_es = key->as_es; 1761 main_part->key.as_ls = key->as_ls; 1762 main_part->is_monolithic = false; 1763 1764 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler, 1765 main_part, &compiler_state->debug) != 0) { 1766 FREE(main_part); 1767 return false; 1768 } 1769 *mainp = main_part; 1770 } 1771 return true; 1772} 1773 1774/* Select the hw shader variant depending on the current state. */ 1775static int si_shader_select_with_key(struct si_screen *sscreen, 1776 struct si_shader_ctx_state *state, 1777 struct si_compiler_ctx_state *compiler_state, 1778 struct si_shader_key *key, 1779 int thread_index) 1780{ 1781 struct si_shader_selector *sel = state->cso; 1782 struct si_shader_selector *previous_stage_sel = NULL; 1783 struct si_shader *current = state->current; 1784 struct si_shader *iter, *shader = NULL; 1785 1786again: 1787 /* Check if we don't need to change anything. 1788 * This path is also used for most shaders that don't need multiple 1789 * variants, it will cost just a computation of the key and this 1790 * test. */ 1791 if (likely(current && 1792 memcmp(¤t->key, key, sizeof(*key)) == 0)) { 1793 if (unlikely(!util_queue_fence_is_signalled(¤t->ready))) { 1794 if (current->is_optimized) { 1795 memset(&key->opt, 0, sizeof(key->opt)); 1796 goto current_not_ready; 1797 } 1798 1799 util_queue_fence_wait(¤t->ready); 1800 } 1801 1802 return current->compilation_failed ? -1 : 0; 1803 } 1804current_not_ready: 1805 1806 /* This must be done before the mutex is locked, because async GS 1807 * compilation calls this function too, and therefore must enter 1808 * the mutex first. 1809 * 1810 * Only wait if we are in a draw call. Don't wait if we are 1811 * in a compiler thread. 1812 */ 1813 if (thread_index < 0) 1814 util_queue_fence_wait(&sel->ready); 1815 1816 mtx_lock(&sel->mutex); 1817 1818 /* Find the shader variant. */ 1819 for (iter = sel->first_variant; iter; iter = iter->next_variant) { 1820 /* Don't check the "current" shader. We checked it above. */ 1821 if (current != iter && 1822 memcmp(&iter->key, key, sizeof(*key)) == 0) { 1823 mtx_unlock(&sel->mutex); 1824 1825 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) { 1826 /* If it's an optimized shader and its compilation has 1827 * been started but isn't done, use the unoptimized 1828 * shader so as not to cause a stall due to compilation. 1829 */ 1830 if (iter->is_optimized) { 1831 memset(&key->opt, 0, sizeof(key->opt)); 1832 goto again; 1833 } 1834 1835 util_queue_fence_wait(&iter->ready); 1836 } 1837 1838 if (iter->compilation_failed) { 1839 return -1; /* skip the draw call */ 1840 } 1841 1842 state->current = iter; 1843 return 0; 1844 } 1845 } 1846 1847 /* Build a new shader. */ 1848 shader = CALLOC_STRUCT(si_shader); 1849 if (!shader) { 1850 mtx_unlock(&sel->mutex); 1851 return -ENOMEM; 1852 } 1853 1854 util_queue_fence_init(&shader->ready); 1855 1856 shader->selector = sel; 1857 shader->key = *key; 1858 shader->compiler_ctx_state = *compiler_state; 1859 1860 /* If this is a merged shader, get the first shader's selector. */ 1861 if (sscreen->info.chip_class >= GFX9) { 1862 if (sel->type == PIPE_SHADER_TESS_CTRL) 1863 previous_stage_sel = key->part.tcs.ls; 1864 else if (sel->type == PIPE_SHADER_GEOMETRY) 1865 previous_stage_sel = key->part.gs.es; 1866 1867 /* We need to wait for the previous shader. */ 1868 if (previous_stage_sel && thread_index < 0) 1869 util_queue_fence_wait(&previous_stage_sel->ready); 1870 } 1871 1872 /* Compile the main shader part if it doesn't exist. This can happen 1873 * if the initial guess was wrong. */ 1874 bool is_pure_monolithic = 1875 sscreen->use_monolithic_shaders || 1876 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0; 1877 1878 if (!is_pure_monolithic) { 1879 bool ok; 1880 1881 /* Make sure the main shader part is present. This is needed 1882 * for shaders that can be compiled as VS, LS, or ES, and only 1883 * one of them is compiled at creation. 1884 * 1885 * For merged shaders, check that the starting shader's main 1886 * part is present. 1887 */ 1888 if (previous_stage_sel) { 1889 struct si_shader_key shader1_key = zeroed; 1890 1891 if (sel->type == PIPE_SHADER_TESS_CTRL) 1892 shader1_key.as_ls = 1; 1893 else if (sel->type == PIPE_SHADER_GEOMETRY) 1894 shader1_key.as_es = 1; 1895 else 1896 assert(0); 1897 1898 mtx_lock(&previous_stage_sel->mutex); 1899 ok = si_check_missing_main_part(sscreen, 1900 previous_stage_sel, 1901 compiler_state, &shader1_key); 1902 mtx_unlock(&previous_stage_sel->mutex); 1903 } else { 1904 ok = si_check_missing_main_part(sscreen, sel, 1905 compiler_state, key); 1906 } 1907 if (!ok) { 1908 FREE(shader); 1909 mtx_unlock(&sel->mutex); 1910 return -ENOMEM; /* skip the draw call */ 1911 } 1912 } 1913 1914 /* Keep the reference to the 1st shader of merged shaders, so that 1915 * Gallium can't destroy it before we destroy the 2nd shader. 1916 * 1917 * Set sctx = NULL, because it's unused if we're not releasing 1918 * the shader, and we don't have any sctx here. 1919 */ 1920 si_shader_selector_reference(NULL, &shader->previous_stage_sel, 1921 previous_stage_sel); 1922 1923 /* Monolithic-only shaders don't make a distinction between optimized 1924 * and unoptimized. */ 1925 shader->is_monolithic = 1926 is_pure_monolithic || 1927 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0; 1928 1929 shader->is_optimized = 1930 !is_pure_monolithic && 1931 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0; 1932 1933 /* If it's an optimized shader, compile it asynchronously. */ 1934 if (shader->is_optimized && 1935 !is_pure_monolithic && 1936 thread_index < 0) { 1937 /* Compile it asynchronously. */ 1938 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, 1939 shader, &shader->ready, 1940 si_build_shader_variant_low_priority, NULL); 1941 1942 /* Add only after the ready fence was reset, to guard against a 1943 * race with si_bind_XX_shader. */ 1944 if (!sel->last_variant) { 1945 sel->first_variant = shader; 1946 sel->last_variant = shader; 1947 } else { 1948 sel->last_variant->next_variant = shader; 1949 sel->last_variant = shader; 1950 } 1951 1952 /* Use the default (unoptimized) shader for now. */ 1953 memset(&key->opt, 0, sizeof(key->opt)); 1954 mtx_unlock(&sel->mutex); 1955 1956 if (sscreen->options.sync_compile) 1957 util_queue_fence_wait(&shader->ready); 1958 1959 goto again; 1960 } 1961 1962 /* Reset the fence before adding to the variant list. */ 1963 util_queue_fence_reset(&shader->ready); 1964 1965 if (!sel->last_variant) { 1966 sel->first_variant = shader; 1967 sel->last_variant = shader; 1968 } else { 1969 sel->last_variant->next_variant = shader; 1970 sel->last_variant = shader; 1971 } 1972 1973 mtx_unlock(&sel->mutex); 1974 1975 assert(!shader->is_optimized); 1976 si_build_shader_variant(shader, thread_index, false); 1977 1978 util_queue_fence_signal(&shader->ready); 1979 1980 if (!shader->compilation_failed) 1981 state->current = shader; 1982 1983 return shader->compilation_failed ? -1 : 0; 1984} 1985 1986static int si_shader_select(struct pipe_context *ctx, 1987 struct si_shader_ctx_state *state, 1988 struct si_compiler_ctx_state *compiler_state) 1989{ 1990 struct si_context *sctx = (struct si_context *)ctx; 1991 struct si_shader_key key; 1992 1993 si_shader_selector_key(ctx, state->cso, &key); 1994 return si_shader_select_with_key(sctx->screen, state, compiler_state, 1995 &key, -1); 1996} 1997 1998static void si_parse_next_shader_property(const struct tgsi_shader_info *info, 1999 bool streamout, 2000 struct si_shader_key *key) 2001{ 2002 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER]; 2003 2004 switch (info->processor) { 2005 case PIPE_SHADER_VERTEX: 2006 switch (next_shader) { 2007 case PIPE_SHADER_GEOMETRY: 2008 key->as_es = 1; 2009 break; 2010 case PIPE_SHADER_TESS_CTRL: 2011 case PIPE_SHADER_TESS_EVAL: 2012 key->as_ls = 1; 2013 break; 2014 default: 2015 /* If POSITION isn't written, it can only be a HW VS 2016 * if streamout is used. If streamout isn't used, 2017 * assume that it's a HW LS. (the next shader is TCS) 2018 * This heuristic is needed for separate shader objects. 2019 */ 2020 if (!info->writes_position && !streamout) 2021 key->as_ls = 1; 2022 } 2023 break; 2024 2025 case PIPE_SHADER_TESS_EVAL: 2026 if (next_shader == PIPE_SHADER_GEOMETRY || 2027 !info->writes_position) 2028 key->as_es = 1; 2029 break; 2030 } 2031} 2032 2033/** 2034 * Compile the main shader part or the monolithic shader as part of 2035 * si_shader_selector initialization. Since it can be done asynchronously, 2036 * there is no way to report compile failures to applications. 2037 */ 2038static void si_init_shader_selector_async(void *job, int thread_index) 2039{ 2040 struct si_shader_selector *sel = (struct si_shader_selector *)job; 2041 struct si_screen *sscreen = sel->screen; 2042 struct ac_llvm_compiler *compiler; 2043 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug; 2044 2045 assert(!debug->debug_message || debug->async); 2046 assert(thread_index >= 0); 2047 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); 2048 compiler = &sscreen->compiler[thread_index]; 2049 2050 if (sel->nir) 2051 si_lower_nir(sel); 2052 2053 /* Compile the main shader part for use with a prolog and/or epilog. 2054 * If this fails, the driver will try to compile a monolithic shader 2055 * on demand. 2056 */ 2057 if (!sscreen->use_monolithic_shaders) { 2058 struct si_shader *shader = CALLOC_STRUCT(si_shader); 2059 void *ir_binary = NULL; 2060 2061 if (!shader) { 2062 fprintf(stderr, "radeonsi: can't allocate a main shader part\n"); 2063 return; 2064 } 2065 2066 /* We can leave the fence signaled because use of the default 2067 * main part is guarded by the selector's ready fence. */ 2068 util_queue_fence_init(&shader->ready); 2069 2070 shader->selector = sel; 2071 shader->is_monolithic = false; 2072 si_parse_next_shader_property(&sel->info, 2073 sel->so.num_outputs != 0, 2074 &shader->key); 2075 2076 if (sel->tokens || sel->nir) 2077 ir_binary = si_get_ir_binary(sel); 2078 2079 /* Try to load the shader from the shader cache. */ 2080 mtx_lock(&sscreen->shader_cache_mutex); 2081 2082 if (ir_binary && 2083 si_shader_cache_load_shader(sscreen, ir_binary, shader)) { 2084 mtx_unlock(&sscreen->shader_cache_mutex); 2085 si_shader_dump_stats_for_shader_db(shader, debug); 2086 } else { 2087 mtx_unlock(&sscreen->shader_cache_mutex); 2088 2089 /* Compile the shader if it hasn't been loaded from the cache. */ 2090 if (si_compile_tgsi_shader(sscreen, compiler, shader, 2091 debug) != 0) { 2092 FREE(shader); 2093 FREE(ir_binary); 2094 fprintf(stderr, "radeonsi: can't compile a main shader part\n"); 2095 return; 2096 } 2097 2098 if (ir_binary) { 2099 mtx_lock(&sscreen->shader_cache_mutex); 2100 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true)) 2101 FREE(ir_binary); 2102 mtx_unlock(&sscreen->shader_cache_mutex); 2103 } 2104 } 2105 2106 *si_get_main_shader_part(sel, &shader->key) = shader; 2107 2108 /* Unset "outputs_written" flags for outputs converted to 2109 * DEFAULT_VAL, so that later inter-shader optimizations don't 2110 * try to eliminate outputs that don't exist in the final 2111 * shader. 2112 * 2113 * This is only done if non-monolithic shaders are enabled. 2114 */ 2115 if ((sel->type == PIPE_SHADER_VERTEX || 2116 sel->type == PIPE_SHADER_TESS_EVAL) && 2117 !shader->key.as_ls && 2118 !shader->key.as_es) { 2119 unsigned i; 2120 2121 for (i = 0; i < sel->info.num_outputs; i++) { 2122 unsigned offset = shader->info.vs_output_param_offset[i]; 2123 2124 if (offset <= AC_EXP_PARAM_OFFSET_31) 2125 continue; 2126 2127 unsigned name = sel->info.output_semantic_name[i]; 2128 unsigned index = sel->info.output_semantic_index[i]; 2129 unsigned id; 2130 2131 switch (name) { 2132 case TGSI_SEMANTIC_GENERIC: 2133 /* don't process indices the function can't handle */ 2134 if (index >= SI_MAX_IO_GENERIC) 2135 break; 2136 /* fall through */ 2137 default: 2138 id = si_shader_io_get_unique_index(name, index, true); 2139 sel->outputs_written_before_ps &= ~(1ull << id); 2140 break; 2141 case TGSI_SEMANTIC_POSITION: /* ignore these */ 2142 case TGSI_SEMANTIC_PSIZE: 2143 case TGSI_SEMANTIC_CLIPVERTEX: 2144 case TGSI_SEMANTIC_EDGEFLAG: 2145 break; 2146 } 2147 } 2148 } 2149 } 2150 2151 /* The GS copy shader is always pre-compiled. */ 2152 if (sel->type == PIPE_SHADER_GEOMETRY) { 2153 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug); 2154 if (!sel->gs_copy_shader) { 2155 fprintf(stderr, "radeonsi: can't create GS copy shader\n"); 2156 return; 2157 } 2158 2159 si_shader_vs(sscreen, sel->gs_copy_shader, sel); 2160 } 2161} 2162 2163void si_schedule_initial_compile(struct si_context *sctx, unsigned processor, 2164 struct util_queue_fence *ready_fence, 2165 struct si_compiler_ctx_state *compiler_ctx_state, 2166 void *job, util_queue_execute_func execute) 2167{ 2168 util_queue_fence_init(ready_fence); 2169 2170 struct util_async_debug_callback async_debug; 2171 bool debug = 2172 (sctx->debug.debug_message && !sctx->debug.async) || 2173 sctx->is_debug || 2174 si_can_dump_shader(sctx->screen, processor); 2175 2176 if (debug) { 2177 u_async_debug_init(&async_debug); 2178 compiler_ctx_state->debug = async_debug.base; 2179 } 2180 2181 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, 2182 ready_fence, execute, NULL); 2183 2184 if (debug) { 2185 util_queue_fence_wait(ready_fence); 2186 u_async_debug_drain(&async_debug, &sctx->debug); 2187 u_async_debug_cleanup(&async_debug); 2188 } 2189 2190 if (sctx->screen->options.sync_compile) 2191 util_queue_fence_wait(ready_fence); 2192} 2193 2194/* Return descriptor slot usage masks from the given shader info. */ 2195void si_get_active_slot_masks(const struct tgsi_shader_info *info, 2196 uint32_t *const_and_shader_buffers, 2197 uint64_t *samplers_and_images) 2198{ 2199 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers; 2200 2201 num_shaderbufs = util_last_bit(info->shader_buffers_declared); 2202 num_constbufs = util_last_bit(info->const_buffers_declared); 2203 /* two 8-byte images share one 16-byte slot */ 2204 num_images = align(util_last_bit(info->images_declared), 2); 2205 num_samplers = util_last_bit(info->samplers_declared); 2206 2207 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */ 2208 start = si_get_shaderbuf_slot(num_shaderbufs - 1); 2209 *const_and_shader_buffers = 2210 u_bit_consecutive(start, num_shaderbufs + num_constbufs); 2211 2212 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */ 2213 start = si_get_image_slot(num_images - 1) / 2; 2214 *samplers_and_images = 2215 u_bit_consecutive64(start, num_images / 2 + num_samplers); 2216} 2217 2218static void *si_create_shader_selector(struct pipe_context *ctx, 2219 const struct pipe_shader_state *state) 2220{ 2221 struct si_screen *sscreen = (struct si_screen *)ctx->screen; 2222 struct si_context *sctx = (struct si_context*)ctx; 2223 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector); 2224 int i; 2225 2226 if (!sel) 2227 return NULL; 2228 2229 pipe_reference_init(&sel->reference, 1); 2230 sel->screen = sscreen; 2231 sel->compiler_ctx_state.debug = sctx->debug; 2232 sel->compiler_ctx_state.is_debug_context = sctx->is_debug; 2233 2234 sel->so = state->stream_output; 2235 2236 if (state->type == PIPE_SHADER_IR_TGSI) { 2237 sel->tokens = tgsi_dup_tokens(state->tokens); 2238 if (!sel->tokens) { 2239 FREE(sel); 2240 return NULL; 2241 } 2242 2243 tgsi_scan_shader(state->tokens, &sel->info); 2244 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info); 2245 } else { 2246 assert(state->type == PIPE_SHADER_IR_NIR); 2247 2248 sel->nir = state->ir.nir; 2249 2250 si_nir_opts(sel->nir); 2251 si_nir_scan_shader(sel->nir, &sel->info); 2252 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info); 2253 } 2254 2255 sel->type = sel->info.processor; 2256 p_atomic_inc(&sscreen->num_shaders_created); 2257 si_get_active_slot_masks(&sel->info, 2258 &sel->active_const_and_shader_buffers, 2259 &sel->active_samplers_and_images); 2260 2261 /* Record which streamout buffers are enabled. */ 2262 for (i = 0; i < sel->so.num_outputs; i++) { 2263 sel->enabled_streamout_buffer_mask |= 2264 (1 << sel->so.output[i].output_buffer) << 2265 (sel->so.output[i].stream * 4); 2266 } 2267 2268 /* The prolog is a no-op if there are no inputs. */ 2269 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX && 2270 sel->info.num_inputs && 2271 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS]; 2272 2273 sel->force_correct_derivs_after_kill = 2274 sel->type == PIPE_SHADER_FRAGMENT && 2275 sel->info.uses_derivatives && 2276 sel->info.uses_kill && 2277 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL); 2278 2279 /* Set which opcode uses which (i,j) pair. */ 2280 if (sel->info.uses_persp_opcode_interp_centroid) 2281 sel->info.uses_persp_centroid = true; 2282 2283 if (sel->info.uses_linear_opcode_interp_centroid) 2284 sel->info.uses_linear_centroid = true; 2285 2286 if (sel->info.uses_persp_opcode_interp_offset || 2287 sel->info.uses_persp_opcode_interp_sample) 2288 sel->info.uses_persp_center = true; 2289 2290 if (sel->info.uses_linear_opcode_interp_offset || 2291 sel->info.uses_linear_opcode_interp_sample) 2292 sel->info.uses_linear_center = true; 2293 2294 switch (sel->type) { 2295 case PIPE_SHADER_GEOMETRY: 2296 sel->gs_output_prim = 2297 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM]; 2298 sel->gs_max_out_vertices = 2299 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES]; 2300 sel->gs_num_invocations = 2301 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS]; 2302 sel->gsvs_vertex_size = sel->info.num_outputs * 16; 2303 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * 2304 sel->gs_max_out_vertices; 2305 2306 sel->max_gs_stream = 0; 2307 for (i = 0; i < sel->so.num_outputs; i++) 2308 sel->max_gs_stream = MAX2(sel->max_gs_stream, 2309 sel->so.output[i].stream); 2310 2311 sel->gs_input_verts_per_prim = 2312 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]); 2313 break; 2314 2315 case PIPE_SHADER_TESS_CTRL: 2316 /* Always reserve space for these. */ 2317 sel->patch_outputs_written |= 2318 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) | 2319 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0)); 2320 /* fall through */ 2321 case PIPE_SHADER_VERTEX: 2322 case PIPE_SHADER_TESS_EVAL: 2323 for (i = 0; i < sel->info.num_outputs; i++) { 2324 unsigned name = sel->info.output_semantic_name[i]; 2325 unsigned index = sel->info.output_semantic_index[i]; 2326 2327 switch (name) { 2328 case TGSI_SEMANTIC_TESSINNER: 2329 case TGSI_SEMANTIC_TESSOUTER: 2330 case TGSI_SEMANTIC_PATCH: 2331 sel->patch_outputs_written |= 2332 1ull << si_shader_io_get_unique_index_patch(name, index); 2333 break; 2334 2335 case TGSI_SEMANTIC_GENERIC: 2336 /* don't process indices the function can't handle */ 2337 if (index >= SI_MAX_IO_GENERIC) 2338 break; 2339 /* fall through */ 2340 default: 2341 sel->outputs_written |= 2342 1ull << si_shader_io_get_unique_index(name, index, false); 2343 sel->outputs_written_before_ps |= 2344 1ull << si_shader_io_get_unique_index(name, index, true); 2345 break; 2346 case TGSI_SEMANTIC_EDGEFLAG: 2347 break; 2348 } 2349 } 2350 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16; 2351 sel->lshs_vertex_stride = sel->esgs_itemsize; 2352 2353 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex 2354 * will start on a different bank. (except for the maximum 32*16). 2355 */ 2356 if (sel->lshs_vertex_stride < 32*16) 2357 sel->lshs_vertex_stride += 4; 2358 2359 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank 2360 * conflicts, i.e. each vertex will start at a different bank. 2361 */ 2362 if (sctx->chip_class >= GFX9) 2363 sel->esgs_itemsize += 4; 2364 2365 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0); 2366 break; 2367 2368 case PIPE_SHADER_FRAGMENT: 2369 for (i = 0; i < sel->info.num_inputs; i++) { 2370 unsigned name = sel->info.input_semantic_name[i]; 2371 unsigned index = sel->info.input_semantic_index[i]; 2372 2373 switch (name) { 2374 case TGSI_SEMANTIC_GENERIC: 2375 /* don't process indices the function can't handle */ 2376 if (index >= SI_MAX_IO_GENERIC) 2377 break; 2378 /* fall through */ 2379 default: 2380 sel->inputs_read |= 2381 1ull << si_shader_io_get_unique_index(name, index, true); 2382 break; 2383 case TGSI_SEMANTIC_PCOORD: /* ignore this */ 2384 break; 2385 } 2386 } 2387 2388 for (i = 0; i < 8; i++) 2389 if (sel->info.colors_written & (1 << i)) 2390 sel->colors_written_4bit |= 0xf << (4 * i); 2391 2392 for (i = 0; i < sel->info.num_inputs; i++) { 2393 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) { 2394 int index = sel->info.input_semantic_index[i]; 2395 sel->color_attr_index[index] = i; 2396 } 2397 } 2398 break; 2399 } 2400 2401 /* PA_CL_VS_OUT_CNTL */ 2402 bool misc_vec_ena = 2403 sel->info.writes_psize || sel->info.writes_edgeflag || 2404 sel->info.writes_layer || sel->info.writes_viewport_index; 2405 sel->pa_cl_vs_out_cntl = 2406 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) | 2407 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) | 2408 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) | 2409 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) | 2410 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) | 2411 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena); 2412 sel->clipdist_mask = sel->info.writes_clipvertex ? 2413 SIX_BITS : sel->info.clipdist_writemask; 2414 sel->culldist_mask = sel->info.culldist_writemask << 2415 sel->info.num_written_clipdistance; 2416 2417 /* DB_SHADER_CONTROL */ 2418 sel->db_shader_control = 2419 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) | 2420 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) | 2421 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) | 2422 S_02880C_KILL_ENABLE(sel->info.uses_kill); 2423 2424 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) { 2425 case TGSI_FS_DEPTH_LAYOUT_GREATER: 2426 sel->db_shader_control |= 2427 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z); 2428 break; 2429 case TGSI_FS_DEPTH_LAYOUT_LESS: 2430 sel->db_shader_control |= 2431 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z); 2432 break; 2433 } 2434 2435 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following: 2436 * 2437 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP 2438 * --|-----------|------------|------------|--------------------|-------------------|------------- 2439 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0 2440 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0 2441 * 2 | false | true | n/a | LateZ | 1 | 0 2442 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0 2443 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1 2444 * 2445 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register. 2446 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense. 2447 * 2448 * Don't use ReZ without profiling !!! 2449 * 2450 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex 2451 * shaders. 2452 */ 2453 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) { 2454 /* Cases 3, 4. */ 2455 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) | 2456 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) | 2457 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory); 2458 } else if (sel->info.writes_memory) { 2459 /* Case 2. */ 2460 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | 2461 S_02880C_EXEC_ON_HIER_FAIL(1); 2462 } else { 2463 /* Case 1. */ 2464 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2465 } 2466 2467 (void) mtx_init(&sel->mutex, mtx_plain); 2468 2469 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, 2470 &sel->compiler_ctx_state, sel, 2471 si_init_shader_selector_async); 2472 return sel; 2473} 2474 2475static void si_update_streamout_state(struct si_context *sctx) 2476{ 2477 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso; 2478 2479 if (!shader_with_so) 2480 return; 2481 2482 sctx->streamout.enabled_stream_buffers_mask = 2483 shader_with_so->enabled_streamout_buffer_mask; 2484 sctx->streamout.stride_in_dw = shader_with_so->so.stride; 2485} 2486 2487static void si_update_clip_regs(struct si_context *sctx, 2488 struct si_shader_selector *old_hw_vs, 2489 struct si_shader *old_hw_vs_variant, 2490 struct si_shader_selector *next_hw_vs, 2491 struct si_shader *next_hw_vs_variant) 2492{ 2493 if (next_hw_vs && 2494 (!old_hw_vs || 2495 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] != 2496 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] || 2497 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl || 2498 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask || 2499 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || 2500 !old_hw_vs_variant || 2501 !next_hw_vs_variant || 2502 old_hw_vs_variant->key.opt.clip_disable != 2503 next_hw_vs_variant->key.opt.clip_disable)) 2504 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs); 2505} 2506 2507static void si_update_common_shader_state(struct si_context *sctx) 2508{ 2509 sctx->uses_bindless_samplers = 2510 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) || 2511 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) || 2512 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) || 2513 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) || 2514 si_shader_uses_bindless_samplers(sctx->tes_shader.cso); 2515 sctx->uses_bindless_images = 2516 si_shader_uses_bindless_images(sctx->vs_shader.cso) || 2517 si_shader_uses_bindless_images(sctx->gs_shader.cso) || 2518 si_shader_uses_bindless_images(sctx->ps_shader.cso) || 2519 si_shader_uses_bindless_images(sctx->tcs_shader.cso) || 2520 si_shader_uses_bindless_images(sctx->tes_shader.cso); 2521 sctx->do_update_shaders = true; 2522} 2523 2524static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 2525{ 2526 struct si_context *sctx = (struct si_context *)ctx; 2527 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 2528 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx); 2529 struct si_shader_selector *sel = state; 2530 2531 if (sctx->vs_shader.cso == sel) 2532 return; 2533 2534 sctx->vs_shader.cso = sel; 2535 sctx->vs_shader.current = sel ? sel->first_variant : NULL; 2536 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0; 2537 2538 si_update_common_shader_state(sctx); 2539 si_update_vs_viewport_state(sctx); 2540 si_set_active_descriptors_for_shader(sctx, sel); 2541 si_update_streamout_state(sctx); 2542 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, 2543 si_get_vs(sctx)->cso, si_get_vs_state(sctx)); 2544} 2545 2546static void si_update_tess_uses_prim_id(struct si_context *sctx) 2547{ 2548 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id = 2549 (sctx->tes_shader.cso && 2550 sctx->tes_shader.cso->info.uses_primid) || 2551 (sctx->tcs_shader.cso && 2552 sctx->tcs_shader.cso->info.uses_primid) || 2553 (sctx->gs_shader.cso && 2554 sctx->gs_shader.cso->info.uses_primid) || 2555 (sctx->ps_shader.cso && !sctx->gs_shader.cso && 2556 sctx->ps_shader.cso->info.uses_primid); 2557} 2558 2559static void si_bind_gs_shader(struct pipe_context *ctx, void *state) 2560{ 2561 struct si_context *sctx = (struct si_context *)ctx; 2562 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 2563 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx); 2564 struct si_shader_selector *sel = state; 2565 bool enable_changed = !!sctx->gs_shader.cso != !!sel; 2566 2567 if (sctx->gs_shader.cso == sel) 2568 return; 2569 2570 sctx->gs_shader.cso = sel; 2571 sctx->gs_shader.current = sel ? sel->first_variant : NULL; 2572 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL; 2573 2574 si_update_common_shader_state(sctx); 2575 sctx->last_rast_prim = -1; /* reset this so that it gets updated */ 2576 2577 if (enable_changed) { 2578 si_shader_change_notify(sctx); 2579 if (sctx->ia_multi_vgt_param_key.u.uses_tess) 2580 si_update_tess_uses_prim_id(sctx); 2581 } 2582 si_update_vs_viewport_state(sctx); 2583 si_set_active_descriptors_for_shader(sctx, sel); 2584 si_update_streamout_state(sctx); 2585 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, 2586 si_get_vs(sctx)->cso, si_get_vs_state(sctx)); 2587} 2588 2589static void si_bind_tcs_shader(struct pipe_context *ctx, void *state) 2590{ 2591 struct si_context *sctx = (struct si_context *)ctx; 2592 struct si_shader_selector *sel = state; 2593 bool enable_changed = !!sctx->tcs_shader.cso != !!sel; 2594 2595 if (sctx->tcs_shader.cso == sel) 2596 return; 2597 2598 sctx->tcs_shader.cso = sel; 2599 sctx->tcs_shader.current = sel ? sel->first_variant : NULL; 2600 si_update_tess_uses_prim_id(sctx); 2601 2602 si_update_common_shader_state(sctx); 2603 2604 if (enable_changed) 2605 sctx->last_tcs = NULL; /* invalidate derived tess state */ 2606 2607 si_set_active_descriptors_for_shader(sctx, sel); 2608} 2609 2610static void si_bind_tes_shader(struct pipe_context *ctx, void *state) 2611{ 2612 struct si_context *sctx = (struct si_context *)ctx; 2613 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 2614 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx); 2615 struct si_shader_selector *sel = state; 2616 bool enable_changed = !!sctx->tes_shader.cso != !!sel; 2617 2618 if (sctx->tes_shader.cso == sel) 2619 return; 2620 2621 sctx->tes_shader.cso = sel; 2622 sctx->tes_shader.current = sel ? sel->first_variant : NULL; 2623 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL; 2624 si_update_tess_uses_prim_id(sctx); 2625 2626 si_update_common_shader_state(sctx); 2627 sctx->last_rast_prim = -1; /* reset this so that it gets updated */ 2628 2629 if (enable_changed) { 2630 si_shader_change_notify(sctx); 2631 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */ 2632 } 2633 si_update_vs_viewport_state(sctx); 2634 si_set_active_descriptors_for_shader(sctx, sel); 2635 si_update_streamout_state(sctx); 2636 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, 2637 si_get_vs(sctx)->cso, si_get_vs_state(sctx)); 2638} 2639 2640static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 2641{ 2642 struct si_context *sctx = (struct si_context *)ctx; 2643 struct si_shader_selector *old_sel = sctx->ps_shader.cso; 2644 struct si_shader_selector *sel = state; 2645 2646 /* skip if supplied shader is one already in use */ 2647 if (old_sel == sel) 2648 return; 2649 2650 sctx->ps_shader.cso = sel; 2651 sctx->ps_shader.current = sel ? sel->first_variant : NULL; 2652 2653 si_update_common_shader_state(sctx); 2654 if (sel) { 2655 if (sctx->ia_multi_vgt_param_key.u.uses_tess) 2656 si_update_tess_uses_prim_id(sctx); 2657 2658 if (!old_sel || 2659 old_sel->info.colors_written != sel->info.colors_written) 2660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); 2661 2662 if (sctx->screen->has_out_of_order_rast && 2663 (!old_sel || 2664 old_sel->info.writes_memory != sel->info.writes_memory || 2665 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] != 2666 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])) 2667 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); 2668 } 2669 si_set_active_descriptors_for_shader(sctx, sel); 2670 si_update_ps_colorbuf0_slot(sctx); 2671} 2672 2673static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) 2674{ 2675 if (shader->is_optimized) { 2676 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority, 2677 &shader->ready); 2678 } 2679 2680 util_queue_fence_destroy(&shader->ready); 2681 2682 if (shader->pm4) { 2683 switch (shader->selector->type) { 2684 case PIPE_SHADER_VERTEX: 2685 if (shader->key.as_ls) { 2686 assert(sctx->chip_class <= VI); 2687 si_pm4_delete_state(sctx, ls, shader->pm4); 2688 } else if (shader->key.as_es) { 2689 assert(sctx->chip_class <= VI); 2690 si_pm4_delete_state(sctx, es, shader->pm4); 2691 } else { 2692 si_pm4_delete_state(sctx, vs, shader->pm4); 2693 } 2694 break; 2695 case PIPE_SHADER_TESS_CTRL: 2696 si_pm4_delete_state(sctx, hs, shader->pm4); 2697 break; 2698 case PIPE_SHADER_TESS_EVAL: 2699 if (shader->key.as_es) { 2700 assert(sctx->chip_class <= VI); 2701 si_pm4_delete_state(sctx, es, shader->pm4); 2702 } else { 2703 si_pm4_delete_state(sctx, vs, shader->pm4); 2704 } 2705 break; 2706 case PIPE_SHADER_GEOMETRY: 2707 if (shader->is_gs_copy_shader) 2708 si_pm4_delete_state(sctx, vs, shader->pm4); 2709 else 2710 si_pm4_delete_state(sctx, gs, shader->pm4); 2711 break; 2712 case PIPE_SHADER_FRAGMENT: 2713 si_pm4_delete_state(sctx, ps, shader->pm4); 2714 break; 2715 } 2716 } 2717 2718 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL); 2719 si_shader_destroy(shader); 2720 free(shader); 2721} 2722 2723void si_destroy_shader_selector(struct si_context *sctx, 2724 struct si_shader_selector *sel) 2725{ 2726 struct si_shader *p = sel->first_variant, *c; 2727 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = { 2728 [PIPE_SHADER_VERTEX] = &sctx->vs_shader, 2729 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader, 2730 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader, 2731 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader, 2732 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader, 2733 }; 2734 2735 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready); 2736 2737 if (current_shader[sel->type]->cso == sel) { 2738 current_shader[sel->type]->cso = NULL; 2739 current_shader[sel->type]->current = NULL; 2740 } 2741 2742 while (p) { 2743 c = p->next_variant; 2744 si_delete_shader(sctx, p); 2745 p = c; 2746 } 2747 2748 if (sel->main_shader_part) 2749 si_delete_shader(sctx, sel->main_shader_part); 2750 if (sel->main_shader_part_ls) 2751 si_delete_shader(sctx, sel->main_shader_part_ls); 2752 if (sel->main_shader_part_es) 2753 si_delete_shader(sctx, sel->main_shader_part_es); 2754 if (sel->gs_copy_shader) 2755 si_delete_shader(sctx, sel->gs_copy_shader); 2756 2757 util_queue_fence_destroy(&sel->ready); 2758 mtx_destroy(&sel->mutex); 2759 free(sel->tokens); 2760 ralloc_free(sel->nir); 2761 free(sel); 2762} 2763 2764static void si_delete_shader_selector(struct pipe_context *ctx, void *state) 2765{ 2766 struct si_context *sctx = (struct si_context *)ctx; 2767 struct si_shader_selector *sel = (struct si_shader_selector *)state; 2768 2769 si_shader_selector_reference(sctx, &sel, NULL); 2770} 2771 2772static unsigned si_get_ps_input_cntl(struct si_context *sctx, 2773 struct si_shader *vs, unsigned name, 2774 unsigned index, unsigned interpolate) 2775{ 2776 struct tgsi_shader_info *vsinfo = &vs->selector->info; 2777 unsigned j, offset, ps_input_cntl = 0; 2778 2779 if (interpolate == TGSI_INTERPOLATE_CONSTANT || 2780 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade)) 2781 ps_input_cntl |= S_028644_FLAT_SHADE(1); 2782 2783 if (name == TGSI_SEMANTIC_PCOORD || 2784 (name == TGSI_SEMANTIC_TEXCOORD && 2785 sctx->sprite_coord_enable & (1 << index))) { 2786 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1); 2787 } 2788 2789 for (j = 0; j < vsinfo->num_outputs; j++) { 2790 if (name == vsinfo->output_semantic_name[j] && 2791 index == vsinfo->output_semantic_index[j]) { 2792 offset = vs->info.vs_output_param_offset[j]; 2793 2794 if (offset <= AC_EXP_PARAM_OFFSET_31) { 2795 /* The input is loaded from parameter memory. */ 2796 ps_input_cntl |= S_028644_OFFSET(offset); 2797 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) { 2798 if (offset == AC_EXP_PARAM_UNDEFINED) { 2799 /* This can happen with depth-only rendering. */ 2800 offset = 0; 2801 } else { 2802 /* The input is a DEFAULT_VAL constant. */ 2803 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 && 2804 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111); 2805 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000; 2806 } 2807 2808 ps_input_cntl = S_028644_OFFSET(0x20) | 2809 S_028644_DEFAULT_VAL(offset); 2810 } 2811 break; 2812 } 2813 } 2814 2815 if (name == TGSI_SEMANTIC_PRIMID) 2816 /* PrimID is written after the last output. */ 2817 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]); 2818 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) { 2819 /* No corresponding output found, load defaults into input. 2820 * Don't set any other bits. 2821 * (FLAT_SHADE=1 completely changes behavior) */ 2822 ps_input_cntl = S_028644_OFFSET(0x20); 2823 /* D3D 9 behaviour. GL is undefined */ 2824 if (name == TGSI_SEMANTIC_COLOR && index == 0) 2825 ps_input_cntl |= S_028644_DEFAULT_VAL(3); 2826 } 2827 return ps_input_cntl; 2828} 2829 2830static void si_emit_spi_map(struct si_context *sctx) 2831{ 2832 struct si_shader *ps = sctx->ps_shader.current; 2833 struct si_shader *vs = si_get_vs_state(sctx); 2834 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL; 2835 unsigned i, num_interp, num_written = 0, bcol_interp[2]; 2836 unsigned spi_ps_input_cntl[32]; 2837 2838 if (!ps || !ps->selector->info.num_inputs) 2839 return; 2840 2841 num_interp = si_get_ps_num_interp(ps); 2842 assert(num_interp > 0); 2843 2844 for (i = 0; i < psinfo->num_inputs; i++) { 2845 unsigned name = psinfo->input_semantic_name[i]; 2846 unsigned index = psinfo->input_semantic_index[i]; 2847 unsigned interpolate = psinfo->input_interpolate[i]; 2848 2849 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name, 2850 index, interpolate); 2851 2852 if (name == TGSI_SEMANTIC_COLOR) { 2853 assert(index < ARRAY_SIZE(bcol_interp)); 2854 bcol_interp[index] = interpolate; 2855 } 2856 } 2857 2858 if (ps->key.part.ps.prolog.color_two_side) { 2859 unsigned bcol = TGSI_SEMANTIC_BCOLOR; 2860 2861 for (i = 0; i < 2; i++) { 2862 if (!(psinfo->colors_read & (0xf << (i * 4)))) 2863 continue; 2864 2865 spi_ps_input_cntl[num_written++] = 2866 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]); 2867 2868 } 2869 } 2870 assert(num_interp == num_written); 2871 2872 /* R_028644_SPI_PS_INPUT_CNTL_0 */ 2873 /* Dota 2: Only ~16% of SPI map updates set different values. */ 2874 /* Talos: Only ~9% of SPI map updates set different values. */ 2875 unsigned initial_cdw = sctx->gfx_cs->current.cdw; 2876 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, 2877 spi_ps_input_cntl, 2878 sctx->tracked_regs.spi_ps_input_cntl, num_interp); 2879 2880 if (initial_cdw != sctx->gfx_cs->current.cdw) 2881 sctx->context_roll = true; 2882} 2883 2884/** 2885 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that. 2886 */ 2887static void si_init_config_add_vgt_flush(struct si_context *sctx) 2888{ 2889 if (sctx->init_config_has_vgt_flush) 2890 return; 2891 2892 /* Done by Vulkan before VGT_FLUSH. */ 2893 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE); 2894 si_pm4_cmd_add(sctx->init_config, 2895 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 2896 si_pm4_cmd_end(sctx->init_config, false); 2897 2898 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */ 2899 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE); 2900 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); 2901 si_pm4_cmd_end(sctx->init_config, false); 2902 sctx->init_config_has_vgt_flush = true; 2903} 2904 2905/* Initialize state related to ESGS / GSVS ring buffers */ 2906static bool si_update_gs_ring_buffers(struct si_context *sctx) 2907{ 2908 struct si_shader_selector *es = 2909 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso; 2910 struct si_shader_selector *gs = sctx->gs_shader.cso; 2911 struct si_pm4_state *pm4; 2912 2913 /* Chip constants. */ 2914 unsigned num_se = sctx->screen->info.max_se; 2915 unsigned wave_size = 64; 2916 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ 2917 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16. 2918 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). 2919 */ 2920 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se; 2921 unsigned alignment = 256 * num_se; 2922 /* The maximum size is 63.999 MB per SE. */ 2923 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; 2924 2925 /* Calculate the minimum size. */ 2926 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse * 2927 wave_size, alignment); 2928 2929 /* These are recommended sizes, not minimum sizes. */ 2930 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size * 2931 es->esgs_itemsize * gs->gs_input_verts_per_prim; 2932 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * 2933 gs->max_gsvs_emit_size; 2934 2935 min_esgs_ring_size = align(min_esgs_ring_size, alignment); 2936 esgs_ring_size = align(esgs_ring_size, alignment); 2937 gsvs_ring_size = align(gsvs_ring_size, alignment); 2938 2939 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); 2940 gsvs_ring_size = MIN2(gsvs_ring_size, max_size); 2941 2942 /* Some rings don't have to be allocated if shaders don't use them. 2943 * (e.g. no varyings between ES and GS or GS and VS) 2944 * 2945 * GFX9 doesn't have the ESGS ring. 2946 */ 2947 bool update_esgs = sctx->chip_class <= VI && 2948 esgs_ring_size && 2949 (!sctx->esgs_ring || 2950 sctx->esgs_ring->width0 < esgs_ring_size); 2951 bool update_gsvs = gsvs_ring_size && 2952 (!sctx->gsvs_ring || 2953 sctx->gsvs_ring->width0 < gsvs_ring_size); 2954 2955 if (!update_esgs && !update_gsvs) 2956 return true; 2957 2958 if (update_esgs) { 2959 pipe_resource_reference(&sctx->esgs_ring, NULL); 2960 sctx->esgs_ring = 2961 pipe_aligned_buffer_create(sctx->b.screen, 2962 SI_RESOURCE_FLAG_UNMAPPABLE, 2963 PIPE_USAGE_DEFAULT, 2964 esgs_ring_size, alignment); 2965 if (!sctx->esgs_ring) 2966 return false; 2967 } 2968 2969 if (update_gsvs) { 2970 pipe_resource_reference(&sctx->gsvs_ring, NULL); 2971 sctx->gsvs_ring = 2972 pipe_aligned_buffer_create(sctx->b.screen, 2973 SI_RESOURCE_FLAG_UNMAPPABLE, 2974 PIPE_USAGE_DEFAULT, 2975 gsvs_ring_size, alignment); 2976 if (!sctx->gsvs_ring) 2977 return false; 2978 } 2979 2980 /* Create the "init_config_gs_rings" state. */ 2981 pm4 = CALLOC_STRUCT(si_pm4_state); 2982 if (!pm4) 2983 return false; 2984 2985 if (sctx->chip_class >= CIK) { 2986 if (sctx->esgs_ring) { 2987 assert(sctx->chip_class <= VI); 2988 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, 2989 sctx->esgs_ring->width0 / 256); 2990 } 2991 if (sctx->gsvs_ring) 2992 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE, 2993 sctx->gsvs_ring->width0 / 256); 2994 } else { 2995 if (sctx->esgs_ring) 2996 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE, 2997 sctx->esgs_ring->width0 / 256); 2998 if (sctx->gsvs_ring) 2999 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE, 3000 sctx->gsvs_ring->width0 / 256); 3001 } 3002 3003 /* Set the state. */ 3004 if (sctx->init_config_gs_rings) 3005 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0); 3006 sctx->init_config_gs_rings = pm4; 3007 3008 if (!sctx->init_config_has_vgt_flush) { 3009 si_init_config_add_vgt_flush(sctx); 3010 si_pm4_upload_indirect_buffer(sctx, sctx->init_config); 3011 } 3012 3013 /* Flush the context to re-emit both init_config states. */ 3014 sctx->initial_gfx_cs_size = 0; /* force flush */ 3015 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 3016 3017 /* Set ring bindings. */ 3018 if (sctx->esgs_ring) { 3019 assert(sctx->chip_class <= VI); 3020 si_set_ring_buffer(sctx, SI_ES_RING_ESGS, 3021 sctx->esgs_ring, 0, sctx->esgs_ring->width0, 3022 true, true, 4, 64, 0); 3023 si_set_ring_buffer(sctx, SI_GS_RING_ESGS, 3024 sctx->esgs_ring, 0, sctx->esgs_ring->width0, 3025 false, false, 0, 0, 0); 3026 } 3027 if (sctx->gsvs_ring) { 3028 si_set_ring_buffer(sctx, SI_RING_GSVS, 3029 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, 3030 false, false, 0, 0, 0); 3031 } 3032 3033 return true; 3034} 3035 3036static void si_shader_lock(struct si_shader *shader) 3037{ 3038 mtx_lock(&shader->selector->mutex); 3039 if (shader->previous_stage_sel) { 3040 assert(shader->previous_stage_sel != shader->selector); 3041 mtx_lock(&shader->previous_stage_sel->mutex); 3042 } 3043} 3044 3045static void si_shader_unlock(struct si_shader *shader) 3046{ 3047 if (shader->previous_stage_sel) 3048 mtx_unlock(&shader->previous_stage_sel->mutex); 3049 mtx_unlock(&shader->selector->mutex); 3050} 3051 3052/** 3053 * @returns 1 if \p sel has been updated to use a new scratch buffer 3054 * 0 if not 3055 * < 0 if there was a failure 3056 */ 3057static int si_update_scratch_buffer(struct si_context *sctx, 3058 struct si_shader *shader) 3059{ 3060 uint64_t scratch_va = sctx->scratch_buffer->gpu_address; 3061 int r; 3062 3063 if (!shader) 3064 return 0; 3065 3066 /* This shader doesn't need a scratch buffer */ 3067 if (shader->config.scratch_bytes_per_wave == 0) 3068 return 0; 3069 3070 /* Prevent race conditions when updating: 3071 * - si_shader::scratch_bo 3072 * - si_shader::binary::code 3073 * - si_shader::previous_stage::binary::code. 3074 */ 3075 si_shader_lock(shader); 3076 3077 /* This shader is already configured to use the current 3078 * scratch buffer. */ 3079 if (shader->scratch_bo == sctx->scratch_buffer) { 3080 si_shader_unlock(shader); 3081 return 0; 3082 } 3083 3084 assert(sctx->scratch_buffer); 3085 3086 if (shader->previous_stage) 3087 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va); 3088 3089 si_shader_apply_scratch_relocs(shader, scratch_va); 3090 3091 /* Replace the shader bo with a new bo that has the relocs applied. */ 3092 r = si_shader_binary_upload(sctx->screen, shader); 3093 if (r) { 3094 si_shader_unlock(shader); 3095 return r; 3096 } 3097 3098 /* Update the shader state to use the new shader bo. */ 3099 si_shader_init_pm4_state(sctx->screen, shader); 3100 3101 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer); 3102 3103 si_shader_unlock(shader); 3104 return 1; 3105} 3106 3107static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader) 3108{ 3109 return shader ? shader->config.scratch_bytes_per_wave : 0; 3110} 3111 3112static struct si_shader *si_get_tcs_current(struct si_context *sctx) 3113{ 3114 if (!sctx->tes_shader.cso) 3115 return NULL; /* tessellation disabled */ 3116 3117 return sctx->tcs_shader.cso ? sctx->tcs_shader.current : 3118 sctx->fixed_func_tcs_shader.current; 3119} 3120 3121static bool si_update_scratch_relocs(struct si_context *sctx) 3122{ 3123 struct si_shader *tcs = si_get_tcs_current(sctx); 3124 int r; 3125 3126 /* Update the shaders, so that they are using the latest scratch. 3127 * The scratch buffer may have been changed since these shaders were 3128 * last used, so we still need to try to update them, even if they 3129 * require scratch buffers smaller than the current size. 3130 */ 3131 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current); 3132 if (r < 0) 3133 return false; 3134 if (r == 1) 3135 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4); 3136 3137 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current); 3138 if (r < 0) 3139 return false; 3140 if (r == 1) 3141 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4); 3142 3143 r = si_update_scratch_buffer(sctx, tcs); 3144 if (r < 0) 3145 return false; 3146 if (r == 1) 3147 si_pm4_bind_state(sctx, hs, tcs->pm4); 3148 3149 /* VS can be bound as LS, ES, or VS. */ 3150 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current); 3151 if (r < 0) 3152 return false; 3153 if (r == 1) { 3154 if (sctx->tes_shader.current) 3155 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4); 3156 else if (sctx->gs_shader.current) 3157 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4); 3158 else 3159 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4); 3160 } 3161 3162 /* TES can be bound as ES or VS. */ 3163 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current); 3164 if (r < 0) 3165 return false; 3166 if (r == 1) { 3167 if (sctx->gs_shader.current) 3168 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4); 3169 else 3170 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4); 3171 } 3172 3173 return true; 3174} 3175 3176static bool si_update_spi_tmpring_size(struct si_context *sctx) 3177{ 3178 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer. 3179 * There are 2 cases to handle: 3180 * 3181 * - If the current needed size is less than the maximum seen size, 3182 * use the maximum seen size, so that WAVESIZE remains the same. 3183 * 3184 * - If the current needed size is greater than the maximum seen size, 3185 * the scratch buffer is reallocated, so we can increase WAVESIZE. 3186 * 3187 * Shaders that set SCRATCH_EN=0 don't allocate scratch space. 3188 * Otherwise, the number of waves that can use scratch is 3189 * SPI_TMPRING_SIZE.WAVES. 3190 */ 3191 unsigned bytes = 0; 3192 3193 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current)); 3194 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current)); 3195 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current)); 3196 3197 if (sctx->tes_shader.cso) { 3198 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current)); 3199 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx))); 3200 } 3201 3202 sctx->max_seen_scratch_bytes_per_wave = 3203 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes); 3204 3205 unsigned scratch_needed_size = 3206 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves; 3207 unsigned spi_tmpring_size; 3208 3209 if (scratch_needed_size > 0) { 3210 if (!sctx->scratch_buffer || 3211 scratch_needed_size > sctx->scratch_buffer->b.b.width0) { 3212 /* Create a bigger scratch buffer */ 3213 si_resource_reference(&sctx->scratch_buffer, NULL); 3214 3215 sctx->scratch_buffer = 3216 si_aligned_buffer_create(&sctx->screen->b, 3217 SI_RESOURCE_FLAG_UNMAPPABLE, 3218 PIPE_USAGE_DEFAULT, 3219 scratch_needed_size, 256); 3220 if (!sctx->scratch_buffer) 3221 return false; 3222 3223 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state); 3224 si_context_add_resource_size(sctx, 3225 &sctx->scratch_buffer->b.b); 3226 } 3227 3228 if (!si_update_scratch_relocs(sctx)) 3229 return false; 3230 } 3231 3232 /* The LLVM shader backend should be reporting aligned scratch_sizes. */ 3233 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size && 3234 "scratch size should already be aligned correctly."); 3235 3236 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) | 3237 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10); 3238 if (spi_tmpring_size != sctx->spi_tmpring_size) { 3239 sctx->spi_tmpring_size = spi_tmpring_size; 3240 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state); 3241 } 3242 return true; 3243} 3244 3245static void si_init_tess_factor_ring(struct si_context *sctx) 3246{ 3247 assert(!sctx->tess_rings); 3248 3249 /* The address must be aligned to 2^19, because the shader only 3250 * receives the high 13 bits. 3251 */ 3252 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen, 3253 SI_RESOURCE_FLAG_32BIT, 3254 PIPE_USAGE_DEFAULT, 3255 sctx->screen->tess_offchip_ring_size + 3256 sctx->screen->tess_factor_ring_size, 3257 1 << 19); 3258 if (!sctx->tess_rings) 3259 return; 3260 3261 si_init_config_add_vgt_flush(sctx); 3262 3263 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings), 3264 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS); 3265 3266 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address + 3267 sctx->screen->tess_offchip_ring_size; 3268 3269 /* Append these registers to the init config state. */ 3270 if (sctx->chip_class >= CIK) { 3271 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE, 3272 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3273 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE, 3274 factor_va >> 8); 3275 if (sctx->chip_class >= GFX9) 3276 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI, 3277 S_030944_BASE_HI(factor_va >> 40)); 3278 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM, 3279 sctx->screen->vgt_hs_offchip_param); 3280 } else { 3281 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE, 3282 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3283 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE, 3284 factor_va >> 8); 3285 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM, 3286 sctx->screen->vgt_hs_offchip_param); 3287 } 3288 3289 /* Flush the context to re-emit the init_config state. 3290 * This is done only once in a lifetime of a context. 3291 */ 3292 si_pm4_upload_indirect_buffer(sctx, sctx->init_config); 3293 sctx->initial_gfx_cs_size = 0; /* force flush */ 3294 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 3295} 3296 3297static void si_update_vgt_shader_config(struct si_context *sctx) 3298{ 3299 /* Calculate the index of the config. 3300 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */ 3301 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso; 3302 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index]; 3303 3304 if (!*pm4) { 3305 uint32_t stages = 0; 3306 3307 *pm4 = CALLOC_STRUCT(si_pm4_state); 3308 3309 if (sctx->tes_shader.cso) { 3310 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | 3311 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1); 3312 3313 if (sctx->gs_shader.cso) 3314 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) | 3315 S_028B54_GS_EN(1) | 3316 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 3317 else 3318 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); 3319 } else if (sctx->gs_shader.cso) { 3320 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | 3321 S_028B54_GS_EN(1) | 3322 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 3323 } 3324 3325 if (sctx->chip_class >= GFX9) 3326 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); 3327 3328 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages); 3329 } 3330 si_pm4_bind_state(sctx, vgt_shader_config, *pm4); 3331} 3332 3333bool si_update_shaders(struct si_context *sctx) 3334{ 3335 struct pipe_context *ctx = (struct pipe_context*)sctx; 3336 struct si_compiler_ctx_state compiler_state; 3337 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 3338 struct si_shader *old_vs = si_get_vs_state(sctx); 3339 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false; 3340 struct si_shader *old_ps = sctx->ps_shader.current; 3341 unsigned old_spi_shader_col_format = 3342 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0; 3343 int r; 3344 3345 compiler_state.compiler = &sctx->compiler; 3346 compiler_state.debug = sctx->debug; 3347 compiler_state.is_debug_context = sctx->is_debug; 3348 3349 /* Update stages before GS. */ 3350 if (sctx->tes_shader.cso) { 3351 if (!sctx->tess_rings) { 3352 si_init_tess_factor_ring(sctx); 3353 if (!sctx->tess_rings) 3354 return false; 3355 } 3356 3357 /* VS as LS */ 3358 if (sctx->chip_class <= VI) { 3359 r = si_shader_select(ctx, &sctx->vs_shader, 3360 &compiler_state); 3361 if (r) 3362 return false; 3363 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4); 3364 } 3365 3366 if (sctx->tcs_shader.cso) { 3367 r = si_shader_select(ctx, &sctx->tcs_shader, 3368 &compiler_state); 3369 if (r) 3370 return false; 3371 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4); 3372 } else { 3373 if (!sctx->fixed_func_tcs_shader.cso) { 3374 sctx->fixed_func_tcs_shader.cso = 3375 si_create_fixed_func_tcs(sctx); 3376 if (!sctx->fixed_func_tcs_shader.cso) 3377 return false; 3378 } 3379 3380 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader, 3381 &compiler_state); 3382 if (r) 3383 return false; 3384 si_pm4_bind_state(sctx, hs, 3385 sctx->fixed_func_tcs_shader.current->pm4); 3386 } 3387 3388 if (sctx->gs_shader.cso) { 3389 /* TES as ES */ 3390 if (sctx->chip_class <= VI) { 3391 r = si_shader_select(ctx, &sctx->tes_shader, 3392 &compiler_state); 3393 if (r) 3394 return false; 3395 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4); 3396 } 3397 } else { 3398 /* TES as VS */ 3399 r = si_shader_select(ctx, &sctx->tes_shader, 3400 &compiler_state); 3401 if (r) 3402 return false; 3403 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4); 3404 } 3405 } else if (sctx->gs_shader.cso) { 3406 if (sctx->chip_class <= VI) { 3407 /* VS as ES */ 3408 r = si_shader_select(ctx, &sctx->vs_shader, 3409 &compiler_state); 3410 if (r) 3411 return false; 3412 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4); 3413 3414 si_pm4_bind_state(sctx, ls, NULL); 3415 si_pm4_bind_state(sctx, hs, NULL); 3416 } 3417 } else { 3418 /* VS as VS */ 3419 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state); 3420 if (r) 3421 return false; 3422 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4); 3423 si_pm4_bind_state(sctx, ls, NULL); 3424 si_pm4_bind_state(sctx, hs, NULL); 3425 } 3426 3427 /* Update GS. */ 3428 if (sctx->gs_shader.cso) { 3429 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state); 3430 if (r) 3431 return false; 3432 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4); 3433 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4); 3434 3435 if (!si_update_gs_ring_buffers(sctx)) 3436 return false; 3437 } else { 3438 si_pm4_bind_state(sctx, gs, NULL); 3439 if (sctx->chip_class <= VI) 3440 si_pm4_bind_state(sctx, es, NULL); 3441 } 3442 3443 si_update_vgt_shader_config(sctx); 3444 3445 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable) 3446 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs); 3447 3448 if (sctx->ps_shader.cso) { 3449 unsigned db_shader_control; 3450 3451 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state); 3452 if (r) 3453 return false; 3454 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4); 3455 3456 db_shader_control = 3457 sctx->ps_shader.cso->db_shader_control | 3458 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS); 3459 3460 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) || 3461 sctx->sprite_coord_enable != rs->sprite_coord_enable || 3462 sctx->flatshade != rs->flatshade) { 3463 sctx->sprite_coord_enable = rs->sprite_coord_enable; 3464 sctx->flatshade = rs->flatshade; 3465 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map); 3466 } 3467 3468 if (sctx->screen->rbplus_allowed && 3469 si_pm4_state_changed(sctx, ps) && 3470 (!old_ps || 3471 old_spi_shader_col_format != 3472 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format)) 3473 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); 3474 3475 if (sctx->ps_db_shader_control != db_shader_control) { 3476 sctx->ps_db_shader_control = db_shader_control; 3477 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 3478 if (sctx->screen->dpbb_allowed) 3479 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 3480 } 3481 3482 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) { 3483 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing; 3484 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); 3485 3486 if (sctx->chip_class == SI) 3487 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 3488 3489 if (sctx->framebuffer.nr_samples <= 1) 3490 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs); 3491 } 3492 } 3493 3494 if (si_pm4_state_enabled_and_changed(sctx, ls) || 3495 si_pm4_state_enabled_and_changed(sctx, hs) || 3496 si_pm4_state_enabled_and_changed(sctx, es) || 3497 si_pm4_state_enabled_and_changed(sctx, gs) || 3498 si_pm4_state_enabled_and_changed(sctx, vs) || 3499 si_pm4_state_enabled_and_changed(sctx, ps)) { 3500 if (!si_update_spi_tmpring_size(sctx)) 3501 return false; 3502 } 3503 3504 if (sctx->chip_class >= CIK) { 3505 if (si_pm4_state_enabled_and_changed(sctx, ls)) 3506 sctx->prefetch_L2_mask |= SI_PREFETCH_LS; 3507 else if (!sctx->queued.named.ls) 3508 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS; 3509 3510 if (si_pm4_state_enabled_and_changed(sctx, hs)) 3511 sctx->prefetch_L2_mask |= SI_PREFETCH_HS; 3512 else if (!sctx->queued.named.hs) 3513 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS; 3514 3515 if (si_pm4_state_enabled_and_changed(sctx, es)) 3516 sctx->prefetch_L2_mask |= SI_PREFETCH_ES; 3517 else if (!sctx->queued.named.es) 3518 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES; 3519 3520 if (si_pm4_state_enabled_and_changed(sctx, gs)) 3521 sctx->prefetch_L2_mask |= SI_PREFETCH_GS; 3522 else if (!sctx->queued.named.gs) 3523 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS; 3524 3525 if (si_pm4_state_enabled_and_changed(sctx, vs)) 3526 sctx->prefetch_L2_mask |= SI_PREFETCH_VS; 3527 else if (!sctx->queued.named.vs) 3528 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS; 3529 3530 if (si_pm4_state_enabled_and_changed(sctx, ps)) 3531 sctx->prefetch_L2_mask |= SI_PREFETCH_PS; 3532 else if (!sctx->queued.named.ps) 3533 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS; 3534 } 3535 3536 sctx->do_update_shaders = false; 3537 return true; 3538} 3539 3540static void si_emit_scratch_state(struct si_context *sctx) 3541{ 3542 struct radeon_cmdbuf *cs = sctx->gfx_cs; 3543 3544 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, 3545 sctx->spi_tmpring_size); 3546 3547 if (sctx->scratch_buffer) { 3548 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, 3549 sctx->scratch_buffer, RADEON_USAGE_READWRITE, 3550 RADEON_PRIO_SCRATCH_BUFFER); 3551 } 3552} 3553 3554void si_init_shader_functions(struct si_context *sctx) 3555{ 3556 sctx->atoms.s.spi_map.emit = si_emit_spi_map; 3557 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state; 3558 3559 sctx->b.create_vs_state = si_create_shader_selector; 3560 sctx->b.create_tcs_state = si_create_shader_selector; 3561 sctx->b.create_tes_state = si_create_shader_selector; 3562 sctx->b.create_gs_state = si_create_shader_selector; 3563 sctx->b.create_fs_state = si_create_shader_selector; 3564 3565 sctx->b.bind_vs_state = si_bind_vs_shader; 3566 sctx->b.bind_tcs_state = si_bind_tcs_shader; 3567 sctx->b.bind_tes_state = si_bind_tes_shader; 3568 sctx->b.bind_gs_state = si_bind_gs_shader; 3569 sctx->b.bind_fs_state = si_bind_ps_shader; 3570 3571 sctx->b.delete_vs_state = si_delete_shader_selector; 3572 sctx->b.delete_tcs_state = si_delete_shader_selector; 3573 sctx->b.delete_tes_state = si_delete_shader_selector; 3574 sctx->b.delete_gs_state = si_delete_shader_selector; 3575 sctx->b.delete_fs_state = si_delete_shader_selector; 3576} 3577