1/**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef SP_TEX_TILE_CACHE_H
29#define SP_TEX_TILE_CACHE_H
30
31
32#include "pipe/p_compiler.h"
33#include "sp_limits.h"
34
35
36struct softpipe_context;
37struct softpipe_tex_tile_cache;
38
39
40/**
41 * Cache tile size (width and height). This needs to be a power of two.
42 */
43#define TEX_TILE_SIZE_LOG2 5
44#define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
45
46#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
47#define TEX_Y_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
48
49/**
50 * Texture tile address as a union for fast compares.
51 */
52union tex_tile_address {
53   struct {
54      unsigned x:TEX_ADDR_BITS;  /* 16K -- need extra bits for texture buffers */
55      unsigned y:TEX_Y_BITS;  /* 16K / TILE_SIZE */
56      unsigned z:TEX_ADDR_BITS;  /* 16K -- z not tiled */
57      unsigned level:4;
58      unsigned invalid:1;
59   } bits;
60   uint64_t value;
61};
62
63
64struct softpipe_tex_cached_tile
65{
66   union tex_tile_address addr;
67   union {
68      float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
69      unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
70      int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
71   } data;
72};
73
74/*
75 * The number of cache entries.
76 * Should not be decreased to lower than 16, and even that
77 * seems too low to avoid cache thrashing in some cases (because
78 * the cache is direct mapped, see tex_cache_pos() function).
79 */
80#define NUM_TEX_TILE_ENTRIES 16
81
82struct softpipe_tex_tile_cache
83{
84   struct pipe_context *pipe;
85   struct pipe_transfer *transfer;
86   void *transfer_map;
87
88   struct pipe_resource *texture;  /**< if caching a texture */
89   unsigned timestamp;
90
91   struct softpipe_tex_cached_tile entries[NUM_TEX_TILE_ENTRIES];
92
93   struct pipe_transfer *tex_trans;
94   void *tex_trans_map;
95   int tex_level, tex_z;
96
97   unsigned swizzle_r;
98   unsigned swizzle_g;
99   unsigned swizzle_b;
100   unsigned swizzle_a;
101   enum pipe_format format;
102
103   struct softpipe_tex_cached_tile *last_tile;  /**< most recently retrieved tile */
104};
105
106
107extern struct softpipe_tex_tile_cache *
108sp_create_tex_tile_cache( struct pipe_context *pipe );
109
110extern void
111sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
112
113extern void
114sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
115                                   struct pipe_sampler_view *view);
116
117void
118sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc);
119
120extern void
121sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
122
123
124
125extern const struct softpipe_tex_cached_tile *
126sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
127                        union tex_tile_address addr );
128
129static inline union tex_tile_address
130tex_tile_address( unsigned x,
131                  unsigned y,
132                  unsigned z,
133                  unsigned face,
134                  unsigned level )
135{
136   union tex_tile_address addr;
137
138   addr.value = 0;
139   addr.bits.x = x / TEX_TILE_SIZE;
140   addr.bits.y = y / TEX_TILE_SIZE;
141   addr.bits.z = z;
142   addr.bits.level = level;
143
144   return addr;
145}
146
147/* Quickly retrieve tile if it matches last lookup.
148 */
149static inline const struct softpipe_tex_cached_tile *
150sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
151                       union tex_tile_address addr )
152{
153   if (tc->last_tile->addr.value == addr.value)
154      return tc->last_tile;
155
156   return sp_find_cached_tile_tex( tc, addr );
157}
158
159
160#endif /* SP_TEX_TILE_CACHE_H */
161
162