1/**********************************************************
2 * Copyright 2008-2009 VMware, Inc.  All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26#ifndef SVGA_CONTEXT_H
27#define SVGA_CONTEXT_H
28
29
30#include "pipe/p_context.h"
31#include "pipe/p_defines.h"
32#include "pipe/p_state.h"
33
34#include "util/os_time.h"
35
36#include "util/u_blitter.h"
37#include "util/list.h"
38
39#include "tgsi/tgsi_scan.h"
40
41#include "svga_screen.h"
42#include "svga_state.h"
43#include "svga_winsys.h"
44#include "svga_hw_reg.h"
45#include "svga3d_shaderdefs.h"
46
47
48/** Non-GPU queries for gallium HUD */
49enum svga_hud {
50/* per-frame counters */
51   SVGA_QUERY_NUM_DRAW_CALLS = PIPE_QUERY_DRIVER_SPECIFIC,
52   SVGA_QUERY_NUM_FALLBACKS,
53   SVGA_QUERY_NUM_FLUSHES,
54   SVGA_QUERY_NUM_VALIDATIONS,
55   SVGA_QUERY_MAP_BUFFER_TIME,
56   SVGA_QUERY_NUM_BUFFERS_MAPPED,
57   SVGA_QUERY_NUM_TEXTURES_MAPPED,
58   SVGA_QUERY_NUM_BYTES_UPLOADED,
59   SVGA_QUERY_COMMAND_BUFFER_SIZE,
60   SVGA_QUERY_FLUSH_TIME,
61   SVGA_QUERY_SURFACE_WRITE_FLUSHES,
62   SVGA_QUERY_NUM_READBACKS,
63   SVGA_QUERY_NUM_RESOURCE_UPDATES,
64   SVGA_QUERY_NUM_BUFFER_UPLOADS,
65   SVGA_QUERY_NUM_CONST_BUF_UPDATES,
66   SVGA_QUERY_NUM_CONST_UPDATES,
67
68/* running total counters */
69   SVGA_QUERY_MEMORY_USED,
70   SVGA_QUERY_NUM_SHADERS,
71   SVGA_QUERY_NUM_RESOURCES,
72   SVGA_QUERY_NUM_STATE_OBJECTS,
73   SVGA_QUERY_NUM_SURFACE_VIEWS,
74   SVGA_QUERY_NUM_GENERATE_MIPMAP,
75   SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
76   SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
77
78/*SVGA_QUERY_MAX has to be last because it is size of an array*/
79   SVGA_QUERY_MAX
80};
81
82/**
83 * Maximum supported number of constant buffers per shader
84 */
85#define SVGA_MAX_CONST_BUFS 14
86
87/**
88 * Maximum constant buffer size that can be set in the
89 * DXSetSingleConstantBuffer command is
90 * DX10 constant buffer element count * 4 4-bytes components
91 */
92#define SVGA_MAX_CONST_BUF_SIZE (4096 * 4 * sizeof(int))
93
94#define CONST0_UPLOAD_ALIGNMENT 256
95
96struct draw_vertex_shader;
97struct draw_fragment_shader;
98struct svga_shader_variant;
99struct SVGACmdMemory;
100struct util_bitmask;
101
102
103struct svga_cache_context;
104struct svga_tracked_state;
105
106struct svga_blend_state {
107   unsigned need_white_fragments:1;
108   unsigned independent_blend_enable:1;
109   unsigned alpha_to_coverage:1;
110   unsigned alpha_to_one:1;
111   unsigned blend_color_alpha:1;  /**< set blend color to alpha value */
112
113   /** Per-render target state */
114   struct {
115      uint8_t writemask;
116
117      boolean blend_enable;
118      uint8_t srcblend;
119      uint8_t dstblend;
120      uint8_t blendeq;
121
122      boolean separate_alpha_blend_enable;
123      uint8_t srcblend_alpha;
124      uint8_t dstblend_alpha;
125      uint8_t blendeq_alpha;
126   } rt[PIPE_MAX_COLOR_BUFS];
127
128   SVGA3dBlendStateId id;  /**< vgpu10 */
129};
130
131struct svga_depth_stencil_state {
132   unsigned zfunc:8;
133   unsigned zenable:1;
134   unsigned zwriteenable:1;
135
136   unsigned alphatestenable:1;
137   unsigned alphafunc:8;
138
139   struct {
140      unsigned enabled:1;
141      unsigned func:8;
142      unsigned fail:8;
143      unsigned zfail:8;
144      unsigned pass:8;
145   } stencil[2];
146
147   /* SVGA3D has one ref/mask/writemask triple shared between front &
148    * back face stencil.  We really need two:
149    */
150   unsigned stencil_mask:8;
151   unsigned stencil_writemask:8;
152
153   float    alpharef;
154
155   SVGA3dDepthStencilStateId id;  /**< vgpu10 */
156};
157
158#define SVGA_UNFILLED_DISABLE 0
159#define SVGA_UNFILLED_LINE    1
160#define SVGA_UNFILLED_POINT   2
161
162#define SVGA_PIPELINE_FLAG_POINTS   (1<<PIPE_PRIM_POINTS)
163#define SVGA_PIPELINE_FLAG_LINES    (1<<PIPE_PRIM_LINES)
164#define SVGA_PIPELINE_FLAG_TRIS     (1<<PIPE_PRIM_TRIANGLES)
165
166struct svga_rasterizer_state {
167   struct pipe_rasterizer_state templ; /* needed for draw module */
168
169   unsigned shademode:8;
170   unsigned cullmode:8;
171   unsigned scissortestenable:1;
172   unsigned multisampleantialias:1;
173   unsigned antialiasedlineenable:1;
174   unsigned lastpixel:1;
175   unsigned pointsprite:1;
176
177   unsigned linepattern;
178
179   float slopescaledepthbias;
180   float depthbias;
181   float pointsize;
182   float linewidth;
183
184   unsigned hw_fillmode:2;         /* PIPE_POLYGON_MODE_x */
185
186   /** Which prims do we need help for?  Bitmask of (1 << PIPE_PRIM_x) flags */
187   unsigned need_pipeline:16;
188
189   SVGA3dRasterizerStateId id;    /**< vgpu10 */
190
191   /** For debugging: */
192   const char* need_pipeline_tris_str;
193   const char* need_pipeline_lines_str;
194   const char* need_pipeline_points_str;
195};
196
197struct svga_sampler_state {
198   unsigned mipfilter;
199   unsigned magfilter;
200   unsigned minfilter;
201   unsigned aniso_level;
202   float lod_bias;
203   unsigned addressu;
204   unsigned addressv;
205   unsigned addressw;
206   unsigned bordercolor;
207   unsigned normalized_coords:1;
208   unsigned compare_mode:1;
209   unsigned compare_func:3;
210
211   unsigned min_lod;
212   unsigned view_min_lod;
213   unsigned view_max_lod;
214
215   SVGA3dSamplerId id[2];
216};
217
218
219struct svga_pipe_sampler_view
220{
221   struct pipe_sampler_view base;
222
223   SVGA3dShaderResourceViewId id;
224};
225
226
227static inline struct svga_pipe_sampler_view *
228svga_pipe_sampler_view(struct pipe_sampler_view *v)
229{
230   return (struct svga_pipe_sampler_view *) v;
231}
232
233
234struct svga_velems_state {
235   unsigned count;
236   struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
237   SVGA3dDeclType decl_type[PIPE_MAX_ATTRIBS]; /**< vertex attrib formats */
238
239   /** Bitmasks indicating which attributes need format conversion */
240   unsigned adjust_attrib_range;     /**< range adjustment */
241   unsigned attrib_is_pure_int;      /**< pure int */
242   unsigned adjust_attrib_w_1;       /**< set w = 1 */
243   unsigned adjust_attrib_itof;      /**< int->float */
244   unsigned adjust_attrib_utof;      /**< uint->float */
245   unsigned attrib_is_bgra;          /**< R / B swizzling */
246   unsigned attrib_puint_to_snorm;   /**< 10_10_10_2 packed uint -> snorm */
247   unsigned attrib_puint_to_uscaled; /**< 10_10_10_2 packed uint -> uscaled */
248   unsigned attrib_puint_to_sscaled; /**< 10_10_10_2 packed uint -> sscaled */
249
250   boolean need_swvfetch;
251
252   SVGA3dElementLayoutId id; /**< VGPU10 */
253};
254
255
256/* Use to calculate differences between state emitted to hardware and
257 * current driver-calculated state.
258 */
259struct svga_state
260{
261   const struct svga_blend_state *blend;
262   const struct svga_depth_stencil_state *depth;
263   const struct svga_rasterizer_state *rast;
264   const struct svga_sampler_state *sampler[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
265   const struct svga_velems_state *velems;
266
267   struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS]; /* or texture ID's? */
268   struct svga_fragment_shader *fs;
269   struct svga_vertex_shader *vs;
270   struct svga_geometry_shader *user_gs; /* user-specified GS */
271   struct svga_geometry_shader *gs;      /* derived GS */
272
273   struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
274   /** Constant buffers for each shader.
275    * The size should probably always match with that of
276    * svga_shader_emitter_v10.num_shader_consts.
277    */
278   struct pipe_constant_buffer constbufs[PIPE_SHADER_TYPES][SVGA_MAX_CONST_BUFS];
279
280   struct pipe_framebuffer_state framebuffer;
281   float depthscale;
282
283   /* Hack to limit the number of different render targets between
284    * flushes.  Helps avoid blowing out our surface cache in EXA.
285    */
286   int nr_fbs;
287
288   struct pipe_poly_stipple poly_stipple;
289   struct pipe_scissor_state scissor;
290   struct pipe_blend_color blend_color;
291   struct pipe_stencil_ref stencil_ref;
292   struct pipe_clip_state clip;
293   struct pipe_viewport_state viewport;
294
295   unsigned num_samplers[PIPE_SHADER_TYPES];
296   unsigned num_sampler_views[PIPE_SHADER_TYPES];
297   unsigned num_vertex_buffers;
298   enum pipe_prim_type reduced_prim;
299
300   struct {
301      unsigned flag_1d;
302      unsigned flag_srgb;
303   } tex_flags;
304
305   unsigned sample_mask;
306};
307
308struct svga_prescale {
309   float translate[4];
310   float scale[4];
311   boolean enabled;
312};
313
314
315/* Updated by calling svga_update_state( SVGA_STATE_HW_CLEAR )
316 */
317struct svga_hw_clear_state
318{
319   SVGA3dRect viewport;
320
321   struct {
322      float zmin, zmax;
323   } depthrange;
324
325   struct pipe_framebuffer_state framebuffer;
326   struct svga_prescale prescale;
327
328   /* VGPU10 state */
329   unsigned num_rendertargets;
330   struct pipe_surface *rtv[SVGA3D_MAX_RENDER_TARGETS];
331   struct pipe_surface *dsv;
332};
333
334struct svga_hw_view_state
335{
336   struct pipe_resource *texture;
337   struct svga_sampler_view *v;
338   unsigned min_lod;
339   unsigned max_lod;
340   boolean dirty;
341};
342
343/* Updated by calling svga_update_state( SVGA_STATE_HW_DRAW )
344 */
345struct svga_hw_draw_state
346{
347   /** VGPU9 rasterization state */
348   unsigned rs[SVGA3D_RS_MAX];
349   /** VGPU9 texture sampler and bindings state */
350   unsigned ts[SVGA3D_PIXEL_SAMPLERREG_MAX][SVGA3D_TS_MAX];
351
352   /** VGPU9 texture views */
353   unsigned num_views;
354   unsigned num_backed_views; /* views with backing copy of texture */
355   struct svga_hw_view_state views[PIPE_MAX_SAMPLERS];
356
357   /** VGPU9 constant buffer values */
358   float cb[PIPE_SHADER_TYPES][SVGA3D_CONSTREG_MAX][4];
359
360   /** Currently bound shaders */
361   struct svga_shader_variant *fs;
362   struct svga_shader_variant *vs;
363   struct svga_shader_variant *gs;
364
365   /** Currently bound constant buffer, per shader stage */
366   struct pipe_resource *constbuf[PIPE_SHADER_TYPES];
367
368   /** Bitmask of enabled constant buffers */
369   unsigned enabled_constbufs[PIPE_SHADER_TYPES];
370
371   /**
372    * These are used to reduce the number of times we call u_upload_unmap()
373    * while updating the zero-th/default VGPU10 constant buffer.
374    */
375   struct pipe_resource *const0_buffer;
376   struct svga_winsys_surface *const0_handle;
377
378   /** VGPU10 HW state (used to prevent emitting redundant state) */
379   SVGA3dDepthStencilStateId depth_stencil_id;
380   unsigned stencil_ref;
381   SVGA3dBlendStateId blend_id;
382   float blend_factor[4];
383   unsigned blend_sample_mask;
384   SVGA3dRasterizerStateId rasterizer_id;
385   SVGA3dElementLayoutId layout_id;
386   SVGA3dPrimitiveType topology;
387
388   /** Vertex buffer state */
389   SVGA3dVertexBuffer vbuffer_attrs[PIPE_MAX_ATTRIBS];
390   struct pipe_resource *vbuffers[PIPE_MAX_ATTRIBS];
391   unsigned num_vbuffers;
392
393   struct pipe_resource *ib;  /**< index buffer for drawing */
394   SVGA3dSurfaceFormat ib_format;
395   unsigned ib_offset;
396
397   unsigned num_samplers[PIPE_SHADER_TYPES];
398   SVGA3dSamplerId samplers[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
399
400   unsigned num_sampler_views[PIPE_SHADER_TYPES];
401   struct pipe_sampler_view
402      *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
403
404   /* used for rebinding */
405   unsigned default_constbuf_size[PIPE_SHADER_TYPES];
406
407   boolean rasterizer_discard; /* set if rasterization is disabled */
408   boolean has_backed_views;   /* set if any of the rtv/dsv is a backed surface view */
409};
410
411
412/* Updated by calling svga_update_state( SVGA_STATE_NEED_SWTNL )
413 */
414struct svga_sw_state
415{
416   /* which parts we need */
417   boolean need_swvfetch;
418   boolean need_pipeline;
419   boolean need_swtnl;
420
421   /* Flag to make sure that need sw is on while
422    * updating state within a swtnl call.
423    */
424   boolean in_swtnl_draw;
425};
426
427
428/* Queue some state updates (like rss) and submit them to hardware in
429 * a single packet.
430 */
431struct svga_hw_queue;
432
433struct svga_query;
434struct svga_qmem_alloc_entry;
435
436struct svga_context
437{
438   struct pipe_context pipe;
439   struct svga_winsys_context *swc;
440   struct blitter_context *blitter;
441   struct u_upload_mgr *const0_upload;
442   struct u_upload_mgr *tex_upload;
443
444   struct {
445      boolean no_swtnl;
446      boolean force_swtnl;
447      boolean use_min_mipmap;
448
449      /* incremented for each shader */
450      unsigned shader_id;
451
452      boolean no_line_width;
453      boolean force_hw_line_stipple;
454
455      /** To report perf/conformance/etc issues to the state tracker */
456      struct pipe_debug_callback callback;
457   } debug;
458
459   struct {
460      struct draw_context *draw;
461      struct vbuf_render *backend;
462      unsigned hw_prim;
463      boolean new_vbuf;
464      boolean new_vdecl;
465   } swtnl;
466
467   /* Bitmask of blend state objects IDs */
468   struct util_bitmask *blend_object_id_bm;
469
470   /* Bitmask of depth/stencil state objects IDs */
471   struct util_bitmask *ds_object_id_bm;
472
473   /* Bitmaks of input element object IDs */
474   struct util_bitmask *input_element_object_id_bm;
475
476   /* Bitmask of rasterizer object IDs */
477   struct util_bitmask *rast_object_id_bm;
478
479   /* Bitmask of sampler state objects IDs */
480   struct util_bitmask *sampler_object_id_bm;
481
482   /* Bitmask of sampler view IDs */
483   struct util_bitmask *sampler_view_id_bm;
484
485   /* Bitmask of used shader IDs */
486   struct util_bitmask *shader_id_bm;
487
488   /* Bitmask of used surface view IDs */
489   struct util_bitmask *surface_view_id_bm;
490
491   /* Bitmask of used stream output IDs */
492   struct util_bitmask *stream_output_id_bm;
493
494   /* Bitmask of used query IDs */
495   struct util_bitmask *query_id_bm;
496
497   struct {
498      unsigned dirty[SVGA_STATE_MAX];
499
500      /** bitmasks of which const buffers are changed */
501      unsigned dirty_constbufs[PIPE_SHADER_TYPES];
502
503      unsigned texture_timestamp;
504
505      struct svga_sw_state          sw;
506      struct svga_hw_draw_state     hw_draw;
507      struct svga_hw_clear_state    hw_clear;
508   } state;
509
510   struct svga_state curr;      /* state from the state tracker */
511   unsigned dirty;              /* statechanges since last update_state() */
512
513   union {
514      struct {
515         unsigned rendertargets:1;
516         unsigned texture_samplers:1;
517         unsigned constbufs:1;
518         unsigned vs:1;
519         unsigned fs:1;
520         unsigned gs:1;
521         unsigned query:1;
522      } flags;
523      unsigned val;
524   } rebind;
525
526   struct svga_hwtnl *hwtnl;
527
528   /** Queries states */
529   struct svga_winsys_gb_query *gb_query;     /**< gb query object, one per context */
530   unsigned gb_query_len;                     /**< gb query object size */
531   struct util_bitmask *gb_query_alloc_mask;  /**< gb query object allocation mask */
532   struct svga_qmem_alloc_entry *gb_query_map[SVGA_QUERY_MAX];
533                                              /**< query mem block mapping */
534   struct svga_query *sq[SVGA_QUERY_MAX];     /**< queries currently in progress */
535
536   /** List of buffers with queued transfers */
537   struct list_head dirty_buffers;
538
539   /** performance / info queries for HUD */
540   struct {
541      uint64_t num_draw_calls;          /**< SVGA_QUERY_DRAW_CALLS */
542      uint64_t num_fallbacks;           /**< SVGA_QUERY_NUM_FALLBACKS */
543      uint64_t num_flushes;             /**< SVGA_QUERY_NUM_FLUSHES */
544      uint64_t num_validations;         /**< SVGA_QUERY_NUM_VALIDATIONS */
545      uint64_t map_buffer_time;         /**< SVGA_QUERY_MAP_BUFFER_TIME */
546      uint64_t num_buffers_mapped;      /**< SVGA_QUERY_NUM_BUFFERS_MAPPED */
547      uint64_t num_textures_mapped;     /**< SVGA_QUERY_NUM_TEXTURES_MAPPED */
548      uint64_t command_buffer_size;     /**< SVGA_QUERY_COMMAND_BUFFER_SIZE */
549      uint64_t flush_time;              /**< SVGA_QUERY_FLUSH_TIME */
550      uint64_t surface_write_flushes;   /**< SVGA_QUERY_SURFACE_WRITE_FLUSHES */
551      uint64_t num_readbacks;           /**< SVGA_QUERY_NUM_READBACKS */
552      uint64_t num_resource_updates;    /**< SVGA_QUERY_NUM_RESOURCE_UPDATES */
553      uint64_t num_buffer_uploads;      /**< SVGA_QUERY_NUM_BUFFER_UPLOADS */
554      uint64_t num_const_buf_updates;   /**< SVGA_QUERY_NUM_CONST_BUF_UPDATES */
555      uint64_t num_const_updates;       /**< SVGA_QUERY_NUM_CONST_UPDATES */
556      uint64_t num_shaders;             /**< SVGA_QUERY_NUM_SHADERS */
557
558      /** The following are summed for SVGA_QUERY_NUM_STATE_OBJECTS */
559      uint64_t num_blend_objects;
560      uint64_t num_depthstencil_objects;
561      uint64_t num_rasterizer_objects;
562      uint64_t num_sampler_objects;
563      uint64_t num_samplerview_objects;
564      uint64_t num_vertexelement_objects;
565
566      uint64_t num_surface_views;       /**< SVGA_QUERY_NUM_SURFACE_VIEWS */
567      uint64_t num_bytes_uploaded;      /**< SVGA_QUERY_NUM_BYTES_UPLOADED */
568      uint64_t num_generate_mipmap;     /**< SVGA_QUERY_NUM_GENERATE_MIPMAP */
569
570      boolean uses_time;                /**< os_time_get() calls needed? */
571   } hud;
572
573   /** The currently bound stream output targets */
574   unsigned num_so_targets;
575   struct svga_winsys_surface *so_surfaces[SVGA3D_DX_MAX_SOTARGETS];
576   struct pipe_stream_output_target *so_targets[SVGA3D_DX_MAX_SOTARGETS];
577   struct svga_stream_output *current_so;
578
579   /** A blend state with blending disabled, for falling back to when blending
580    * is illegal (e.g. an integer texture is bound)
581    */
582   struct svga_blend_state *noop_blend;
583
584   struct {
585      struct pipe_resource *texture;
586      struct svga_pipe_sampler_view *sampler_view;
587      void *sampler;
588   } polygon_stipple;
589
590   /** Alternate rasterizer states created for point sprite */
591   struct svga_rasterizer_state *rasterizer_no_cull[2];
592
593   /** Depth stencil state created to disable depth stencil test */
594   struct svga_depth_stencil_state *depthstencil_disable;
595
596   /** Current conditional rendering predicate */
597   struct {
598      SVGA3dQueryId query_id;
599      boolean cond;
600   } pred;
601
602   boolean render_condition;
603   boolean disable_rasterizer; /* Set if to disable rasterization */
604};
605
606/* A flag for each state_tracker state object:
607 */
608#define SVGA_NEW_BLEND               0x1
609#define SVGA_NEW_DEPTH_STENCIL_ALPHA 0x2
610#define SVGA_NEW_RAST                0x4
611#define SVGA_NEW_SAMPLER             0x8
612#define SVGA_NEW_TEXTURE             0x10
613#define SVGA_NEW_VBUFFER             0x20
614#define SVGA_NEW_VELEMENT            0x40
615#define SVGA_NEW_FS                  0x80
616#define SVGA_NEW_VS                  0x100
617#define SVGA_NEW_FS_CONST_BUFFER     0x200
618#define SVGA_NEW_VS_CONST_BUFFER     0x400
619#define SVGA_NEW_FRAME_BUFFER        0x800
620#define SVGA_NEW_STIPPLE             0x1000
621#define SVGA_NEW_SCISSOR             0x2000
622#define SVGA_NEW_BLEND_COLOR         0x4000
623#define SVGA_NEW_CLIP                0x8000
624#define SVGA_NEW_VIEWPORT            0x10000
625#define SVGA_NEW_PRESCALE            0x20000
626#define SVGA_NEW_REDUCED_PRIMITIVE   0x40000
627#define SVGA_NEW_TEXTURE_BINDING     0x80000
628#define SVGA_NEW_NEED_PIPELINE       0x100000
629#define SVGA_NEW_NEED_SWVFETCH       0x200000
630#define SVGA_NEW_NEED_SWTNL          0x400000
631#define SVGA_NEW_FS_VARIANT          0x800000
632#define SVGA_NEW_VS_VARIANT          0x1000000
633#define SVGA_NEW_TEXTURE_FLAGS       0x4000000
634#define SVGA_NEW_STENCIL_REF         0x8000000
635#define SVGA_NEW_GS                  0x10000000
636#define SVGA_NEW_GS_CONST_BUFFER     0x20000000
637#define SVGA_NEW_GS_VARIANT          0x40000000
638#define SVGA_NEW_TEXTURE_CONSTS      0x80000000
639
640
641void svga_init_state_functions( struct svga_context *svga );
642void svga_init_flush_functions( struct svga_context *svga );
643void svga_init_string_functions( struct svga_context *svga );
644void svga_init_blit_functions(struct svga_context *svga);
645
646void svga_init_blend_functions( struct svga_context *svga );
647void svga_init_depth_stencil_functions( struct svga_context *svga );
648void svga_init_misc_functions( struct svga_context *svga );
649void svga_init_rasterizer_functions( struct svga_context *svga );
650void svga_init_sampler_functions( struct svga_context *svga );
651void svga_init_fs_functions( struct svga_context *svga );
652void svga_init_vs_functions( struct svga_context *svga );
653void svga_init_gs_functions( struct svga_context *svga );
654void svga_init_vertex_functions( struct svga_context *svga );
655void svga_init_constbuffer_functions( struct svga_context *svga );
656void svga_init_draw_functions( struct svga_context *svga );
657void svga_init_query_functions( struct svga_context *svga );
658void svga_init_surface_functions(struct svga_context *svga);
659void svga_init_stream_output_functions( struct svga_context *svga );
660void svga_init_clear_functions( struct svga_context *svga );
661
662void svga_cleanup_vertex_state( struct svga_context *svga );
663void svga_cleanup_sampler_state( struct svga_context *svga );
664void svga_cleanup_tss_binding( struct svga_context *svga );
665void svga_cleanup_framebuffer( struct svga_context *svga );
666
667void svga_context_flush( struct svga_context *svga,
668                         struct pipe_fence_handle **pfence );
669
670void svga_context_finish(struct svga_context *svga);
671
672void svga_hwtnl_flush_retry( struct svga_context *svga );
673void svga_hwtnl_flush_buffer( struct svga_context *svga,
674                              struct pipe_resource *buffer );
675
676void svga_surfaces_flush(struct svga_context *svga);
677
678struct pipe_context *
679svga_context_create(struct pipe_screen *screen,
680                    void *priv, unsigned flags);
681
682void svga_toggle_render_condition(struct svga_context *svga,
683                                  boolean render_condition_enabled,
684                                  boolean on);
685
686/***********************************************************************
687 * Inline conversion functions.  These are better-typed than the
688 * macros used previously:
689 */
690static inline struct svga_context *
691svga_context( struct pipe_context *pipe )
692{
693   return (struct svga_context *)pipe;
694}
695
696static inline struct svga_winsys_screen *
697svga_sws(struct svga_context *svga)
698{
699   return svga_screen(svga->pipe.screen)->sws;
700}
701
702static inline boolean
703svga_have_gb_objects(const struct svga_context *svga)
704{
705   return svga_screen(svga->pipe.screen)->sws->have_gb_objects;
706}
707
708static inline boolean
709svga_have_gb_dma(const struct svga_context *svga)
710{
711   return svga_screen(svga->pipe.screen)->sws->have_gb_dma;
712}
713
714static inline boolean
715svga_have_vgpu10(const struct svga_context *svga)
716{
717   return svga_screen(svga->pipe.screen)->sws->have_vgpu10;
718}
719
720static inline boolean
721svga_have_sm4_1(const struct svga_context *svga)
722{
723   return svga_screen(svga->pipe.screen)->sws->have_sm4_1;
724}
725
726static inline boolean
727svga_need_to_rebind_resources(const struct svga_context *svga)
728{
729   return svga_screen(svga->pipe.screen)->sws->need_to_rebind_resources;
730}
731
732static inline boolean
733svga_rects_equal(const SVGA3dRect *r1, const SVGA3dRect *r2)
734{
735   return memcmp(r1, r2, sizeof(*r1)) == 0;
736}
737
738/**
739 * If the Gallium HUD is enabled, this will return the current time.
740 * Otherwise, just return zero.
741 */
742static inline int64_t
743svga_get_time(struct svga_context *svga)
744{
745   return svga->hud.uses_time ? os_time_get() : 0;
746}
747
748
749#endif
750