1b8e80941Smrg/*
2b8e80941Smrg * Copyright © 2014-2018 NVIDIA Corporation
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the next
12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the
13b8e80941Smrg * Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21b8e80941Smrg * IN THE SOFTWARE.
22b8e80941Smrg */
23b8e80941Smrg
24b8e80941Smrg#include <inttypes.h>
25b8e80941Smrg#include <stdlib.h>
26b8e80941Smrg
27b8e80941Smrg#include "util/u_debug.h"
28b8e80941Smrg#include "util/u_inlines.h"
29b8e80941Smrg#include "util/u_upload_mgr.h"
30b8e80941Smrg
31b8e80941Smrg#include "tegra_context.h"
32b8e80941Smrg#include "tegra_resource.h"
33b8e80941Smrg#include "tegra_screen.h"
34b8e80941Smrg
35b8e80941Smrgstatic void
36b8e80941Smrgtegra_destroy(struct pipe_context *pcontext)
37b8e80941Smrg{
38b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
39b8e80941Smrg
40b8e80941Smrg   if (context->base.stream_uploader)
41b8e80941Smrg      u_upload_destroy(context->base.stream_uploader);
42b8e80941Smrg
43b8e80941Smrg   context->gpu->destroy(context->gpu);
44b8e80941Smrg   free(context);
45b8e80941Smrg}
46b8e80941Smrg
47b8e80941Smrgstatic void
48b8e80941Smrgtegra_draw_vbo(struct pipe_context *pcontext,
49b8e80941Smrg               const struct pipe_draw_info *pinfo)
50b8e80941Smrg{
51b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
52b8e80941Smrg   struct pipe_draw_indirect_info indirect;
53b8e80941Smrg   struct pipe_draw_info info;
54b8e80941Smrg
55b8e80941Smrg   if (pinfo && (pinfo->indirect || pinfo->index_size)) {
56b8e80941Smrg      memcpy(&info, pinfo, sizeof(info));
57b8e80941Smrg
58b8e80941Smrg      if (pinfo->indirect) {
59b8e80941Smrg         memcpy(&indirect, pinfo->indirect, sizeof(indirect));
60b8e80941Smrg         indirect.buffer = tegra_resource_unwrap(info.indirect->buffer);
61b8e80941Smrg         info.indirect = &indirect;
62b8e80941Smrg      }
63b8e80941Smrg
64b8e80941Smrg      if (pinfo->index_size && !pinfo->has_user_indices)
65b8e80941Smrg         info.index.resource = tegra_resource_unwrap(info.index.resource);
66b8e80941Smrg
67b8e80941Smrg      pinfo = &info;
68b8e80941Smrg   }
69b8e80941Smrg
70b8e80941Smrg   context->gpu->draw_vbo(context->gpu, pinfo);
71b8e80941Smrg}
72b8e80941Smrg
73b8e80941Smrgstatic void
74b8e80941Smrgtegra_render_condition(struct pipe_context *pcontext,
75b8e80941Smrg                       struct pipe_query *query,
76b8e80941Smrg                       boolean condition,
77b8e80941Smrg                       unsigned int mode)
78b8e80941Smrg{
79b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
80b8e80941Smrg
81b8e80941Smrg   context->gpu->render_condition(context->gpu, query, condition, mode);
82b8e80941Smrg}
83b8e80941Smrg
84b8e80941Smrgstatic struct pipe_query *
85b8e80941Smrgtegra_create_query(struct pipe_context *pcontext, unsigned int query_type,
86b8e80941Smrg                   unsigned int index)
87b8e80941Smrg{
88b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
89b8e80941Smrg
90b8e80941Smrg   return context->gpu->create_query(context->gpu, query_type, index);
91b8e80941Smrg}
92b8e80941Smrg
93b8e80941Smrgstatic struct pipe_query *
94b8e80941Smrgtegra_create_batch_query(struct pipe_context *pcontext,
95b8e80941Smrg                         unsigned int num_queries,
96b8e80941Smrg                         unsigned int *queries)
97b8e80941Smrg{
98b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
99b8e80941Smrg
100b8e80941Smrg   return context->gpu->create_batch_query(context->gpu, num_queries,
101b8e80941Smrg                                           queries);
102b8e80941Smrg}
103b8e80941Smrg
104b8e80941Smrgstatic void
105b8e80941Smrgtegra_destroy_query(struct pipe_context *pcontext, struct pipe_query *query)
106b8e80941Smrg{
107b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
108b8e80941Smrg
109b8e80941Smrg   context->gpu->destroy_query(context->gpu, query);
110b8e80941Smrg}
111b8e80941Smrg
112b8e80941Smrgstatic boolean
113b8e80941Smrgtegra_begin_query(struct pipe_context *pcontext, struct pipe_query *query)
114b8e80941Smrg{
115b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
116b8e80941Smrg
117b8e80941Smrg   return context->gpu->begin_query(context->gpu, query);
118b8e80941Smrg}
119b8e80941Smrg
120b8e80941Smrgstatic bool
121b8e80941Smrgtegra_end_query(struct pipe_context *pcontext, struct pipe_query *query)
122b8e80941Smrg{
123b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
124b8e80941Smrg
125b8e80941Smrg   return context->gpu->end_query(context->gpu, query);
126b8e80941Smrg}
127b8e80941Smrg
128b8e80941Smrgstatic boolean
129b8e80941Smrgtegra_get_query_result(struct pipe_context *pcontext,
130b8e80941Smrg                       struct pipe_query *query,
131b8e80941Smrg                       boolean wait,
132b8e80941Smrg                       union pipe_query_result *result)
133b8e80941Smrg{
134b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
135b8e80941Smrg
136b8e80941Smrg   return context->gpu->get_query_result(context->gpu, query, wait,
137b8e80941Smrg                     result);
138b8e80941Smrg}
139b8e80941Smrg
140b8e80941Smrgstatic void
141b8e80941Smrgtegra_get_query_result_resource(struct pipe_context *pcontext,
142b8e80941Smrg                                struct pipe_query *query,
143b8e80941Smrg                                boolean wait,
144b8e80941Smrg                                enum pipe_query_value_type result_type,
145b8e80941Smrg                                int index,
146b8e80941Smrg                                struct pipe_resource *resource,
147b8e80941Smrg                                unsigned int offset)
148b8e80941Smrg{
149b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
150b8e80941Smrg
151b8e80941Smrg   context->gpu->get_query_result_resource(context->gpu, query, wait,
152b8e80941Smrg                                           result_type, index, resource,
153b8e80941Smrg                                           offset);
154b8e80941Smrg}
155b8e80941Smrg
156b8e80941Smrgstatic void
157b8e80941Smrgtegra_set_active_query_state(struct pipe_context *pcontext, boolean enable)
158b8e80941Smrg{
159b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
160b8e80941Smrg
161b8e80941Smrg   context->gpu->set_active_query_state(context->gpu, enable);
162b8e80941Smrg}
163b8e80941Smrg
164b8e80941Smrgstatic void *
165b8e80941Smrgtegra_create_blend_state(struct pipe_context *pcontext,
166b8e80941Smrg                         const struct pipe_blend_state *cso)
167b8e80941Smrg{
168b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
169b8e80941Smrg
170b8e80941Smrg   return context->gpu->create_blend_state(context->gpu, cso);
171b8e80941Smrg}
172b8e80941Smrg
173b8e80941Smrgstatic void
174b8e80941Smrgtegra_bind_blend_state(struct pipe_context *pcontext, void *so)
175b8e80941Smrg{
176b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
177b8e80941Smrg
178b8e80941Smrg   context->gpu->bind_blend_state(context->gpu, so);
179b8e80941Smrg}
180b8e80941Smrg
181b8e80941Smrgstatic void
182b8e80941Smrgtegra_delete_blend_state(struct pipe_context *pcontext, void *so)
183b8e80941Smrg{
184b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
185b8e80941Smrg
186b8e80941Smrg   context->gpu->delete_blend_state(context->gpu, so);
187b8e80941Smrg}
188b8e80941Smrg
189b8e80941Smrgstatic void *
190b8e80941Smrgtegra_create_sampler_state(struct pipe_context *pcontext,
191b8e80941Smrg                           const struct pipe_sampler_state *cso)
192b8e80941Smrg{
193b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
194b8e80941Smrg
195b8e80941Smrg   return context->gpu->create_sampler_state(context->gpu, cso);
196b8e80941Smrg}
197b8e80941Smrg
198b8e80941Smrgstatic void
199b8e80941Smrgtegra_bind_sampler_states(struct pipe_context *pcontext, unsigned shader,
200b8e80941Smrg                          unsigned start_slot, unsigned num_samplers,
201b8e80941Smrg                          void **samplers)
202b8e80941Smrg{
203b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
204b8e80941Smrg
205b8e80941Smrg   context->gpu->bind_sampler_states(context->gpu, shader, start_slot,
206b8e80941Smrg                                     num_samplers, samplers);
207b8e80941Smrg}
208b8e80941Smrg
209b8e80941Smrgstatic void
210b8e80941Smrgtegra_delete_sampler_state(struct pipe_context *pcontext, void *so)
211b8e80941Smrg{
212b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
213b8e80941Smrg
214b8e80941Smrg   context->gpu->delete_sampler_state(context->gpu, so);
215b8e80941Smrg}
216b8e80941Smrg
217b8e80941Smrgstatic void *
218b8e80941Smrgtegra_create_rasterizer_state(struct pipe_context *pcontext,
219b8e80941Smrg                              const struct pipe_rasterizer_state *cso)
220b8e80941Smrg{
221b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
222b8e80941Smrg
223b8e80941Smrg   return context->gpu->create_rasterizer_state(context->gpu, cso);
224b8e80941Smrg}
225b8e80941Smrg
226b8e80941Smrgstatic void
227b8e80941Smrgtegra_bind_rasterizer_state(struct pipe_context *pcontext, void *so)
228b8e80941Smrg{
229b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
230b8e80941Smrg
231b8e80941Smrg   context->gpu->bind_rasterizer_state(context->gpu, so);
232b8e80941Smrg}
233b8e80941Smrg
234b8e80941Smrgstatic void
235b8e80941Smrgtegra_delete_rasterizer_state(struct pipe_context *pcontext, void *so)
236b8e80941Smrg{
237b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
238b8e80941Smrg
239b8e80941Smrg   context->gpu->delete_rasterizer_state(context->gpu, so);
240b8e80941Smrg}
241b8e80941Smrg
242b8e80941Smrgstatic void *
243b8e80941Smrgtegra_create_depth_stencil_alpha_state(struct pipe_context *pcontext,
244b8e80941Smrg                                       const struct pipe_depth_stencil_alpha_state *cso)
245b8e80941Smrg{
246b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
247b8e80941Smrg
248b8e80941Smrg   return context->gpu->create_depth_stencil_alpha_state(context->gpu, cso);
249b8e80941Smrg}
250b8e80941Smrg
251b8e80941Smrgstatic void
252b8e80941Smrgtegra_bind_depth_stencil_alpha_state(struct pipe_context *pcontext, void *so)
253b8e80941Smrg{
254b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
255b8e80941Smrg
256b8e80941Smrg   context->gpu->bind_depth_stencil_alpha_state(context->gpu, so);
257b8e80941Smrg}
258b8e80941Smrg
259b8e80941Smrgstatic void
260b8e80941Smrgtegra_delete_depth_stencil_alpha_state(struct pipe_context *pcontext, void *so)
261b8e80941Smrg{
262b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
263b8e80941Smrg
264b8e80941Smrg   context->gpu->delete_depth_stencil_alpha_state(context->gpu, so);
265b8e80941Smrg}
266b8e80941Smrg
267b8e80941Smrgstatic void *
268b8e80941Smrgtegra_create_fs_state(struct pipe_context *pcontext,
269b8e80941Smrg                      const struct pipe_shader_state *cso)
270b8e80941Smrg{
271b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
272b8e80941Smrg
273b8e80941Smrg   return context->gpu->create_fs_state(context->gpu, cso);
274b8e80941Smrg}
275b8e80941Smrg
276b8e80941Smrgstatic void
277b8e80941Smrgtegra_bind_fs_state(struct pipe_context *pcontext, void *so)
278b8e80941Smrg{
279b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
280b8e80941Smrg
281b8e80941Smrg   context->gpu->bind_fs_state(context->gpu, so);
282b8e80941Smrg}
283b8e80941Smrg
284b8e80941Smrgstatic void
285b8e80941Smrgtegra_delete_fs_state(struct pipe_context *pcontext, void *so)
286b8e80941Smrg{
287b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
288b8e80941Smrg
289b8e80941Smrg   context->gpu->delete_fs_state(context->gpu, so);
290b8e80941Smrg}
291b8e80941Smrg
292b8e80941Smrgstatic void *
293b8e80941Smrgtegra_create_vs_state(struct pipe_context *pcontext,
294b8e80941Smrg                      const struct pipe_shader_state *cso)
295b8e80941Smrg{
296b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
297b8e80941Smrg
298b8e80941Smrg   return context->gpu->create_vs_state(context->gpu, cso);
299b8e80941Smrg}
300b8e80941Smrg
301b8e80941Smrgstatic void
302b8e80941Smrgtegra_bind_vs_state(struct pipe_context *pcontext, void *so)
303b8e80941Smrg{
304b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
305b8e80941Smrg
306b8e80941Smrg   context->gpu->bind_vs_state(context->gpu, so);
307b8e80941Smrg}
308b8e80941Smrg
309b8e80941Smrgstatic void
310b8e80941Smrgtegra_delete_vs_state(struct pipe_context *pcontext, void *so)
311b8e80941Smrg{
312b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
313b8e80941Smrg
314b8e80941Smrg   context->gpu->delete_vs_state(context->gpu, so);
315b8e80941Smrg}
316b8e80941Smrg
317b8e80941Smrgstatic void *
318b8e80941Smrgtegra_create_gs_state(struct pipe_context *pcontext,
319b8e80941Smrg                      const struct pipe_shader_state *cso)
320b8e80941Smrg{
321b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
322b8e80941Smrg
323b8e80941Smrg   return context->gpu->create_gs_state(context->gpu, cso);
324b8e80941Smrg}
325b8e80941Smrg
326b8e80941Smrgstatic void
327b8e80941Smrgtegra_bind_gs_state(struct pipe_context *pcontext, void *so)
328b8e80941Smrg{
329b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
330b8e80941Smrg
331b8e80941Smrg   context->gpu->bind_gs_state(context->gpu, so);
332b8e80941Smrg}
333b8e80941Smrg
334b8e80941Smrgstatic void
335b8e80941Smrgtegra_delete_gs_state(struct pipe_context *pcontext, void *so)
336b8e80941Smrg{
337b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
338b8e80941Smrg
339b8e80941Smrg   context->gpu->delete_gs_state(context->gpu, so);
340b8e80941Smrg}
341b8e80941Smrg
342b8e80941Smrgstatic void *
343b8e80941Smrgtegra_create_tcs_state(struct pipe_context *pcontext,
344b8e80941Smrg                       const struct pipe_shader_state *cso)
345b8e80941Smrg{
346b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
347b8e80941Smrg
348b8e80941Smrg   return context->gpu->create_tcs_state(context->gpu, cso);
349b8e80941Smrg}
350b8e80941Smrg
351b8e80941Smrgstatic void
352b8e80941Smrgtegra_bind_tcs_state(struct pipe_context *pcontext, void *so)
353b8e80941Smrg{
354b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
355b8e80941Smrg
356b8e80941Smrg   context->gpu->bind_tcs_state(context->gpu, so);
357b8e80941Smrg}
358b8e80941Smrg
359b8e80941Smrgstatic void
360b8e80941Smrgtegra_delete_tcs_state(struct pipe_context *pcontext, void *so)
361b8e80941Smrg{
362b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
363b8e80941Smrg
364b8e80941Smrg   context->gpu->delete_tcs_state(context->gpu, so);
365b8e80941Smrg}
366b8e80941Smrg
367b8e80941Smrgstatic void *
368b8e80941Smrgtegra_create_tes_state(struct pipe_context *pcontext,
369b8e80941Smrg                       const struct pipe_shader_state *cso)
370b8e80941Smrg{
371b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
372b8e80941Smrg
373b8e80941Smrg   return context->gpu->create_tes_state(context->gpu, cso);
374b8e80941Smrg}
375b8e80941Smrg
376b8e80941Smrgstatic void
377b8e80941Smrgtegra_bind_tes_state(struct pipe_context *pcontext, void *so)
378b8e80941Smrg{
379b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
380b8e80941Smrg
381b8e80941Smrg   context->gpu->bind_tes_state(context->gpu, so);
382b8e80941Smrg}
383b8e80941Smrg
384b8e80941Smrgstatic void
385b8e80941Smrgtegra_delete_tes_state(struct pipe_context *pcontext, void *so)
386b8e80941Smrg{
387b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
388b8e80941Smrg
389b8e80941Smrg   context->gpu->delete_tes_state(context->gpu, so);
390b8e80941Smrg}
391b8e80941Smrg
392b8e80941Smrgstatic void *
393b8e80941Smrgtegra_create_vertex_elements_state(struct pipe_context *pcontext,
394b8e80941Smrg                                   unsigned num_elements,
395b8e80941Smrg                                   const struct pipe_vertex_element *elements)
396b8e80941Smrg{
397b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
398b8e80941Smrg
399b8e80941Smrg   return context->gpu->create_vertex_elements_state(context->gpu,
400b8e80941Smrg                                                     num_elements,
401b8e80941Smrg                                                     elements);
402b8e80941Smrg}
403b8e80941Smrg
404b8e80941Smrgstatic void
405b8e80941Smrgtegra_bind_vertex_elements_state(struct pipe_context *pcontext, void *so)
406b8e80941Smrg{
407b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
408b8e80941Smrg
409b8e80941Smrg   context->gpu->bind_vertex_elements_state(context->gpu, so);
410b8e80941Smrg}
411b8e80941Smrg
412b8e80941Smrgstatic void
413b8e80941Smrgtegra_delete_vertex_elements_state(struct pipe_context *pcontext, void *so)
414b8e80941Smrg{
415b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
416b8e80941Smrg
417b8e80941Smrg   context->gpu->delete_vertex_elements_state(context->gpu, so);
418b8e80941Smrg}
419b8e80941Smrg
420b8e80941Smrgstatic void
421b8e80941Smrgtegra_set_blend_color(struct pipe_context *pcontext,
422b8e80941Smrg                      const struct pipe_blend_color *color)
423b8e80941Smrg{
424b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
425b8e80941Smrg
426b8e80941Smrg   context->gpu->set_blend_color(context->gpu, color);
427b8e80941Smrg}
428b8e80941Smrg
429b8e80941Smrgstatic void
430b8e80941Smrgtegra_set_stencil_ref(struct pipe_context *pcontext,
431b8e80941Smrg                      const struct pipe_stencil_ref *ref)
432b8e80941Smrg{
433b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
434b8e80941Smrg
435b8e80941Smrg   context->gpu->set_stencil_ref(context->gpu, ref);
436b8e80941Smrg}
437b8e80941Smrg
438b8e80941Smrgstatic void
439b8e80941Smrgtegra_set_sample_mask(struct pipe_context *pcontext, unsigned int mask)
440b8e80941Smrg{
441b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
442b8e80941Smrg
443b8e80941Smrg   context->gpu->set_sample_mask(context->gpu, mask);
444b8e80941Smrg}
445b8e80941Smrg
446b8e80941Smrgstatic void
447b8e80941Smrgtegra_set_min_samples(struct pipe_context *pcontext, unsigned int samples)
448b8e80941Smrg{
449b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
450b8e80941Smrg
451b8e80941Smrg   context->gpu->set_min_samples(context->gpu, samples);
452b8e80941Smrg}
453b8e80941Smrg
454b8e80941Smrgstatic void
455b8e80941Smrgtegra_set_clip_state(struct pipe_context *pcontext,
456b8e80941Smrg                     const struct pipe_clip_state *state)
457b8e80941Smrg{
458b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
459b8e80941Smrg
460b8e80941Smrg   context->gpu->set_clip_state(context->gpu, state);
461b8e80941Smrg}
462b8e80941Smrg
463b8e80941Smrgstatic void
464b8e80941Smrgtegra_set_constant_buffer(struct pipe_context *pcontext, unsigned int shader,
465b8e80941Smrg                          unsigned int index,
466b8e80941Smrg                          const struct pipe_constant_buffer *buf)
467b8e80941Smrg{
468b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
469b8e80941Smrg   struct pipe_constant_buffer buffer;
470b8e80941Smrg
471b8e80941Smrg   if (buf && buf->buffer) {
472b8e80941Smrg      memcpy(&buffer, buf, sizeof(buffer));
473b8e80941Smrg      buffer.buffer = tegra_resource_unwrap(buffer.buffer);
474b8e80941Smrg      buf = &buffer;
475b8e80941Smrg   }
476b8e80941Smrg
477b8e80941Smrg   context->gpu->set_constant_buffer(context->gpu, shader, index, buf);
478b8e80941Smrg}
479b8e80941Smrg
480b8e80941Smrgstatic void
481b8e80941Smrgtegra_set_framebuffer_state(struct pipe_context *pcontext,
482b8e80941Smrg                            const struct pipe_framebuffer_state *fb)
483b8e80941Smrg{
484b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
485b8e80941Smrg   struct pipe_framebuffer_state state;
486b8e80941Smrg   unsigned i;
487b8e80941Smrg
488b8e80941Smrg   if (fb) {
489b8e80941Smrg      memcpy(&state, fb, sizeof(state));
490b8e80941Smrg
491b8e80941Smrg      for (i = 0; i < fb->nr_cbufs; i++)
492b8e80941Smrg         state.cbufs[i] = tegra_surface_unwrap(fb->cbufs[i]);
493b8e80941Smrg
494b8e80941Smrg      while (i < PIPE_MAX_COLOR_BUFS)
495b8e80941Smrg         state.cbufs[i++] = NULL;
496b8e80941Smrg
497b8e80941Smrg      state.zsbuf = tegra_surface_unwrap(fb->zsbuf);
498b8e80941Smrg
499b8e80941Smrg      fb = &state;
500b8e80941Smrg   }
501b8e80941Smrg
502b8e80941Smrg   context->gpu->set_framebuffer_state(context->gpu, fb);
503b8e80941Smrg}
504b8e80941Smrg
505b8e80941Smrgstatic void
506b8e80941Smrgtegra_set_polygon_stipple(struct pipe_context *pcontext,
507b8e80941Smrg                          const struct pipe_poly_stipple *stipple)
508b8e80941Smrg{
509b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
510b8e80941Smrg
511b8e80941Smrg   context->gpu->set_polygon_stipple(context->gpu, stipple);
512b8e80941Smrg}
513b8e80941Smrg
514b8e80941Smrgstatic void
515b8e80941Smrgtegra_set_scissor_states(struct pipe_context *pcontext, unsigned start_slot,
516b8e80941Smrg                         unsigned num_scissors,
517b8e80941Smrg                         const struct pipe_scissor_state *scissors)
518b8e80941Smrg{
519b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
520b8e80941Smrg
521b8e80941Smrg   context->gpu->set_scissor_states(context->gpu, start_slot, num_scissors,
522b8e80941Smrg                                    scissors);
523b8e80941Smrg}
524b8e80941Smrg
525b8e80941Smrgstatic void
526b8e80941Smrgtegra_set_window_rectangles(struct pipe_context *pcontext, boolean include,
527b8e80941Smrg                            unsigned int num_rectangles,
528b8e80941Smrg                            const struct pipe_scissor_state *rectangles)
529b8e80941Smrg{
530b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
531b8e80941Smrg
532b8e80941Smrg   context->gpu->set_window_rectangles(context->gpu, include, num_rectangles,
533b8e80941Smrg                                       rectangles);
534b8e80941Smrg}
535b8e80941Smrg
536b8e80941Smrgstatic void
537b8e80941Smrgtegra_set_viewport_states(struct pipe_context *pcontext, unsigned start_slot,
538b8e80941Smrg                          unsigned num_viewports,
539b8e80941Smrg                          const struct pipe_viewport_state *viewports)
540b8e80941Smrg{
541b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
542b8e80941Smrg
543b8e80941Smrg   context->gpu->set_viewport_states(context->gpu, start_slot, num_viewports,
544b8e80941Smrg                                     viewports);
545b8e80941Smrg}
546b8e80941Smrg
547b8e80941Smrgstatic void
548b8e80941Smrgtegra_set_sampler_views(struct pipe_context *pcontext, unsigned shader,
549b8e80941Smrg                        unsigned start_slot, unsigned num_views,
550b8e80941Smrg                        struct pipe_sampler_view **pviews)
551b8e80941Smrg{
552b8e80941Smrg   struct pipe_sampler_view *views[PIPE_MAX_SHADER_SAMPLER_VIEWS];
553b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
554b8e80941Smrg   unsigned i;
555b8e80941Smrg
556b8e80941Smrg   for (i = 0; i < num_views; i++)
557b8e80941Smrg      views[i] = tegra_sampler_view_unwrap(pviews[i]);
558b8e80941Smrg
559b8e80941Smrg   context->gpu->set_sampler_views(context->gpu, shader, start_slot,
560b8e80941Smrg                                   num_views, views);
561b8e80941Smrg}
562b8e80941Smrg
563b8e80941Smrgstatic void
564b8e80941Smrgtegra_set_tess_state(struct pipe_context *pcontext,
565b8e80941Smrg                     const float default_outer_level[4],
566b8e80941Smrg                     const float default_inner_level[2])
567b8e80941Smrg{
568b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
569b8e80941Smrg
570b8e80941Smrg   context->gpu->set_tess_state(context->gpu, default_outer_level,
571b8e80941Smrg                                default_inner_level);
572b8e80941Smrg}
573b8e80941Smrg
574b8e80941Smrgstatic void
575b8e80941Smrgtegra_set_debug_callback(struct pipe_context *pcontext,
576b8e80941Smrg                         const struct pipe_debug_callback *callback)
577b8e80941Smrg{
578b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
579b8e80941Smrg
580b8e80941Smrg   context->gpu->set_debug_callback(context->gpu, callback);
581b8e80941Smrg}
582b8e80941Smrg
583b8e80941Smrgstatic void
584b8e80941Smrgtegra_set_shader_buffers(struct pipe_context *pcontext, unsigned int shader,
585b8e80941Smrg                         unsigned start, unsigned count,
586b8e80941Smrg                         const struct pipe_shader_buffer *buffers,
587b8e80941Smrg                         unsigned writable_bitmask)
588b8e80941Smrg{
589b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
590b8e80941Smrg
591b8e80941Smrg   context->gpu->set_shader_buffers(context->gpu, shader, start, count,
592b8e80941Smrg                                    buffers, writable_bitmask);
593b8e80941Smrg}
594b8e80941Smrg
595b8e80941Smrgstatic void
596b8e80941Smrgtegra_set_shader_images(struct pipe_context *pcontext, unsigned int shader,
597b8e80941Smrg                        unsigned start, unsigned count,
598b8e80941Smrg                        const struct pipe_image_view *images)
599b8e80941Smrg{
600b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
601b8e80941Smrg
602b8e80941Smrg   context->gpu->set_shader_images(context->gpu, shader, start, count,
603b8e80941Smrg                                   images);
604b8e80941Smrg}
605b8e80941Smrg
606b8e80941Smrgstatic void
607b8e80941Smrgtegra_set_vertex_buffers(struct pipe_context *pcontext, unsigned start_slot,
608b8e80941Smrg                         unsigned num_buffers,
609b8e80941Smrg                         const struct pipe_vertex_buffer *buffers)
610b8e80941Smrg{
611b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
612b8e80941Smrg   struct pipe_vertex_buffer buf[PIPE_MAX_SHADER_INPUTS];
613b8e80941Smrg   unsigned i;
614b8e80941Smrg
615b8e80941Smrg   if (num_buffers && buffers) {
616b8e80941Smrg      memcpy(buf, buffers, num_buffers * sizeof(struct pipe_vertex_buffer));
617b8e80941Smrg
618b8e80941Smrg      for (i = 0; i < num_buffers; i++) {
619b8e80941Smrg         if (!buf[i].is_user_buffer)
620b8e80941Smrg            buf[i].buffer.resource = tegra_resource_unwrap(buf[i].buffer.resource);
621b8e80941Smrg      }
622b8e80941Smrg
623b8e80941Smrg      buffers = buf;
624b8e80941Smrg   }
625b8e80941Smrg
626b8e80941Smrg   context->gpu->set_vertex_buffers(context->gpu, start_slot, num_buffers,
627b8e80941Smrg                                    buffers);
628b8e80941Smrg}
629b8e80941Smrg
630b8e80941Smrgstatic struct pipe_stream_output_target *
631b8e80941Smrgtegra_create_stream_output_target(struct pipe_context *pcontext,
632b8e80941Smrg                                  struct pipe_resource *presource,
633b8e80941Smrg                                  unsigned buffer_offset,
634b8e80941Smrg                                  unsigned buffer_size)
635b8e80941Smrg{
636b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
637b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
638b8e80941Smrg
639b8e80941Smrg   return context->gpu->create_stream_output_target(context->gpu,
640b8e80941Smrg                                                    resource->gpu,
641b8e80941Smrg                                                    buffer_offset,
642b8e80941Smrg                                                    buffer_size);
643b8e80941Smrg}
644b8e80941Smrg
645b8e80941Smrgstatic void
646b8e80941Smrgtegra_stream_output_target_destroy(struct pipe_context *pcontext,
647b8e80941Smrg                                   struct pipe_stream_output_target *target)
648b8e80941Smrg{
649b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
650b8e80941Smrg
651b8e80941Smrg   context->gpu->stream_output_target_destroy(context->gpu, target);
652b8e80941Smrg}
653b8e80941Smrg
654b8e80941Smrgstatic void
655b8e80941Smrgtegra_set_stream_output_targets(struct pipe_context *pcontext,
656b8e80941Smrg                                unsigned num_targets,
657b8e80941Smrg                                struct pipe_stream_output_target **targets,
658b8e80941Smrg                                const unsigned *offsets)
659b8e80941Smrg{
660b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
661b8e80941Smrg
662b8e80941Smrg   context->gpu->set_stream_output_targets(context->gpu, num_targets,
663b8e80941Smrg                                           targets, offsets);
664b8e80941Smrg}
665b8e80941Smrg
666b8e80941Smrgstatic void
667b8e80941Smrgtegra_resource_copy_region(struct pipe_context *pcontext,
668b8e80941Smrg                           struct pipe_resource *pdst,
669b8e80941Smrg                           unsigned int dst_level,
670b8e80941Smrg                           unsigned int dstx,
671b8e80941Smrg                           unsigned int dsty,
672b8e80941Smrg                           unsigned int dstz,
673b8e80941Smrg                           struct pipe_resource *psrc,
674b8e80941Smrg                           unsigned int src_level,
675b8e80941Smrg                           const struct pipe_box *src_box)
676b8e80941Smrg{
677b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
678b8e80941Smrg   struct tegra_resource *dst = to_tegra_resource(pdst);
679b8e80941Smrg   struct tegra_resource *src = to_tegra_resource(psrc);
680b8e80941Smrg
681b8e80941Smrg   context->gpu->resource_copy_region(context->gpu, dst->gpu, dst_level, dstx,
682b8e80941Smrg                                      dsty, dstz, src->gpu, src_level,
683b8e80941Smrg                                      src_box);
684b8e80941Smrg}
685b8e80941Smrg
686b8e80941Smrgstatic void
687b8e80941Smrgtegra_blit(struct pipe_context *pcontext, const struct pipe_blit_info *pinfo)
688b8e80941Smrg{
689b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
690b8e80941Smrg   struct pipe_blit_info info;
691b8e80941Smrg
692b8e80941Smrg   if (pinfo) {
693b8e80941Smrg      memcpy(&info, pinfo, sizeof(info));
694b8e80941Smrg      info.dst.resource = tegra_resource_unwrap(info.dst.resource);
695b8e80941Smrg      info.src.resource = tegra_resource_unwrap(info.src.resource);
696b8e80941Smrg      pinfo = &info;
697b8e80941Smrg   }
698b8e80941Smrg
699b8e80941Smrg   context->gpu->blit(context->gpu, pinfo);
700b8e80941Smrg}
701b8e80941Smrg
702b8e80941Smrgstatic void
703b8e80941Smrgtegra_clear(struct pipe_context *pcontext, unsigned buffers,
704b8e80941Smrg            const union pipe_color_union *color, double depth,
705b8e80941Smrg            unsigned stencil)
706b8e80941Smrg{
707b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
708b8e80941Smrg
709b8e80941Smrg   context->gpu->clear(context->gpu, buffers, color, depth, stencil);
710b8e80941Smrg}
711b8e80941Smrg
712b8e80941Smrgstatic void
713b8e80941Smrgtegra_clear_render_target(struct pipe_context *pcontext,
714b8e80941Smrg                          struct pipe_surface *pdst,
715b8e80941Smrg                          const union pipe_color_union *color,
716b8e80941Smrg                          unsigned int dstx,
717b8e80941Smrg                          unsigned int dsty,
718b8e80941Smrg                          unsigned int width,
719b8e80941Smrg                          unsigned int height,
720b8e80941Smrg                          bool render_condition)
721b8e80941Smrg{
722b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
723b8e80941Smrg   struct tegra_surface *dst = to_tegra_surface(pdst);
724b8e80941Smrg
725b8e80941Smrg   context->gpu->clear_render_target(context->gpu, dst->gpu, color, dstx,
726b8e80941Smrg                                     dsty, width, height, render_condition);
727b8e80941Smrg}
728b8e80941Smrg
729b8e80941Smrgstatic void
730b8e80941Smrgtegra_clear_depth_stencil(struct pipe_context *pcontext,
731b8e80941Smrg                          struct pipe_surface *pdst,
732b8e80941Smrg                          unsigned int flags,
733b8e80941Smrg                          double depth,
734b8e80941Smrg                          unsigned int stencil,
735b8e80941Smrg                          unsigned int dstx,
736b8e80941Smrg                          unsigned int dsty,
737b8e80941Smrg                          unsigned int width,
738b8e80941Smrg                          unsigned int height,
739b8e80941Smrg                          bool render_condition)
740b8e80941Smrg{
741b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
742b8e80941Smrg   struct tegra_surface *dst = to_tegra_surface(pdst);
743b8e80941Smrg
744b8e80941Smrg   context->gpu->clear_depth_stencil(context->gpu, dst->gpu, flags, depth,
745b8e80941Smrg                                     stencil, dstx, dsty, width, height,
746b8e80941Smrg                                     render_condition);
747b8e80941Smrg}
748b8e80941Smrg
749b8e80941Smrgstatic void
750b8e80941Smrgtegra_clear_texture(struct pipe_context *pcontext,
751b8e80941Smrg                    struct pipe_resource *presource,
752b8e80941Smrg                    unsigned int level,
753b8e80941Smrg                    const struct pipe_box *box,
754b8e80941Smrg                    const void *data)
755b8e80941Smrg{
756b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
757b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
758b8e80941Smrg
759b8e80941Smrg   context->gpu->clear_texture(context->gpu, resource->gpu, level, box, data);
760b8e80941Smrg}
761b8e80941Smrg
762b8e80941Smrgstatic void
763b8e80941Smrgtegra_clear_buffer(struct pipe_context *pcontext,
764b8e80941Smrg                   struct pipe_resource *presource,
765b8e80941Smrg                   unsigned int offset,
766b8e80941Smrg                   unsigned int size,
767b8e80941Smrg                   const void *value,
768b8e80941Smrg                   int value_size)
769b8e80941Smrg{
770b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
771b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
772b8e80941Smrg
773b8e80941Smrg   context->gpu->clear_buffer(context->gpu, resource->gpu, offset, size,
774b8e80941Smrg                              value, value_size);
775b8e80941Smrg}
776b8e80941Smrg
777b8e80941Smrgstatic void
778b8e80941Smrgtegra_flush(struct pipe_context *pcontext, struct pipe_fence_handle **fence,
779b8e80941Smrg            unsigned flags)
780b8e80941Smrg{
781b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
782b8e80941Smrg
783b8e80941Smrg   context->gpu->flush(context->gpu, fence, flags);
784b8e80941Smrg}
785b8e80941Smrg
786b8e80941Smrgstatic void
787b8e80941Smrgtegra_create_fence_fd(struct pipe_context *pcontext,
788b8e80941Smrg                      struct pipe_fence_handle **fence,
789b8e80941Smrg                      int fd, enum pipe_fd_type type)
790b8e80941Smrg{
791b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
792b8e80941Smrg
793b8e80941Smrg   assert(type == PIPE_FD_TYPE_NATIVE_SYNC);
794b8e80941Smrg   context->gpu->create_fence_fd(context->gpu, fence, fd, type);
795b8e80941Smrg}
796b8e80941Smrg
797b8e80941Smrgstatic void
798b8e80941Smrgtegra_fence_server_sync(struct pipe_context *pcontext,
799b8e80941Smrg                        struct pipe_fence_handle *fence)
800b8e80941Smrg{
801b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
802b8e80941Smrg
803b8e80941Smrg   context->gpu->fence_server_sync(context->gpu, fence);
804b8e80941Smrg}
805b8e80941Smrg
806b8e80941Smrgstatic struct pipe_sampler_view *
807b8e80941Smrgtegra_create_sampler_view(struct pipe_context *pcontext,
808b8e80941Smrg                          struct pipe_resource *presource,
809b8e80941Smrg                          const struct pipe_sampler_view *template)
810b8e80941Smrg{
811b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
812b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
813b8e80941Smrg   struct tegra_sampler_view *view;
814b8e80941Smrg
815b8e80941Smrg   view = calloc(1, sizeof(*view));
816b8e80941Smrg   if (!view)
817b8e80941Smrg      return NULL;
818b8e80941Smrg
819b8e80941Smrg   view->gpu = context->gpu->create_sampler_view(context->gpu, resource->gpu,
820b8e80941Smrg                                                 template);
821b8e80941Smrg   memcpy(&view->base, view->gpu, sizeof(*view->gpu));
822b8e80941Smrg   /* overwrite to prevent reference from being released */
823b8e80941Smrg   view->base.texture = NULL;
824b8e80941Smrg
825b8e80941Smrg   pipe_reference_init(&view->base.reference, 1);
826b8e80941Smrg   pipe_resource_reference(&view->base.texture, presource);
827b8e80941Smrg   view->base.context = pcontext;
828b8e80941Smrg
829b8e80941Smrg   return &view->base;
830b8e80941Smrg}
831b8e80941Smrg
832b8e80941Smrgstatic void
833b8e80941Smrgtegra_sampler_view_destroy(struct pipe_context *pcontext,
834b8e80941Smrg                           struct pipe_sampler_view *pview)
835b8e80941Smrg{
836b8e80941Smrg   struct tegra_sampler_view *view = to_tegra_sampler_view(pview);
837b8e80941Smrg
838b8e80941Smrg   pipe_resource_reference(&view->base.texture, NULL);
839b8e80941Smrg   pipe_sampler_view_reference(&view->gpu, NULL);
840b8e80941Smrg   free(view);
841b8e80941Smrg}
842b8e80941Smrg
843b8e80941Smrgstatic struct pipe_surface *
844b8e80941Smrgtegra_create_surface(struct pipe_context *pcontext,
845b8e80941Smrg                     struct pipe_resource *presource,
846b8e80941Smrg                     const struct pipe_surface *template)
847b8e80941Smrg{
848b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
849b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
850b8e80941Smrg   struct tegra_surface *surface;
851b8e80941Smrg
852b8e80941Smrg   surface = calloc(1, sizeof(*surface));
853b8e80941Smrg   if (!surface)
854b8e80941Smrg      return NULL;
855b8e80941Smrg
856b8e80941Smrg   surface->gpu = context->gpu->create_surface(context->gpu, resource->gpu,
857b8e80941Smrg                                               template);
858b8e80941Smrg   if (!surface->gpu) {
859b8e80941Smrg      free(surface);
860b8e80941Smrg      return NULL;
861b8e80941Smrg   }
862b8e80941Smrg
863b8e80941Smrg   memcpy(&surface->base, surface->gpu, sizeof(*surface->gpu));
864b8e80941Smrg   /* overwrite to prevent reference from being released */
865b8e80941Smrg   surface->base.texture = NULL;
866b8e80941Smrg
867b8e80941Smrg   pipe_reference_init(&surface->base.reference, 1);
868b8e80941Smrg   pipe_resource_reference(&surface->base.texture, presource);
869b8e80941Smrg   surface->base.context = &context->base;
870b8e80941Smrg
871b8e80941Smrg   return &surface->base;
872b8e80941Smrg}
873b8e80941Smrg
874b8e80941Smrgstatic void
875b8e80941Smrgtegra_surface_destroy(struct pipe_context *pcontext,
876b8e80941Smrg                      struct pipe_surface *psurface)
877b8e80941Smrg{
878b8e80941Smrg   struct tegra_surface *surface = to_tegra_surface(psurface);
879b8e80941Smrg
880b8e80941Smrg   pipe_resource_reference(&surface->base.texture, NULL);
881b8e80941Smrg   pipe_surface_reference(&surface->gpu, NULL);
882b8e80941Smrg   free(surface);
883b8e80941Smrg}
884b8e80941Smrg
885b8e80941Smrgstatic void *
886b8e80941Smrgtegra_transfer_map(struct pipe_context *pcontext,
887b8e80941Smrg                   struct pipe_resource *presource,
888b8e80941Smrg                   unsigned level, unsigned usage,
889b8e80941Smrg                   const struct pipe_box *box,
890b8e80941Smrg                   struct pipe_transfer **ptransfer)
891b8e80941Smrg{
892b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
893b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
894b8e80941Smrg   struct tegra_transfer *transfer;
895b8e80941Smrg
896b8e80941Smrg   transfer = calloc(1, sizeof(*transfer));
897b8e80941Smrg   if (!transfer)
898b8e80941Smrg      return NULL;
899b8e80941Smrg
900b8e80941Smrg   transfer->map = context->gpu->transfer_map(context->gpu, resource->gpu,
901b8e80941Smrg                                              level, usage, box,
902b8e80941Smrg                                              &transfer->gpu);
903b8e80941Smrg   memcpy(&transfer->base, transfer->gpu, sizeof(*transfer->gpu));
904b8e80941Smrg   transfer->base.resource = NULL;
905b8e80941Smrg   pipe_resource_reference(&transfer->base.resource, presource);
906b8e80941Smrg
907b8e80941Smrg   *ptransfer = &transfer->base;
908b8e80941Smrg
909b8e80941Smrg   return transfer->map;
910b8e80941Smrg}
911b8e80941Smrg
912b8e80941Smrgstatic void
913b8e80941Smrgtegra_transfer_flush_region(struct pipe_context *pcontext,
914b8e80941Smrg                            struct pipe_transfer *ptransfer,
915b8e80941Smrg                            const struct pipe_box *box)
916b8e80941Smrg{
917b8e80941Smrg   struct tegra_transfer *transfer = to_tegra_transfer(ptransfer);
918b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
919b8e80941Smrg
920b8e80941Smrg   context->gpu->transfer_flush_region(context->gpu, transfer->gpu, box);
921b8e80941Smrg}
922b8e80941Smrg
923b8e80941Smrgstatic void
924b8e80941Smrgtegra_transfer_unmap(struct pipe_context *pcontext,
925b8e80941Smrg                     struct pipe_transfer *ptransfer)
926b8e80941Smrg{
927b8e80941Smrg   struct tegra_transfer *transfer = to_tegra_transfer(ptransfer);
928b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
929b8e80941Smrg
930b8e80941Smrg   context->gpu->transfer_unmap(context->gpu, transfer->gpu);
931b8e80941Smrg   pipe_resource_reference(&transfer->base.resource, NULL);
932b8e80941Smrg   free(transfer);
933b8e80941Smrg}
934b8e80941Smrg
935b8e80941Smrgstatic void
936b8e80941Smrgtegra_buffer_subdata(struct pipe_context *pcontext,
937b8e80941Smrg                     struct pipe_resource *presource,
938b8e80941Smrg                     unsigned usage, unsigned offset,
939b8e80941Smrg                     unsigned size, const void *data)
940b8e80941Smrg{
941b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
942b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
943b8e80941Smrg
944b8e80941Smrg   context->gpu->buffer_subdata(context->gpu, resource->gpu, usage, offset,
945b8e80941Smrg                                size, data);
946b8e80941Smrg}
947b8e80941Smrg
948b8e80941Smrgstatic void
949b8e80941Smrgtegra_texture_subdata(struct pipe_context *pcontext,
950b8e80941Smrg                      struct pipe_resource *presource,
951b8e80941Smrg                      unsigned level,
952b8e80941Smrg                      unsigned usage,
953b8e80941Smrg                      const struct pipe_box *box,
954b8e80941Smrg                      const void *data,
955b8e80941Smrg                      unsigned stride,
956b8e80941Smrg                      unsigned layer_stride)
957b8e80941Smrg{
958b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
959b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
960b8e80941Smrg
961b8e80941Smrg   context->gpu->texture_subdata(context->gpu, resource->gpu, level, usage,
962b8e80941Smrg                                 box, data, stride, layer_stride);
963b8e80941Smrg}
964b8e80941Smrg
965b8e80941Smrgstatic void
966b8e80941Smrgtegra_texture_barrier(struct pipe_context *pcontext, unsigned int flags)
967b8e80941Smrg{
968b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
969b8e80941Smrg
970b8e80941Smrg   context->gpu->texture_barrier(context->gpu, flags);
971b8e80941Smrg}
972b8e80941Smrg
973b8e80941Smrgstatic void
974b8e80941Smrgtegra_memory_barrier(struct pipe_context *pcontext, unsigned int flags)
975b8e80941Smrg{
976b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
977b8e80941Smrg
978b8e80941Smrg   if (!(flags & ~PIPE_BARRIER_UPDATE))
979b8e80941Smrg      return;
980b8e80941Smrg
981b8e80941Smrg   context->gpu->memory_barrier(context->gpu, flags);
982b8e80941Smrg}
983b8e80941Smrg
984b8e80941Smrgstatic struct pipe_video_codec *
985b8e80941Smrgtegra_create_video_codec(struct pipe_context *pcontext,
986b8e80941Smrg                         const struct pipe_video_codec *template)
987b8e80941Smrg{
988b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
989b8e80941Smrg
990b8e80941Smrg   return context->gpu->create_video_codec(context->gpu, template);
991b8e80941Smrg}
992b8e80941Smrg
993b8e80941Smrgstatic struct pipe_video_buffer *
994b8e80941Smrgtegra_create_video_buffer(struct pipe_context *pcontext,
995b8e80941Smrg                          const struct pipe_video_buffer *template)
996b8e80941Smrg{
997b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
998b8e80941Smrg
999b8e80941Smrg   return context->gpu->create_video_buffer(context->gpu, template);
1000b8e80941Smrg}
1001b8e80941Smrg
1002b8e80941Smrgstatic void *
1003b8e80941Smrgtegra_create_compute_state(struct pipe_context *pcontext,
1004b8e80941Smrg                           const struct pipe_compute_state *template)
1005b8e80941Smrg{
1006b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1007b8e80941Smrg
1008b8e80941Smrg   return context->gpu->create_compute_state(context->gpu, template);
1009b8e80941Smrg}
1010b8e80941Smrg
1011b8e80941Smrgstatic void
1012b8e80941Smrgtegra_bind_compute_state(struct pipe_context *pcontext, void *so)
1013b8e80941Smrg{
1014b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1015b8e80941Smrg
1016b8e80941Smrg   context->gpu->bind_compute_state(context->gpu, so);
1017b8e80941Smrg}
1018b8e80941Smrg
1019b8e80941Smrgstatic void
1020b8e80941Smrgtegra_delete_compute_state(struct pipe_context *pcontext, void *so)
1021b8e80941Smrg{
1022b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1023b8e80941Smrg
1024b8e80941Smrg   context->gpu->delete_compute_state(context->gpu, so);
1025b8e80941Smrg}
1026b8e80941Smrg
1027b8e80941Smrgstatic void
1028b8e80941Smrgtegra_set_compute_resources(struct pipe_context *pcontext,
1029b8e80941Smrg                            unsigned int start, unsigned int count,
1030b8e80941Smrg                            struct pipe_surface **resources)
1031b8e80941Smrg{
1032b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1033b8e80941Smrg
1034b8e80941Smrg   /* XXX unwrap resources */
1035b8e80941Smrg
1036b8e80941Smrg   context->gpu->set_compute_resources(context->gpu, start, count, resources);
1037b8e80941Smrg}
1038b8e80941Smrg
1039b8e80941Smrgstatic void
1040b8e80941Smrgtegra_set_global_binding(struct pipe_context *pcontext, unsigned int first,
1041b8e80941Smrg                         unsigned int count, struct pipe_resource **resources,
1042b8e80941Smrg                         uint32_t **handles)
1043b8e80941Smrg{
1044b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1045b8e80941Smrg
1046b8e80941Smrg   /* XXX unwrap resources */
1047b8e80941Smrg
1048b8e80941Smrg   context->gpu->set_global_binding(context->gpu, first, count, resources,
1049b8e80941Smrg                                    handles);
1050b8e80941Smrg}
1051b8e80941Smrg
1052b8e80941Smrgstatic void
1053b8e80941Smrgtegra_launch_grid(struct pipe_context *pcontext,
1054b8e80941Smrg                  const struct pipe_grid_info *info)
1055b8e80941Smrg{
1056b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1057b8e80941Smrg
1058b8e80941Smrg   /* XXX unwrap info->indirect? */
1059b8e80941Smrg
1060b8e80941Smrg   context->gpu->launch_grid(context->gpu, info);
1061b8e80941Smrg}
1062b8e80941Smrg
1063b8e80941Smrgstatic void
1064b8e80941Smrgtegra_get_sample_position(struct pipe_context *pcontext, unsigned int count,
1065b8e80941Smrg                          unsigned int index, float *value)
1066b8e80941Smrg{
1067b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1068b8e80941Smrg
1069b8e80941Smrg   context->gpu->get_sample_position(context->gpu, count, index, value);
1070b8e80941Smrg}
1071b8e80941Smrg
1072b8e80941Smrgstatic uint64_t
1073b8e80941Smrgtegra_get_timestamp(struct pipe_context *pcontext)
1074b8e80941Smrg{
1075b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1076b8e80941Smrg
1077b8e80941Smrg   return context->gpu->get_timestamp(context->gpu);
1078b8e80941Smrg}
1079b8e80941Smrg
1080b8e80941Smrgstatic void
1081b8e80941Smrgtegra_flush_resource(struct pipe_context *pcontext,
1082b8e80941Smrg                     struct pipe_resource *presource)
1083b8e80941Smrg{
1084b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
1085b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1086b8e80941Smrg
1087b8e80941Smrg   context->gpu->flush_resource(context->gpu, resource->gpu);
1088b8e80941Smrg}
1089b8e80941Smrg
1090b8e80941Smrgstatic void
1091b8e80941Smrgtegra_invalidate_resource(struct pipe_context *pcontext,
1092b8e80941Smrg                          struct pipe_resource *presource)
1093b8e80941Smrg{
1094b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
1095b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1096b8e80941Smrg
1097b8e80941Smrg   context->gpu->invalidate_resource(context->gpu, resource->gpu);
1098b8e80941Smrg}
1099b8e80941Smrg
1100b8e80941Smrgstatic enum pipe_reset_status
1101b8e80941Smrgtegra_get_device_reset_status(struct pipe_context *pcontext)
1102b8e80941Smrg{
1103b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1104b8e80941Smrg
1105b8e80941Smrg   return context->gpu->get_device_reset_status(context->gpu);
1106b8e80941Smrg}
1107b8e80941Smrg
1108b8e80941Smrgstatic void
1109b8e80941Smrgtegra_set_device_reset_callback(struct pipe_context *pcontext,
1110b8e80941Smrg                                const struct pipe_device_reset_callback *cb)
1111b8e80941Smrg{
1112b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1113b8e80941Smrg
1114b8e80941Smrg   context->gpu->set_device_reset_callback(context->gpu, cb);
1115b8e80941Smrg}
1116b8e80941Smrg
1117b8e80941Smrgstatic void
1118b8e80941Smrgtegra_dump_debug_state(struct pipe_context *pcontext, FILE *stream,
1119b8e80941Smrg                       unsigned int flags)
1120b8e80941Smrg{
1121b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1122b8e80941Smrg
1123b8e80941Smrg   context->gpu->dump_debug_state(context->gpu, stream, flags);
1124b8e80941Smrg}
1125b8e80941Smrg
1126b8e80941Smrgstatic void
1127b8e80941Smrgtegra_emit_string_marker(struct pipe_context *pcontext, const char *string,
1128b8e80941Smrg                         int length)
1129b8e80941Smrg{
1130b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1131b8e80941Smrg
1132b8e80941Smrg   context->gpu->emit_string_marker(context->gpu, string, length);
1133b8e80941Smrg}
1134b8e80941Smrg
1135b8e80941Smrgstatic boolean
1136b8e80941Smrgtegra_generate_mipmap(struct pipe_context *pcontext,
1137b8e80941Smrg                      struct pipe_resource *presource,
1138b8e80941Smrg                      enum pipe_format format,
1139b8e80941Smrg                      unsigned int base_level,
1140b8e80941Smrg                      unsigned int last_level,
1141b8e80941Smrg                      unsigned int first_layer,
1142b8e80941Smrg                      unsigned int last_layer)
1143b8e80941Smrg{
1144b8e80941Smrg   struct tegra_resource *resource = to_tegra_resource(presource);
1145b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1146b8e80941Smrg
1147b8e80941Smrg   return context->gpu->generate_mipmap(context->gpu, resource->gpu, format,
1148b8e80941Smrg                                        base_level, last_level, first_layer,
1149b8e80941Smrg                                        last_layer);
1150b8e80941Smrg}
1151b8e80941Smrg
1152b8e80941Smrgstatic uint64_t
1153b8e80941Smrgtegra_create_texture_handle(struct pipe_context *pcontext,
1154b8e80941Smrg                            struct pipe_sampler_view *view,
1155b8e80941Smrg                            const struct pipe_sampler_state *state)
1156b8e80941Smrg{
1157b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1158b8e80941Smrg
1159b8e80941Smrg   return context->gpu->create_texture_handle(context->gpu, view, state);
1160b8e80941Smrg}
1161b8e80941Smrg
1162b8e80941Smrgstatic void tegra_delete_texture_handle(struct pipe_context *pcontext,
1163b8e80941Smrg                                        uint64_t handle)
1164b8e80941Smrg{
1165b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1166b8e80941Smrg
1167b8e80941Smrg   context->gpu->delete_texture_handle(context->gpu, handle);
1168b8e80941Smrg}
1169b8e80941Smrg
1170b8e80941Smrgstatic void tegra_make_texture_handle_resident(struct pipe_context *pcontext,
1171b8e80941Smrg                                               uint64_t handle, bool resident)
1172b8e80941Smrg{
1173b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1174b8e80941Smrg
1175b8e80941Smrg   context->gpu->make_texture_handle_resident(context->gpu, handle, resident);
1176b8e80941Smrg}
1177b8e80941Smrg
1178b8e80941Smrgstatic uint64_t tegra_create_image_handle(struct pipe_context *pcontext,
1179b8e80941Smrg                                          const struct pipe_image_view *image)
1180b8e80941Smrg{
1181b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1182b8e80941Smrg
1183b8e80941Smrg   return context->gpu->create_image_handle(context->gpu, image);
1184b8e80941Smrg}
1185b8e80941Smrg
1186b8e80941Smrgstatic void tegra_delete_image_handle(struct pipe_context *pcontext,
1187b8e80941Smrg                                      uint64_t handle)
1188b8e80941Smrg{
1189b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1190b8e80941Smrg
1191b8e80941Smrg   context->gpu->delete_image_handle(context->gpu, handle);
1192b8e80941Smrg}
1193b8e80941Smrg
1194b8e80941Smrgstatic void tegra_make_image_handle_resident(struct pipe_context *pcontext,
1195b8e80941Smrg                                             uint64_t handle, unsigned access,
1196b8e80941Smrg                                             bool resident)
1197b8e80941Smrg{
1198b8e80941Smrg   struct tegra_context *context = to_tegra_context(pcontext);
1199b8e80941Smrg
1200b8e80941Smrg   context->gpu->make_image_handle_resident(context->gpu, handle, access,
1201b8e80941Smrg                                            resident);
1202b8e80941Smrg}
1203b8e80941Smrg
1204b8e80941Smrgstruct pipe_context *
1205b8e80941Smrgtegra_screen_context_create(struct pipe_screen *pscreen, void *priv,
1206b8e80941Smrg                            unsigned int flags)
1207b8e80941Smrg{
1208b8e80941Smrg   struct tegra_screen *screen = to_tegra_screen(pscreen);
1209b8e80941Smrg   struct tegra_context *context;
1210b8e80941Smrg
1211b8e80941Smrg   context = calloc(1, sizeof(*context));
1212b8e80941Smrg   if (!context)
1213b8e80941Smrg      return NULL;
1214b8e80941Smrg
1215b8e80941Smrg   context->gpu = screen->gpu->context_create(screen->gpu, priv, flags);
1216b8e80941Smrg   if (!context->gpu) {
1217b8e80941Smrg      debug_error("failed to create GPU context\n");
1218b8e80941Smrg      goto free;
1219b8e80941Smrg   }
1220b8e80941Smrg
1221b8e80941Smrg   context->base.screen = &screen->base;
1222b8e80941Smrg   context->base.priv = priv;
1223b8e80941Smrg
1224b8e80941Smrg   /*
1225b8e80941Smrg    * Create custom stream and const uploaders. Note that technically nouveau
1226b8e80941Smrg    * already creates uploaders that could be reused, but that would make the
1227b8e80941Smrg    * resource unwrapping rather complicate. The reason for that is that both
1228b8e80941Smrg    * uploaders create resources based on the context that they were created
1229b8e80941Smrg    * from, which means that nouveau's uploader will use the nouveau context
1230b8e80941Smrg    * which means that those resources must not be unwrapped. So before each
1231b8e80941Smrg    * resource is unwrapped, the code would need to check that it does not
1232b8e80941Smrg    * correspond to the uploaders' buffers.
1233b8e80941Smrg    *
1234b8e80941Smrg    * However, duplicating the uploaders here sounds worse than it is. The
1235b8e80941Smrg    * default implementation that nouveau uses allocates buffers lazily, and
1236b8e80941Smrg    * since it is never used, no buffers will every be allocated and the only
1237b8e80941Smrg    * memory wasted is that occupied by the nouveau uploader itself.
1238b8e80941Smrg    */
1239b8e80941Smrg   context->base.stream_uploader = u_upload_create_default(&context->base);
1240b8e80941Smrg   if (!context->base.stream_uploader)
1241b8e80941Smrg      goto destroy;
1242b8e80941Smrg
1243b8e80941Smrg   context->base.const_uploader = context->base.stream_uploader;
1244b8e80941Smrg
1245b8e80941Smrg   context->base.destroy = tegra_destroy;
1246b8e80941Smrg
1247b8e80941Smrg   context->base.draw_vbo = tegra_draw_vbo;
1248b8e80941Smrg
1249b8e80941Smrg   context->base.render_condition = tegra_render_condition;
1250b8e80941Smrg
1251b8e80941Smrg   context->base.create_query = tegra_create_query;
1252b8e80941Smrg   context->base.create_batch_query = tegra_create_batch_query;
1253b8e80941Smrg   context->base.destroy_query = tegra_destroy_query;
1254b8e80941Smrg   context->base.begin_query = tegra_begin_query;
1255b8e80941Smrg   context->base.end_query = tegra_end_query;
1256b8e80941Smrg   context->base.get_query_result = tegra_get_query_result;
1257b8e80941Smrg   context->base.get_query_result_resource = tegra_get_query_result_resource;
1258b8e80941Smrg   context->base.set_active_query_state = tegra_set_active_query_state;
1259b8e80941Smrg
1260b8e80941Smrg   context->base.create_blend_state = tegra_create_blend_state;
1261b8e80941Smrg   context->base.bind_blend_state = tegra_bind_blend_state;
1262b8e80941Smrg   context->base.delete_blend_state = tegra_delete_blend_state;
1263b8e80941Smrg
1264b8e80941Smrg   context->base.create_sampler_state = tegra_create_sampler_state;
1265b8e80941Smrg   context->base.bind_sampler_states = tegra_bind_sampler_states;
1266b8e80941Smrg   context->base.delete_sampler_state = tegra_delete_sampler_state;
1267b8e80941Smrg
1268b8e80941Smrg   context->base.create_rasterizer_state = tegra_create_rasterizer_state;
1269b8e80941Smrg   context->base.bind_rasterizer_state = tegra_bind_rasterizer_state;
1270b8e80941Smrg   context->base.delete_rasterizer_state = tegra_delete_rasterizer_state;
1271b8e80941Smrg
1272b8e80941Smrg   context->base.create_depth_stencil_alpha_state = tegra_create_depth_stencil_alpha_state;
1273b8e80941Smrg   context->base.bind_depth_stencil_alpha_state = tegra_bind_depth_stencil_alpha_state;
1274b8e80941Smrg   context->base.delete_depth_stencil_alpha_state = tegra_delete_depth_stencil_alpha_state;
1275b8e80941Smrg
1276b8e80941Smrg   context->base.create_fs_state = tegra_create_fs_state;
1277b8e80941Smrg   context->base.bind_fs_state = tegra_bind_fs_state;
1278b8e80941Smrg   context->base.delete_fs_state = tegra_delete_fs_state;
1279b8e80941Smrg
1280b8e80941Smrg   context->base.create_vs_state = tegra_create_vs_state;
1281b8e80941Smrg   context->base.bind_vs_state = tegra_bind_vs_state;
1282b8e80941Smrg   context->base.delete_vs_state = tegra_delete_vs_state;
1283b8e80941Smrg
1284b8e80941Smrg   context->base.create_gs_state = tegra_create_gs_state;
1285b8e80941Smrg   context->base.bind_gs_state = tegra_bind_gs_state;
1286b8e80941Smrg   context->base.delete_gs_state = tegra_delete_gs_state;
1287b8e80941Smrg
1288b8e80941Smrg   context->base.create_tcs_state = tegra_create_tcs_state;
1289b8e80941Smrg   context->base.bind_tcs_state = tegra_bind_tcs_state;
1290b8e80941Smrg   context->base.delete_tcs_state = tegra_delete_tcs_state;
1291b8e80941Smrg
1292b8e80941Smrg   context->base.create_tes_state = tegra_create_tes_state;
1293b8e80941Smrg   context->base.bind_tes_state = tegra_bind_tes_state;
1294b8e80941Smrg   context->base.delete_tes_state = tegra_delete_tes_state;
1295b8e80941Smrg
1296b8e80941Smrg   context->base.create_vertex_elements_state = tegra_create_vertex_elements_state;
1297b8e80941Smrg   context->base.bind_vertex_elements_state = tegra_bind_vertex_elements_state;
1298b8e80941Smrg   context->base.delete_vertex_elements_state = tegra_delete_vertex_elements_state;
1299b8e80941Smrg
1300b8e80941Smrg   context->base.set_blend_color = tegra_set_blend_color;
1301b8e80941Smrg   context->base.set_stencil_ref = tegra_set_stencil_ref;
1302b8e80941Smrg   context->base.set_sample_mask = tegra_set_sample_mask;
1303b8e80941Smrg   context->base.set_min_samples = tegra_set_min_samples;
1304b8e80941Smrg   context->base.set_clip_state = tegra_set_clip_state;
1305b8e80941Smrg
1306b8e80941Smrg   context->base.set_constant_buffer = tegra_set_constant_buffer;
1307b8e80941Smrg   context->base.set_framebuffer_state = tegra_set_framebuffer_state;
1308b8e80941Smrg   context->base.set_polygon_stipple = tegra_set_polygon_stipple;
1309b8e80941Smrg   context->base.set_scissor_states = tegra_set_scissor_states;
1310b8e80941Smrg   context->base.set_window_rectangles = tegra_set_window_rectangles;
1311b8e80941Smrg   context->base.set_viewport_states = tegra_set_viewport_states;
1312b8e80941Smrg   context->base.set_sampler_views = tegra_set_sampler_views;
1313b8e80941Smrg   context->base.set_tess_state = tegra_set_tess_state;
1314b8e80941Smrg
1315b8e80941Smrg   context->base.set_debug_callback = tegra_set_debug_callback;
1316b8e80941Smrg
1317b8e80941Smrg   context->base.set_shader_buffers = tegra_set_shader_buffers;
1318b8e80941Smrg   context->base.set_shader_images = tegra_set_shader_images;
1319b8e80941Smrg   context->base.set_vertex_buffers = tegra_set_vertex_buffers;
1320b8e80941Smrg
1321b8e80941Smrg   context->base.create_stream_output_target = tegra_create_stream_output_target;
1322b8e80941Smrg   context->base.stream_output_target_destroy = tegra_stream_output_target_destroy;
1323b8e80941Smrg   context->base.set_stream_output_targets = tegra_set_stream_output_targets;
1324b8e80941Smrg
1325b8e80941Smrg   context->base.resource_copy_region = tegra_resource_copy_region;
1326b8e80941Smrg   context->base.blit = tegra_blit;
1327b8e80941Smrg   context->base.clear = tegra_clear;
1328b8e80941Smrg   context->base.clear_render_target = tegra_clear_render_target;
1329b8e80941Smrg   context->base.clear_depth_stencil = tegra_clear_depth_stencil;
1330b8e80941Smrg   context->base.clear_texture = tegra_clear_texture;
1331b8e80941Smrg   context->base.clear_buffer = tegra_clear_buffer;
1332b8e80941Smrg   context->base.flush = tegra_flush;
1333b8e80941Smrg
1334b8e80941Smrg   context->base.create_fence_fd = tegra_create_fence_fd;
1335b8e80941Smrg   context->base.fence_server_sync = tegra_fence_server_sync;
1336b8e80941Smrg
1337b8e80941Smrg   context->base.create_sampler_view = tegra_create_sampler_view;
1338b8e80941Smrg   context->base.sampler_view_destroy = tegra_sampler_view_destroy;
1339b8e80941Smrg
1340b8e80941Smrg   context->base.create_surface = tegra_create_surface;
1341b8e80941Smrg   context->base.surface_destroy = tegra_surface_destroy;
1342b8e80941Smrg
1343b8e80941Smrg   context->base.transfer_map = tegra_transfer_map;
1344b8e80941Smrg   context->base.transfer_flush_region = tegra_transfer_flush_region;
1345b8e80941Smrg   context->base.transfer_unmap = tegra_transfer_unmap;
1346b8e80941Smrg   context->base.buffer_subdata = tegra_buffer_subdata;
1347b8e80941Smrg   context->base.texture_subdata = tegra_texture_subdata;
1348b8e80941Smrg
1349b8e80941Smrg   context->base.texture_barrier = tegra_texture_barrier;
1350b8e80941Smrg   context->base.memory_barrier = tegra_memory_barrier;
1351b8e80941Smrg
1352b8e80941Smrg   context->base.create_video_codec = tegra_create_video_codec;
1353b8e80941Smrg   context->base.create_video_buffer = tegra_create_video_buffer;
1354b8e80941Smrg
1355b8e80941Smrg   context->base.create_compute_state = tegra_create_compute_state;
1356b8e80941Smrg   context->base.bind_compute_state = tegra_bind_compute_state;
1357b8e80941Smrg   context->base.delete_compute_state = tegra_delete_compute_state;
1358b8e80941Smrg   context->base.set_compute_resources = tegra_set_compute_resources;
1359b8e80941Smrg   context->base.set_global_binding = tegra_set_global_binding;
1360b8e80941Smrg   context->base.launch_grid = tegra_launch_grid;
1361b8e80941Smrg   context->base.get_sample_position = tegra_get_sample_position;
1362b8e80941Smrg   context->base.get_timestamp = tegra_get_timestamp;
1363b8e80941Smrg
1364b8e80941Smrg   context->base.flush_resource = tegra_flush_resource;
1365b8e80941Smrg   context->base.invalidate_resource = tegra_invalidate_resource;
1366b8e80941Smrg
1367b8e80941Smrg   context->base.get_device_reset_status = tegra_get_device_reset_status;
1368b8e80941Smrg   context->base.set_device_reset_callback = tegra_set_device_reset_callback;
1369b8e80941Smrg   context->base.dump_debug_state = tegra_dump_debug_state;
1370b8e80941Smrg   context->base.emit_string_marker = tegra_emit_string_marker;
1371b8e80941Smrg
1372b8e80941Smrg   context->base.generate_mipmap = tegra_generate_mipmap;
1373b8e80941Smrg
1374b8e80941Smrg   context->base.create_texture_handle = tegra_create_texture_handle;
1375b8e80941Smrg   context->base.delete_texture_handle = tegra_delete_texture_handle;
1376b8e80941Smrg   context->base.make_texture_handle_resident = tegra_make_texture_handle_resident;
1377b8e80941Smrg   context->base.create_image_handle = tegra_create_image_handle;
1378b8e80941Smrg   context->base.delete_image_handle = tegra_delete_image_handle;
1379b8e80941Smrg   context->base.make_image_handle_resident = tegra_make_image_handle_resident;
1380b8e80941Smrg
1381b8e80941Smrg   return &context->base;
1382b8e80941Smrg
1383b8e80941Smrgdestroy:
1384b8e80941Smrg   context->gpu->destroy(context->gpu);
1385b8e80941Smrgfree:
1386b8e80941Smrg   free(context);
1387b8e80941Smrg   return NULL;
1388b8e80941Smrg}
1389