1b8e80941Smrg/* 2b8e80941Smrg * Copyright © 2014-2018 NVIDIA Corporation 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 9b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21b8e80941Smrg * IN THE SOFTWARE. 22b8e80941Smrg */ 23b8e80941Smrg 24b8e80941Smrg#ifndef TEGRA_CONTEXT_H 25b8e80941Smrg#define TEGRA_CONTEXT_H 26b8e80941Smrg 27b8e80941Smrg#include "pipe/p_context.h" 28b8e80941Smrg#include "pipe/p_state.h" 29b8e80941Smrg 30b8e80941Smrgstruct tegra_screen; 31b8e80941Smrg 32b8e80941Smrgstruct tegra_context { 33b8e80941Smrg struct pipe_context base; 34b8e80941Smrg struct pipe_context *gpu; 35b8e80941Smrg}; 36b8e80941Smrg 37b8e80941Smrgstatic inline struct tegra_context * 38b8e80941Smrgto_tegra_context(struct pipe_context *context) 39b8e80941Smrg{ 40b8e80941Smrg return (struct tegra_context *)context; 41b8e80941Smrg} 42b8e80941Smrg 43b8e80941Smrgstruct pipe_context * 44b8e80941Smrgtegra_screen_context_create(struct pipe_screen *pscreen, void *priv, 45b8e80941Smrg unsigned int flags); 46b8e80941Smrg 47b8e80941Smrgstruct tegra_sampler_view { 48b8e80941Smrg struct pipe_sampler_view base; 49b8e80941Smrg struct pipe_sampler_view *gpu; 50b8e80941Smrg}; 51b8e80941Smrg 52b8e80941Smrgstatic inline struct tegra_sampler_view * 53b8e80941Smrgto_tegra_sampler_view(struct pipe_sampler_view *view) 54b8e80941Smrg{ 55b8e80941Smrg return (struct tegra_sampler_view *)view; 56b8e80941Smrg} 57b8e80941Smrg 58b8e80941Smrgstatic inline struct pipe_sampler_view * 59b8e80941Smrgtegra_sampler_view_unwrap(struct pipe_sampler_view *view) 60b8e80941Smrg{ 61b8e80941Smrg if (!view) 62b8e80941Smrg return NULL; 63b8e80941Smrg 64b8e80941Smrg return to_tegra_sampler_view(view)->gpu; 65b8e80941Smrg} 66b8e80941Smrg 67b8e80941Smrgstruct tegra_transfer { 68b8e80941Smrg struct pipe_transfer base; 69b8e80941Smrg struct pipe_transfer *gpu; 70b8e80941Smrg 71b8e80941Smrg unsigned int count; 72b8e80941Smrg void *map; 73b8e80941Smrg}; 74b8e80941Smrg 75b8e80941Smrgstatic inline struct tegra_transfer * 76b8e80941Smrgto_tegra_transfer(struct pipe_transfer *transfer) 77b8e80941Smrg{ 78b8e80941Smrg return (struct tegra_transfer *)transfer; 79b8e80941Smrg} 80b8e80941Smrg 81b8e80941Smrg#endif /* TEGRA_SCREEN_H */ 82