1b8e80941Smrg/* 2b8e80941Smrg * Copyright 2014, 2015 Red Hat. 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub 8b8e80941Smrg * license, and/or sell copies of the Software, and to permit persons to whom 9b8e80941Smrg * the Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19b8e80941Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20b8e80941Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21b8e80941Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE. 22b8e80941Smrg */ 23b8e80941Smrg#ifndef VIRGL_PROTOCOL_H 24b8e80941Smrg#define VIRGL_PROTOCOL_H 25b8e80941Smrg 26b8e80941Smrg#define VIRGL_QUERY_STATE_NEW 0 27b8e80941Smrg#define VIRGL_QUERY_STATE_DONE 1 28b8e80941Smrg#define VIRGL_QUERY_STATE_WAIT_HOST 2 29b8e80941Smrg 30b8e80941Smrgstruct virgl_host_query_state { 31b8e80941Smrg uint32_t query_state; 32b8e80941Smrg uint32_t result_size; 33b8e80941Smrg uint64_t result; 34b8e80941Smrg}; 35b8e80941Smrg 36b8e80941Smrgenum virgl_object_type { 37b8e80941Smrg VIRGL_OBJECT_NULL, 38b8e80941Smrg VIRGL_OBJECT_BLEND, 39b8e80941Smrg VIRGL_OBJECT_RASTERIZER, 40b8e80941Smrg VIRGL_OBJECT_DSA, 41b8e80941Smrg VIRGL_OBJECT_SHADER, 42b8e80941Smrg VIRGL_OBJECT_VERTEX_ELEMENTS, 43b8e80941Smrg VIRGL_OBJECT_SAMPLER_VIEW, 44b8e80941Smrg VIRGL_OBJECT_SAMPLER_STATE, 45b8e80941Smrg VIRGL_OBJECT_SURFACE, 46b8e80941Smrg VIRGL_OBJECT_QUERY, 47b8e80941Smrg VIRGL_OBJECT_STREAMOUT_TARGET, 48b8e80941Smrg VIRGL_MAX_OBJECTS, 49b8e80941Smrg}; 50b8e80941Smrg 51b8e80941Smrg/* context cmds to be encoded in the command stream */ 52b8e80941Smrgenum virgl_context_cmd { 53b8e80941Smrg VIRGL_CCMD_NOP = 0, 54b8e80941Smrg VIRGL_CCMD_CREATE_OBJECT = 1, 55b8e80941Smrg VIRGL_CCMD_BIND_OBJECT, 56b8e80941Smrg VIRGL_CCMD_DESTROY_OBJECT, 57b8e80941Smrg VIRGL_CCMD_SET_VIEWPORT_STATE, 58b8e80941Smrg VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 59b8e80941Smrg VIRGL_CCMD_SET_VERTEX_BUFFERS, 60b8e80941Smrg VIRGL_CCMD_CLEAR, 61b8e80941Smrg VIRGL_CCMD_DRAW_VBO, 62b8e80941Smrg VIRGL_CCMD_RESOURCE_INLINE_WRITE, 63b8e80941Smrg VIRGL_CCMD_SET_SAMPLER_VIEWS, 64b8e80941Smrg VIRGL_CCMD_SET_INDEX_BUFFER, 65b8e80941Smrg VIRGL_CCMD_SET_CONSTANT_BUFFER, 66b8e80941Smrg VIRGL_CCMD_SET_STENCIL_REF, 67b8e80941Smrg VIRGL_CCMD_SET_BLEND_COLOR, 68b8e80941Smrg VIRGL_CCMD_SET_SCISSOR_STATE, 69b8e80941Smrg VIRGL_CCMD_BLIT, 70b8e80941Smrg VIRGL_CCMD_RESOURCE_COPY_REGION, 71b8e80941Smrg VIRGL_CCMD_BIND_SAMPLER_STATES, 72b8e80941Smrg VIRGL_CCMD_BEGIN_QUERY, 73b8e80941Smrg VIRGL_CCMD_END_QUERY, 74b8e80941Smrg VIRGL_CCMD_GET_QUERY_RESULT, 75b8e80941Smrg VIRGL_CCMD_SET_POLYGON_STIPPLE, 76b8e80941Smrg VIRGL_CCMD_SET_CLIP_STATE, 77b8e80941Smrg VIRGL_CCMD_SET_SAMPLE_MASK, 78b8e80941Smrg VIRGL_CCMD_SET_STREAMOUT_TARGETS, 79b8e80941Smrg VIRGL_CCMD_SET_RENDER_CONDITION, 80b8e80941Smrg VIRGL_CCMD_SET_UNIFORM_BUFFER, 81b8e80941Smrg 82b8e80941Smrg VIRGL_CCMD_SET_SUB_CTX, 83b8e80941Smrg VIRGL_CCMD_CREATE_SUB_CTX, 84b8e80941Smrg VIRGL_CCMD_DESTROY_SUB_CTX, 85b8e80941Smrg VIRGL_CCMD_BIND_SHADER, 86b8e80941Smrg VIRGL_CCMD_SET_TESS_STATE, 87b8e80941Smrg VIRGL_CCMD_SET_MIN_SAMPLES, 88b8e80941Smrg VIRGL_CCMD_SET_SHADER_BUFFERS, 89b8e80941Smrg VIRGL_CCMD_SET_SHADER_IMAGES, 90b8e80941Smrg VIRGL_CCMD_MEMORY_BARRIER, 91b8e80941Smrg VIRGL_CCMD_LAUNCH_GRID, 92b8e80941Smrg VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACH, 93b8e80941Smrg VIRGL_CCMD_TEXTURE_BARRIER, 94b8e80941Smrg VIRGL_CCMD_SET_ATOMIC_BUFFERS, 95b8e80941Smrg VIRGL_CCMD_SET_DEBUG_FLAGS, 96b8e80941Smrg VIRGL_CCMD_GET_QUERY_RESULT_QBO, 97b8e80941Smrg VIRGL_CCMD_TRANSFER3D, 98b8e80941Smrg VIRGL_CCMD_END_TRANSFERS, 99b8e80941Smrg}; 100b8e80941Smrg 101b8e80941Smrg/* 102b8e80941Smrg 8-bit cmd headers 103b8e80941Smrg 8-bit object type 104b8e80941Smrg 16-bit length 105b8e80941Smrg*/ 106b8e80941Smrg 107b8e80941Smrg#define VIRGL_CMD0(cmd, obj, len) ((cmd) | ((obj) << 8) | ((len) << 16)) 108b8e80941Smrg#define VIRGL_CMD0_MAX_DWORDS (((1ULL << 16) - 1) / 4) * 4 109b8e80941Smrg 110b8e80941Smrg/* hw specification */ 111b8e80941Smrg#define VIRGL_MAX_COLOR_BUFS 8 112b8e80941Smrg#define VIRGL_MAX_CLIP_PLANES 8 113b8e80941Smrg 114b8e80941Smrg#define VIRGL_OBJ_CREATE_HEADER 0 115b8e80941Smrg#define VIRGL_OBJ_CREATE_HANDLE 1 116b8e80941Smrg 117b8e80941Smrg#define VIRGL_OBJ_BIND_HEADER 0 118b8e80941Smrg#define VIRGL_OBJ_BIND_HANDLE 1 119b8e80941Smrg 120b8e80941Smrg#define VIRGL_OBJ_DESTROY_HANDLE 1 121b8e80941Smrg 122b8e80941Smrg/* some of these defines are a specification - not used in the code */ 123b8e80941Smrg/* bit offsets for blend state object */ 124b8e80941Smrg#define VIRGL_OBJ_BLEND_SIZE (VIRGL_MAX_COLOR_BUFS + 3) 125b8e80941Smrg#define VIRGL_OBJ_BLEND_HANDLE 1 126b8e80941Smrg#define VIRGL_OBJ_BLEND_S0 2 127b8e80941Smrg#define VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(x) ((x) & 0x1 << 0) 128b8e80941Smrg#define VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(x) (((x) & 0x1) << 1) 129b8e80941Smrg#define VIRGL_OBJ_BLEND_S0_DITHER(x) (((x) & 0x1) << 2) 130b8e80941Smrg#define VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(x) (((x) & 0x1) << 3) 131b8e80941Smrg#define VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(x) (((x) & 0x1) << 4) 132b8e80941Smrg#define VIRGL_OBJ_BLEND_S1 3 133b8e80941Smrg#define VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(x) (((x) & 0xf) << 0) 134b8e80941Smrg/* repeated once per number of cbufs */ 135b8e80941Smrg 136b8e80941Smrg#define VIRGL_OBJ_BLEND_S2(cbuf) (4 + (cbuf)) 137b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(x) (((x) & 0x1) << 0) 138b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(x) (((x) & 0x7) << 1) 139b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(x) (((x) & 0x1f) << 4) 140b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(x) (((x) & 0x1f) << 9) 141b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(x) (((x) & 0x7) << 14) 142b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(x) (((x) & 0x1f) << 17) 143b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(x) (((x) & 0x1f) << 22) 144b8e80941Smrg#define VIRGL_OBJ_BLEND_S2_RT_COLORMASK(x) (((x) & 0xf) << 27) 145b8e80941Smrg 146b8e80941Smrg/* bit offsets for DSA state */ 147b8e80941Smrg#define VIRGL_OBJ_DSA_SIZE 5 148b8e80941Smrg#define VIRGL_OBJ_DSA_HANDLE 1 149b8e80941Smrg#define VIRGL_OBJ_DSA_S0 2 150b8e80941Smrg#define VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(x) (((x) & 0x1) << 0) 151b8e80941Smrg#define VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(x) (((x) & 0x1) << 1) 152b8e80941Smrg#define VIRGL_OBJ_DSA_S0_DEPTH_FUNC(x) (((x) & 0x7) << 2) 153b8e80941Smrg#define VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(x) (((x) & 0x1) << 8) 154b8e80941Smrg#define VIRGL_OBJ_DSA_S0_ALPHA_FUNC(x) (((x) & 0x7) << 9) 155b8e80941Smrg#define VIRGL_OBJ_DSA_S1 3 156b8e80941Smrg#define VIRGL_OBJ_DSA_S2 4 157b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(x) (((x) & 0x1) << 0) 158b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_FUNC(x) (((x) & 0x7) << 1) 159b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(x) (((x) & 0x7) << 4) 160b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(x) (((x) & 0x7) << 7) 161b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(x) (((x) & 0x7) << 10) 162b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(x) (((x) & 0xff) << 13) 163b8e80941Smrg#define VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(x) (((x) & 0xff) << 21) 164b8e80941Smrg#define VIRGL_OBJ_DSA_ALPHA_REF 5 165b8e80941Smrg 166b8e80941Smrg/* offsets for rasterizer state */ 167b8e80941Smrg#define VIRGL_OBJ_RS_SIZE 9 168b8e80941Smrg#define VIRGL_OBJ_RS_HANDLE 1 169b8e80941Smrg#define VIRGL_OBJ_RS_S0 2 170b8e80941Smrg#define VIRGL_OBJ_RS_S0_FLATSHADE(x) (((x) & 0x1) << 0) 171b8e80941Smrg#define VIRGL_OBJ_RS_S0_DEPTH_CLIP(x) (((x) & 0x1) << 1) 172b8e80941Smrg#define VIRGL_OBJ_RS_S0_CLIP_HALFZ(x) (((x) & 0x1) << 2) 173b8e80941Smrg#define VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(x) (((x) & 0x1) << 3) 174b8e80941Smrg#define VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(x) (((x) & 0x1) << 4) 175b8e80941Smrg#define VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(x) (((x) & 0x1) << 5) 176b8e80941Smrg#define VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(x) (((x) & 0x1) << 6) 177b8e80941Smrg#define VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(x) (((x) & 0x1) << 7) 178b8e80941Smrg#define VIRGL_OBJ_RS_S0_CULL_FACE(x) (((x) & 0x3) << 8) 179b8e80941Smrg#define VIRGL_OBJ_RS_S0_FILL_FRONT(x) (((x) & 0x3) << 10) 180b8e80941Smrg#define VIRGL_OBJ_RS_S0_FILL_BACK(x) (((x) & 0x3) << 12) 181b8e80941Smrg#define VIRGL_OBJ_RS_S0_SCISSOR(x) (((x) & 0x1) << 14) 182b8e80941Smrg#define VIRGL_OBJ_RS_S0_FRONT_CCW(x) (((x) & 0x1) << 15) 183b8e80941Smrg#define VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(x) (((x) & 0x1) << 16) 184b8e80941Smrg#define VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(x) (((x) & 0x1) << 17) 185b8e80941Smrg#define VIRGL_OBJ_RS_S0_OFFSET_LINE(x) (((x) & 0x1) << 18) 186b8e80941Smrg#define VIRGL_OBJ_RS_S0_OFFSET_POINT(x) (((x) & 0x1) << 19) 187b8e80941Smrg#define VIRGL_OBJ_RS_S0_OFFSET_TRI(x) (((x) & 0x1) << 20) 188b8e80941Smrg#define VIRGL_OBJ_RS_S0_POLY_SMOOTH(x) (((x) & 0x1) << 21) 189b8e80941Smrg#define VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(x) (((x) & 0x1) << 22) 190b8e80941Smrg#define VIRGL_OBJ_RS_S0_POINT_SMOOTH(x) (((x) & 0x1) << 23) 191b8e80941Smrg#define VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(x) (((x) & 0x1) << 24) 192b8e80941Smrg#define VIRGL_OBJ_RS_S0_MULTISAMPLE(x) (((x) & 0x1) << 25) 193b8e80941Smrg#define VIRGL_OBJ_RS_S0_LINE_SMOOTH(x) (((x) & 0x1) << 26) 194b8e80941Smrg#define VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 27) 195b8e80941Smrg#define VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28) 196b8e80941Smrg#define VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29) 197b8e80941Smrg#define VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30) 198b8e80941Smrg#define VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31) 199b8e80941Smrg 200b8e80941Smrg#define VIRGL_OBJ_RS_POINT_SIZE 3 201b8e80941Smrg#define VIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4 202b8e80941Smrg#define VIRGL_OBJ_RS_S3 5 203b8e80941Smrg 204b8e80941Smrg#define VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(x) (((x) & 0xffff) << 0) 205b8e80941Smrg#define VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(x) (((x) & 0xff) << 16) 206b8e80941Smrg#define VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(x) (((x) & 0xff) << 24) 207b8e80941Smrg#define VIRGL_OBJ_RS_LINE_WIDTH 6 208b8e80941Smrg#define VIRGL_OBJ_RS_OFFSET_UNITS 7 209b8e80941Smrg#define VIRGL_OBJ_RS_OFFSET_SCALE 8 210b8e80941Smrg#define VIRGL_OBJ_RS_OFFSET_CLAMP 9 211b8e80941Smrg 212b8e80941Smrg#define VIRGL_OBJ_CLEAR_SIZE 8 213b8e80941Smrg#define VIRGL_OBJ_CLEAR_BUFFERS 1 214b8e80941Smrg#define VIRGL_OBJ_CLEAR_COLOR_0 2 /* color is 4 * u32/f32/i32 */ 215b8e80941Smrg#define VIRGL_OBJ_CLEAR_COLOR_1 3 216b8e80941Smrg#define VIRGL_OBJ_CLEAR_COLOR_2 4 217b8e80941Smrg#define VIRGL_OBJ_CLEAR_COLOR_3 5 218b8e80941Smrg#define VIRGL_OBJ_CLEAR_DEPTH_0 6 /* depth is a double precision float */ 219b8e80941Smrg#define VIRGL_OBJ_CLEAR_DEPTH_1 7 220b8e80941Smrg#define VIRGL_OBJ_CLEAR_STENCIL 8 221b8e80941Smrg 222b8e80941Smrg/* shader object */ 223b8e80941Smrg#define VIRGL_OBJ_SHADER_HDR_SIZE(nso) (5 + ((nso) ? (2 * nso) + 4 : 0)) 224b8e80941Smrg#define VIRGL_OBJ_SHADER_HANDLE 1 225b8e80941Smrg#define VIRGL_OBJ_SHADER_TYPE 2 226b8e80941Smrg#define VIRGL_OBJ_SHADER_OFFSET 3 227b8e80941Smrg#define VIRGL_OBJ_SHADER_OFFSET_VAL(x) (((x) & 0x7fffffff) << 0) 228b8e80941Smrg/* start contains full length in VAL - also implies continuations */ 229b8e80941Smrg/* continuation contains offset in VAL */ 230b8e80941Smrg#define VIRGL_OBJ_SHADER_OFFSET_CONT (0x1u << 31) 231b8e80941Smrg#define VIRGL_OBJ_SHADER_NUM_TOKENS 4 232b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_NUM_OUTPUTS 5 233b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_STRIDE(x) (6 + (x)) 234b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT0(x) (10 + (x * 2)) 235b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(x) (((x) & 0xff) << 0) 236b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(x) (((x) & 0x3) << 8) 237b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(x) (((x) & 0x7) << 10) 238b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(x) (((x) & 0x7) << 13) 239b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(x) (((x) & 0xffff) << 16) 240b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT0_SO(x) (11 + (x * 2)) 241b8e80941Smrg#define VIRGL_OBJ_SHADER_SO_OUTPUT_STREAM(x) (((x) & 0x03) << 0) 242b8e80941Smrg 243b8e80941Smrg/* viewport state */ 244b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports) ((6 * num_viewports) + 1) 245b8e80941Smrg#define VIRGL_SET_VIEWPORT_START_SLOT 1 246b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_SCALE_0(x) (2 + (x * 6)) 247b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_SCALE_1(x) (3 + (x * 6)) 248b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_SCALE_2(x) (4 + (x * 6)) 249b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_0(x) (5 + (x * 6)) 250b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_1(x) (6 + (x * 6)) 251b8e80941Smrg#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_2(x) (7 + (x * 6)) 252b8e80941Smrg 253b8e80941Smrg/* framebuffer state */ 254b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_SIZE(nr_cbufs) (nr_cbufs + 2) 255b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NR_CBUFS 1 256b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NR_ZSURF_HANDLE 2 257b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_CBUF_HANDLE(x) ((x) + 3) 258b8e80941Smrg 259b8e80941Smrg/* vertex elements object */ 260b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements) (((num_elements) * 4) + 1) 261b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_HANDLE 1 262b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_OFFSET(x) (((x) * 4) + 2) /* repeated per VE */ 263b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_INSTANCE_DIVISOR(x) (((x) * 4) + 3) 264b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_VERTEX_BUFFER_INDEX(x) (((x) * 4) + 4) 265b8e80941Smrg#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_FORMAT(x) (((x) * 4) + 5) 266b8e80941Smrg 267b8e80941Smrg/* vertex buffers */ 268b8e80941Smrg#define VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers) ((num_buffers) * 3) 269b8e80941Smrg#define VIRGL_SET_VERTEX_BUFFER_STRIDE(x) (((x) * 3) + 1) 270b8e80941Smrg#define VIRGL_SET_VERTEX_BUFFER_OFFSET(x) (((x) * 3) + 2) 271b8e80941Smrg#define VIRGL_SET_VERTEX_BUFFER_HANDLE(x) (((x) * 3) + 3) 272b8e80941Smrg 273b8e80941Smrg/* index buffer */ 274b8e80941Smrg#define VIRGL_SET_INDEX_BUFFER_SIZE(ib) (((ib) ? 2 : 0) + 1) 275b8e80941Smrg#define VIRGL_SET_INDEX_BUFFER_HANDLE 1 276b8e80941Smrg#define VIRGL_SET_INDEX_BUFFER_INDEX_SIZE 2 /* only if sending an IB handle */ 277b8e80941Smrg#define VIRGL_SET_INDEX_BUFFER_OFFSET 3 /* only if sending an IB handle */ 278b8e80941Smrg 279b8e80941Smrg/* constant buffer */ 280b8e80941Smrg#define VIRGL_SET_CONSTANT_BUFFER_SHADER_TYPE 1 281b8e80941Smrg#define VIRGL_SET_CONSTANT_BUFFER_INDEX 2 282b8e80941Smrg#define VIRGL_SET_CONSTANT_BUFFER_DATA_START 3 283b8e80941Smrg 284b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_SIZE 5 285b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_SHADER_TYPE 1 286b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_INDEX 2 287b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_OFFSET 3 288b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_LENGTH 4 289b8e80941Smrg#define VIRGL_SET_UNIFORM_BUFFER_RES_HANDLE 5 290b8e80941Smrg 291b8e80941Smrg/* draw VBO */ 292b8e80941Smrg#define VIRGL_DRAW_VBO_SIZE 12 293b8e80941Smrg#define VIRGL_DRAW_VBO_SIZE_TESS 14 294b8e80941Smrg#define VIRGL_DRAW_VBO_SIZE_INDIRECT 20 295b8e80941Smrg#define VIRGL_DRAW_VBO_START 1 296b8e80941Smrg#define VIRGL_DRAW_VBO_COUNT 2 297b8e80941Smrg#define VIRGL_DRAW_VBO_MODE 3 298b8e80941Smrg#define VIRGL_DRAW_VBO_INDEXED 4 299b8e80941Smrg#define VIRGL_DRAW_VBO_INSTANCE_COUNT 5 300b8e80941Smrg#define VIRGL_DRAW_VBO_INDEX_BIAS 6 301b8e80941Smrg#define VIRGL_DRAW_VBO_START_INSTANCE 7 302b8e80941Smrg#define VIRGL_DRAW_VBO_PRIMITIVE_RESTART 8 303b8e80941Smrg#define VIRGL_DRAW_VBO_RESTART_INDEX 9 304b8e80941Smrg#define VIRGL_DRAW_VBO_MIN_INDEX 10 305b8e80941Smrg#define VIRGL_DRAW_VBO_MAX_INDEX 11 306b8e80941Smrg#define VIRGL_DRAW_VBO_COUNT_FROM_SO 12 307b8e80941Smrg/* tess packet */ 308b8e80941Smrg#define VIRGL_DRAW_VBO_VERTICES_PER_PATCH 13 309b8e80941Smrg#define VIRGL_DRAW_VBO_DRAWID 14 310b8e80941Smrg/* indirect packet */ 311b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_HANDLE 15 312b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_OFFSET 16 313b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_STRIDE 17 314b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18 315b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19 316b8e80941Smrg#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20 317b8e80941Smrg 318b8e80941Smrg/* create surface */ 319b8e80941Smrg#define VIRGL_OBJ_SURFACE_SIZE 5 320b8e80941Smrg#define VIRGL_OBJ_SURFACE_HANDLE 1 321b8e80941Smrg#define VIRGL_OBJ_SURFACE_RES_HANDLE 2 322b8e80941Smrg#define VIRGL_OBJ_SURFACE_FORMAT 3 323b8e80941Smrg#define VIRGL_OBJ_SURFACE_BUFFER_FIRST_ELEMENT 4 324b8e80941Smrg#define VIRGL_OBJ_SURFACE_BUFFER_LAST_ELEMENT 5 325b8e80941Smrg#define VIRGL_OBJ_SURFACE_TEXTURE_LEVEL 4 326b8e80941Smrg#define VIRGL_OBJ_SURFACE_TEXTURE_LAYERS 5 327b8e80941Smrg 328b8e80941Smrg/* create streamout target */ 329b8e80941Smrg#define VIRGL_OBJ_STREAMOUT_SIZE 4 330b8e80941Smrg#define VIRGL_OBJ_STREAMOUT_HANDLE 1 331b8e80941Smrg#define VIRGL_OBJ_STREAMOUT_RES_HANDLE 2 332b8e80941Smrg#define VIRGL_OBJ_STREAMOUT_BUFFER_OFFSET 3 333b8e80941Smrg#define VIRGL_OBJ_STREAMOUT_BUFFER_SIZE 4 334b8e80941Smrg 335b8e80941Smrg/* sampler state */ 336b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_SIZE 9 337b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_HANDLE 1 338b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_S0 2 339b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(x) (((x) & 0x7) << 0) 340b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(x) (((x) & 0x7) << 3) 341b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(x) (((x) & 0x7) << 6) 342b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(x) (((x) & 0x3) << 9) 343b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(x) (((x) & 0x3) << 11) 344b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13) 345b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15) 346b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16) 347b8e80941Smrg#define VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19) 348b8e80941Smrg 349b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3 350b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4 351b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_MAX_LOD 5 352b8e80941Smrg#define VIRGL_OBJ_SAMPLER_STATE_BORDER_COLOR(x) ((x) + 6) /* 6 - 9 */ 353b8e80941Smrg 354b8e80941Smrg 355b8e80941Smrg/* sampler view */ 356b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SIZE 6 357b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_HANDLE 1 358b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_RES_HANDLE 2 359b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_FORMAT 3 360b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_FIRST_ELEMENT 4 361b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_LAST_ELEMENT 5 362b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LAYER 4 363b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LEVEL 5 364b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE 6 365b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(x) (((x) & 0x7) << 0) 366b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(x) (((x) & 0x7) << 3) 367b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(x) (((x) & 0x7) << 6) 368b8e80941Smrg#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(x) (((x) & 0x7) << 9) 369b8e80941Smrg 370b8e80941Smrg/* set sampler views */ 371b8e80941Smrg#define VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views) ((num_views) + 2) 372b8e80941Smrg#define VIRGL_SET_SAMPLER_VIEWS_SHADER_TYPE 1 373b8e80941Smrg#define VIRGL_SET_SAMPLER_VIEWS_START_SLOT 2 374b8e80941Smrg#define VIRGL_SET_SAMPLER_VIEWS_V0_HANDLE 3 375b8e80941Smrg 376b8e80941Smrg/* bind sampler states */ 377b8e80941Smrg#define VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2) 378b8e80941Smrg#define VIRGL_BIND_SAMPLER_STATES_SHADER_TYPE 1 379b8e80941Smrg#define VIRGL_BIND_SAMPLER_STATES_START_SLOT 2 380b8e80941Smrg#define VIRGL_BIND_SAMPLER_STATES_S0_HANDLE 3 381b8e80941Smrg 382b8e80941Smrg/* set stencil reference */ 383b8e80941Smrg#define VIRGL_SET_STENCIL_REF_SIZE 1 384b8e80941Smrg#define VIRGL_SET_STENCIL_REF 1 385b8e80941Smrg#define VIRGL_STENCIL_REF_VAL(f, s) ((f & 0xff) | (((s & 0xff) << 8))) 386b8e80941Smrg 387b8e80941Smrg/* set blend color */ 388b8e80941Smrg#define VIRGL_SET_BLEND_COLOR_SIZE 4 389b8e80941Smrg#define VIRGL_SET_BLEND_COLOR(x) ((x) + 1) 390b8e80941Smrg 391b8e80941Smrg/* set scissor state */ 392b8e80941Smrg#define VIRGL_SET_SCISSOR_STATE_SIZE(x) (1 + 2 * x) 393b8e80941Smrg#define VIRGL_SET_SCISSOR_START_SLOT 1 394b8e80941Smrg#define VIRGL_SET_SCISSOR_MINX_MINY(x) (2 + (x * 2)) 395b8e80941Smrg#define VIRGL_SET_SCISSOR_MAXX_MAXY(x) (3 + (x * 2)) 396b8e80941Smrg 397b8e80941Smrg/* resource copy region */ 398b8e80941Smrg#define VIRGL_CMD_RESOURCE_COPY_REGION_SIZE 13 399b8e80941Smrg#define VIRGL_CMD_RCR_DST_RES_HANDLE 1 400b8e80941Smrg#define VIRGL_CMD_RCR_DST_LEVEL 2 401b8e80941Smrg#define VIRGL_CMD_RCR_DST_X 3 402b8e80941Smrg#define VIRGL_CMD_RCR_DST_Y 4 403b8e80941Smrg#define VIRGL_CMD_RCR_DST_Z 5 404b8e80941Smrg#define VIRGL_CMD_RCR_SRC_RES_HANDLE 6 405b8e80941Smrg#define VIRGL_CMD_RCR_SRC_LEVEL 7 406b8e80941Smrg#define VIRGL_CMD_RCR_SRC_X 8 407b8e80941Smrg#define VIRGL_CMD_RCR_SRC_Y 9 408b8e80941Smrg#define VIRGL_CMD_RCR_SRC_Z 10 409b8e80941Smrg#define VIRGL_CMD_RCR_SRC_W 11 410b8e80941Smrg#define VIRGL_CMD_RCR_SRC_H 12 411b8e80941Smrg#define VIRGL_CMD_RCR_SRC_D 13 412b8e80941Smrg 413b8e80941Smrg/* blit */ 414b8e80941Smrg#define VIRGL_CMD_BLIT_SIZE 21 415b8e80941Smrg#define VIRGL_CMD_BLIT_S0 1 416b8e80941Smrg#define VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0) 417b8e80941Smrg#define VIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8) 418b8e80941Smrg#define VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10) 419b8e80941Smrg#define VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11) 420b8e80941Smrg#define VIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12) 421b8e80941Smrg#define VIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2 422b8e80941Smrg#define VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3 423b8e80941Smrg#define VIRGL_CMD_BLIT_DST_RES_HANDLE 4 424b8e80941Smrg#define VIRGL_CMD_BLIT_DST_LEVEL 5 425b8e80941Smrg#define VIRGL_CMD_BLIT_DST_FORMAT 6 426b8e80941Smrg#define VIRGL_CMD_BLIT_DST_X 7 427b8e80941Smrg#define VIRGL_CMD_BLIT_DST_Y 8 428b8e80941Smrg#define VIRGL_CMD_BLIT_DST_Z 9 429b8e80941Smrg#define VIRGL_CMD_BLIT_DST_W 10 430b8e80941Smrg#define VIRGL_CMD_BLIT_DST_H 11 431b8e80941Smrg#define VIRGL_CMD_BLIT_DST_D 12 432b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_RES_HANDLE 13 433b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_LEVEL 14 434b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_FORMAT 15 435b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_X 16 436b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_Y 17 437b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_Z 18 438b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_W 19 439b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_H 20 440b8e80941Smrg#define VIRGL_CMD_BLIT_SRC_D 21 441b8e80941Smrg 442b8e80941Smrg/* query object */ 443b8e80941Smrg#define VIRGL_OBJ_QUERY_SIZE 4 444b8e80941Smrg#define VIRGL_OBJ_QUERY_HANDLE 1 445b8e80941Smrg#define VIRGL_OBJ_QUERY_TYPE_INDEX 2 446b8e80941Smrg#define VIRGL_OBJ_QUERY_TYPE(x) (x & 0xffff) 447b8e80941Smrg#define VIRGL_OBJ_QUERY_INDEX(x) ((x & 0xffff) << 16) 448b8e80941Smrg#define VIRGL_OBJ_QUERY_OFFSET 3 449b8e80941Smrg#define VIRGL_OBJ_QUERY_RES_HANDLE 4 450b8e80941Smrg 451b8e80941Smrg#define VIRGL_QUERY_BEGIN_HANDLE 1 452b8e80941Smrg 453b8e80941Smrg#define VIRGL_QUERY_END_HANDLE 1 454b8e80941Smrg 455b8e80941Smrg#define VIRGL_QUERY_RESULT_SIZE 2 456b8e80941Smrg#define VIRGL_QUERY_RESULT_HANDLE 1 457b8e80941Smrg#define VIRGL_QUERY_RESULT_WAIT 2 458b8e80941Smrg 459b8e80941Smrg/* render condition */ 460b8e80941Smrg#define VIRGL_RENDER_CONDITION_SIZE 3 461b8e80941Smrg#define VIRGL_RENDER_CONDITION_HANDLE 1 462b8e80941Smrg#define VIRGL_RENDER_CONDITION_CONDITION 2 463b8e80941Smrg#define VIRGL_RENDER_CONDITION_MODE 3 464b8e80941Smrg 465b8e80941Smrg/* resource inline write */ 466b8e80941Smrg#define VIRGL_RESOURCE_IW_RES_HANDLE 1 467b8e80941Smrg#define VIRGL_RESOURCE_IW_LEVEL 2 468b8e80941Smrg#define VIRGL_RESOURCE_IW_USAGE 3 469b8e80941Smrg#define VIRGL_RESOURCE_IW_STRIDE 4 470b8e80941Smrg#define VIRGL_RESOURCE_IW_LAYER_STRIDE 5 471b8e80941Smrg#define VIRGL_RESOURCE_IW_X 6 472b8e80941Smrg#define VIRGL_RESOURCE_IW_Y 7 473b8e80941Smrg#define VIRGL_RESOURCE_IW_Z 8 474b8e80941Smrg#define VIRGL_RESOURCE_IW_W 9 475b8e80941Smrg#define VIRGL_RESOURCE_IW_H 10 476b8e80941Smrg#define VIRGL_RESOURCE_IW_D 11 477b8e80941Smrg#define VIRGL_RESOURCE_IW_DATA_START 12 478b8e80941Smrg 479b8e80941Smrg/* set streamout targets */ 480b8e80941Smrg#define VIRGL_SET_STREAMOUT_TARGETS_APPEND_BITMASK 1 481b8e80941Smrg#define VIRGL_SET_STREAMOUT_TARGETS_H0 2 482b8e80941Smrg 483b8e80941Smrg/* set sample mask */ 484b8e80941Smrg#define VIRGL_SET_SAMPLE_MASK_SIZE 1 485b8e80941Smrg#define VIRGL_SET_SAMPLE_MASK_MASK 1 486b8e80941Smrg 487b8e80941Smrg/* set clip state */ 488b8e80941Smrg#define VIRGL_SET_CLIP_STATE_SIZE 32 489b8e80941Smrg#define VIRGL_SET_CLIP_STATE_C0 1 490b8e80941Smrg 491b8e80941Smrg/* polygon stipple */ 492b8e80941Smrg#define VIRGL_POLYGON_STIPPLE_SIZE 32 493b8e80941Smrg#define VIRGL_POLYGON_STIPPLE_P0 1 494b8e80941Smrg 495b8e80941Smrg#define VIRGL_BIND_SHADER_SIZE 2 496b8e80941Smrg#define VIRGL_BIND_SHADER_HANDLE 1 497b8e80941Smrg#define VIRGL_BIND_SHADER_TYPE 2 498b8e80941Smrg 499b8e80941Smrg/* tess state */ 500b8e80941Smrg#define VIRGL_TESS_STATE_SIZE 6 501b8e80941Smrg 502b8e80941Smrg/* set min samples */ 503b8e80941Smrg#define VIRGL_SET_MIN_SAMPLES_SIZE 1 504b8e80941Smrg#define VIRGL_SET_MIN_SAMPLES_MASK 1 505b8e80941Smrg 506b8e80941Smrg/* set shader buffers */ 507b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE 3 508b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_SIZE(x) (VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE * (x)) + 2 509b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_SHADER_TYPE 1 510b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_START_SLOT 2 511b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_OFFSET(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 3) 512b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4) 513b8e80941Smrg#define VIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5) 514b8e80941Smrg 515b8e80941Smrg/* set shader images */ 516b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5 517b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2 518b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1 519b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_START_SLOT 2 520b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3) 521b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4) 522b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5) 523b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6) 524b8e80941Smrg#define VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7) 525b8e80941Smrg 526b8e80941Smrg/* memory barrier */ 527b8e80941Smrg#define VIRGL_MEMORY_BARRIER_SIZE 1 528b8e80941Smrg#define VIRGL_MEMORY_BARRIER_FLAGS 1 529b8e80941Smrg 530b8e80941Smrg/* launch grid */ 531b8e80941Smrg#define VIRGL_LAUNCH_GRID_SIZE 8 532b8e80941Smrg#define VIRGL_LAUNCH_BLOCK_X 1 533b8e80941Smrg#define VIRGL_LAUNCH_BLOCK_Y 2 534b8e80941Smrg#define VIRGL_LAUNCH_BLOCK_Z 3 535b8e80941Smrg#define VIRGL_LAUNCH_GRID_X 4 536b8e80941Smrg#define VIRGL_LAUNCH_GRID_Y 5 537b8e80941Smrg#define VIRGL_LAUNCH_GRID_Z 6 538b8e80941Smrg#define VIRGL_LAUNCH_INDIRECT_HANDLE 7 539b8e80941Smrg#define VIRGL_LAUNCH_INDIRECT_OFFSET 8 540b8e80941Smrg 541b8e80941Smrg/* framebuffer state no attachment */ 542b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE 2 543b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH_HEIGHT 1 544b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH(x) (x & 0xffff) 545b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_HEIGHT(x) ((x >> 16) & 0xffff) 546b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS_SAMPLES 2 547b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS(x) (x & 0xffff) 548b8e80941Smrg#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SAMPLES(x) ((x >> 16) & 0xff) 549b8e80941Smrg 550b8e80941Smrg/* texture barrier */ 551b8e80941Smrg#define VIRGL_TEXTURE_BARRIER_SIZE 1 552b8e80941Smrg#define VIRGL_TEXTURE_BARRIER_FLAGS 1 553b8e80941Smrg 554b8e80941Smrg/* hw atomics */ 555b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE 3 556b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_SIZE(x) (VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE * (x)) + 1 557b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_START_SLOT 1 558b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_OFFSET(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 2) 559b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_LENGTH(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 3) 560b8e80941Smrg#define VIRGL_SET_ATOMIC_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 4) 561b8e80941Smrg 562b8e80941Smrg/* qbo */ 563b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_SIZE 6 564b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_HANDLE 1 565b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_QBO_HANDLE 2 566b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_WAIT 3 567b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_RESULT_TYPE 4 568b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_OFFSET 5 569b8e80941Smrg#define VIRGL_QUERY_RESULT_QBO_INDEX 6 570b8e80941Smrg 571b8e80941Smrg#define VIRGL_TRANSFER_TO_HOST 1 572b8e80941Smrg#define VIRGL_TRANSFER_FROM_HOST 2 573b8e80941Smrg 574b8e80941Smrg/* Transfer */ 575b8e80941Smrg#define VIRGL_TRANSFER3D_SIZE 13 576b8e80941Smrg/* The first 11 dwords are the same as VIRGL_RESOURCE_IW_* */ 577b8e80941Smrg#define VIRGL_TRANSFER3D_DATA_OFFSET 12 578b8e80941Smrg#define VIRGL_TRANSFER3D_DIRECTION 13 579b8e80941Smrg 580b8e80941Smrg#endif 581