1b8e80941Smrg/*
2b8e80941Smrg * Copyright © 2018 Intel Corporation
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the next
12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the
13b8e80941Smrg * Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21b8e80941Smrg * IN THE SOFTWARE.
22b8e80941Smrg */
23b8e80941Smrg
24b8e80941Smrg#ifndef GEN_GEM_H
25b8e80941Smrg#define GEN_GEM_H
26b8e80941Smrg
27b8e80941Smrg#include <stdint.h>
28b8e80941Smrg
29b8e80941Smrgstatic inline uint64_t
30b8e80941Smrggen_canonical_address(uint64_t v)
31b8e80941Smrg{
32b8e80941Smrg   /* From the Broadwell PRM Vol. 2a, MI_LOAD_REGISTER_MEM::MemoryAddress:
33b8e80941Smrg    *
34b8e80941Smrg    *    "This field specifies the address of the memory location where the
35b8e80941Smrg    *    register value specified in the DWord above will read from. The
36b8e80941Smrg    *    address specifies the DWord location of the data. Range =
37b8e80941Smrg    *    GraphicsVirtualAddress[63:2] for a DWord register GraphicsAddress
38b8e80941Smrg    *    [63:48] are ignored by the HW and assumed to be in correct
39b8e80941Smrg    *    canonical form [63:48] == [47]."
40b8e80941Smrg    */
41b8e80941Smrg   const int shift = 63 - 47;
42b8e80941Smrg   return (int64_t)(v << shift) >> shift;
43b8e80941Smrg}
44b8e80941Smrg
45b8e80941Smrg/**
46b8e80941Smrg * This returns a 48-bit address with the high 16 bits zeroed.
47b8e80941Smrg *
48b8e80941Smrg * It's the opposite of gen_canonicalize_address.
49b8e80941Smrg */
50b8e80941Smrgstatic inline uint64_t
51b8e80941Smrggen_48b_address(uint64_t v)
52b8e80941Smrg{
53b8e80941Smrg   const int shift = 63 - 47;
54b8e80941Smrg   return (uint64_t)(v << shift) >> shift;
55b8e80941Smrg}
56b8e80941Smrg
57b8e80941Smrg#endif /* GEN_GEM_H */
58