1/* 2 * Copyright © 2015-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "brw_compiler.h" 25#include "brw_shader.h" 26#include "brw_eu.h" 27#include "dev/gen_debug.h" 28#include "compiler/nir/nir.h" 29#include "main/errors.h" 30#include "util/debug.h" 31 32#define COMMON_OPTIONS \ 33 .lower_sub = true, \ 34 .lower_fdiv = true, \ 35 .lower_scmp = true, \ 36 .lower_flrp16 = true, \ 37 .lower_fmod16 = true, \ 38 .lower_fmod32 = true, \ 39 .lower_fmod64 = false, \ 40 .lower_bitfield_extract = true, \ 41 .lower_bitfield_insert = true, \ 42 .lower_uadd_carry = true, \ 43 .lower_usub_borrow = true, \ 44 .lower_fdiv = true, \ 45 .lower_flrp64 = true, \ 46 .lower_isign = true, \ 47 .lower_ldexp = true, \ 48 .lower_device_index_to_zero = true, \ 49 .native_integers = true, \ 50 .use_interpolated_input_intrinsics = true, \ 51 .vertex_id_zero_based = true, \ 52 .lower_base_vertex = true 53 54#define COMMON_SCALAR_OPTIONS \ 55 .lower_pack_half_2x16 = true, \ 56 .lower_pack_snorm_2x16 = true, \ 57 .lower_pack_snorm_4x8 = true, \ 58 .lower_pack_unorm_2x16 = true, \ 59 .lower_pack_unorm_4x8 = true, \ 60 .lower_unpack_half_2x16 = true, \ 61 .lower_unpack_snorm_2x16 = true, \ 62 .lower_unpack_snorm_4x8 = true, \ 63 .lower_unpack_unorm_2x16 = true, \ 64 .lower_unpack_unorm_4x8 = true, \ 65 .max_unroll_iterations = 32 66 67static const struct nir_shader_compiler_options scalar_nir_options = { 68 COMMON_OPTIONS, 69 COMMON_SCALAR_OPTIONS, 70}; 71 72static const struct nir_shader_compiler_options vector_nir_options = { 73 COMMON_OPTIONS, 74 75 /* In the vec4 backend, our dpN instruction replicates its result to all the 76 * components of a vec4. We would like NIR to give us replicated fdot 77 * instructions because it can optimize better for us. 78 */ 79 .fdot_replicates = true, 80 81 .lower_pack_snorm_2x16 = true, 82 .lower_pack_unorm_2x16 = true, 83 .lower_unpack_snorm_2x16 = true, 84 .lower_unpack_unorm_2x16 = true, 85 .lower_extract_byte = true, 86 .lower_extract_word = true, 87 .max_unroll_iterations = 32, 88}; 89 90struct brw_compiler * 91brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) 92{ 93 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler); 94 95 compiler->devinfo = devinfo; 96 97 brw_fs_alloc_reg_sets(compiler); 98 brw_vec4_alloc_reg_set(compiler); 99 brw_init_compaction_tables(devinfo); 100 101 compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false); 102 103 if (devinfo->gen >= 10) { 104 /* We don't support vec4 mode on Cannonlake. */ 105 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++) 106 compiler->scalar_stage[i] = true; 107 } else { 108 compiler->scalar_stage[MESA_SHADER_VERTEX] = 109 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true); 110 compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = 111 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true); 112 compiler->scalar_stage[MESA_SHADER_TESS_EVAL] = 113 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true); 114 compiler->scalar_stage[MESA_SHADER_GEOMETRY] = 115 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true); 116 compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true; 117 compiler->scalar_stage[MESA_SHADER_COMPUTE] = true; 118 } 119 120 nir_lower_int64_options int64_options = 121 nir_lower_imul64 | 122 nir_lower_isign64 | 123 nir_lower_divmod64 | 124 nir_lower_imul_high64; 125 nir_lower_doubles_options fp64_options = 126 nir_lower_drcp | 127 nir_lower_dsqrt | 128 nir_lower_drsq | 129 nir_lower_dtrunc | 130 nir_lower_dfloor | 131 nir_lower_dceil | 132 nir_lower_dfract | 133 nir_lower_dround_even | 134 nir_lower_dmod; 135 136 if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) { 137 int64_options |= nir_lower_mov64 | 138 nir_lower_icmp64 | 139 nir_lower_iadd64 | 140 nir_lower_iabs64 | 141 nir_lower_ineg64 | 142 nir_lower_logic64 | 143 nir_lower_minmax64 | 144 nir_lower_shift64 | 145 nir_lower_extract64; 146 fp64_options |= nir_lower_fp64_full_software; 147 } 148 149 /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that 150 * destination type can be Quadword and source type Doubleword for Gen8 and 151 * Gen9. So, lower 64 bit multiply instruction on rest of the platforms. 152 */ 153 if (devinfo->gen < 8 || devinfo->gen > 9) 154 int64_options |= nir_lower_imul_2x32_64; 155 156 /* We want the GLSL compiler to emit code that uses condition codes */ 157 for (int i = 0; i < MESA_SHADER_STAGES; i++) { 158 compiler->glsl_compiler_options[i].MaxUnrollIterations = 0; 159 compiler->glsl_compiler_options[i].MaxIfDepth = 160 devinfo->gen < 6 ? 16 : UINT_MAX; 161 162 compiler->glsl_compiler_options[i].EmitNoIndirectInput = true; 163 compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false; 164 165 bool is_scalar = compiler->scalar_stage[i]; 166 167 compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar; 168 compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar; 169 compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar; 170 171 struct nir_shader_compiler_options *nir_options = 172 rzalloc(compiler, struct nir_shader_compiler_options); 173 if (is_scalar) { 174 *nir_options = scalar_nir_options; 175 176 if (devinfo->gen >= 11) { 177 nir_options->lower_flrp32 = true; 178 } 179 } else { 180 *nir_options = vector_nir_options; 181 182 if (devinfo->gen < 6) { 183 /* Prior to Gen6, there are no three source operations. */ 184 nir_options->lower_flrp32 = true; 185 } 186 } 187 188 /* Prior to Gen6, there are no three source operations. */ 189 nir_options->lower_ffma = devinfo->gen < 6; 190 191 nir_options->lower_bitfield_reverse = devinfo->gen < 7; 192 193 nir_options->lower_int64_options = int64_options; 194 nir_options->lower_doubles_options = fp64_options; 195 compiler->glsl_compiler_options[i].NirOptions = nir_options; 196 197 compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true; 198 } 199 200 compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false; 201 compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false; 202 compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false; 203 204 if (compiler->scalar_stage[MESA_SHADER_GEOMETRY]) 205 compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false; 206 207 return compiler; 208} 209 210static void 211insert_u64_bit(uint64_t *val, bool add) 212{ 213 *val = (*val << 1) | !!add; 214} 215 216uint64_t 217brw_get_compiler_config_value(const struct brw_compiler *compiler) 218{ 219 uint64_t config = 0; 220 insert_u64_bit(&config, compiler->precise_trig); 221 if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) { 222 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]); 223 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]); 224 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]); 225 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]); 226 } 227 uint64_t debug_bits = INTEL_DEBUG; 228 uint64_t mask = DEBUG_DISK_CACHE_MASK; 229 while (mask != 0) { 230 const uint64_t bit = 1ULL << (ffsll(mask) - 1); 231 insert_u64_bit(&config, (debug_bits & bit) != 0); 232 mask &= ~bit; 233 } 234 return config; 235} 236 237unsigned 238brw_prog_data_size(gl_shader_stage stage) 239{ 240 STATIC_ASSERT(MESA_SHADER_VERTEX == 0); 241 STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1); 242 STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2); 243 STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3); 244 STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4); 245 STATIC_ASSERT(MESA_SHADER_COMPUTE == 5); 246 static const size_t stage_sizes[] = { 247 sizeof(struct brw_vs_prog_data), 248 sizeof(struct brw_tcs_prog_data), 249 sizeof(struct brw_tes_prog_data), 250 sizeof(struct brw_gs_prog_data), 251 sizeof(struct brw_wm_prog_data), 252 sizeof(struct brw_cs_prog_data), 253 }; 254 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); 255 return stage_sizes[stage]; 256} 257 258unsigned 259brw_prog_key_size(gl_shader_stage stage) 260{ 261 static const size_t stage_sizes[] = { 262 sizeof(struct brw_vs_prog_key), 263 sizeof(struct brw_tcs_prog_key), 264 sizeof(struct brw_tes_prog_key), 265 sizeof(struct brw_gs_prog_key), 266 sizeof(struct brw_wm_prog_key), 267 sizeof(struct brw_cs_prog_key), 268 }; 269 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); 270 return stage_sizes[stage]; 271} 272