1/* 2 * Copyright © 2010 - 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef BRW_COMPILER_H 25#define BRW_COMPILER_H 26 27#include <stdio.h> 28#include "dev/gen_device_info.h" 29#include "main/macros.h" 30#include "main/mtypes.h" 31#include "util/ralloc.h" 32 33#ifdef __cplusplus 34extern "C" { 35#endif 36 37struct ra_regs; 38struct nir_shader; 39struct brw_program; 40 41struct brw_compiler { 42 const struct gen_device_info *devinfo; 43 44 struct { 45 struct ra_regs *regs; 46 47 /** 48 * Array of the ra classes for the unaligned contiguous register 49 * block sizes used. 50 */ 51 int *classes; 52 53 /** 54 * Mapping for register-allocated objects in *regs to the first 55 * GRF for that object. 56 */ 57 uint8_t *ra_reg_to_grf; 58 } vec4_reg_set; 59 60 struct { 61 struct ra_regs *regs; 62 63 /** 64 * Array of the ra classes for the unaligned contiguous register 65 * block sizes used, indexed by register size. 66 */ 67 int classes[16]; 68 69 /** 70 * Mapping from classes to ra_reg ranges. Each of the per-size 71 * classes corresponds to a range of ra_reg nodes. This array stores 72 * those ranges in the form of first ra_reg in each class and the 73 * total number of ra_reg elements in the last array element. This 74 * way the range of the i'th class is given by: 75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] ) 76 */ 77 int class_to_ra_reg_range[17]; 78 79 /** 80 * Mapping for register-allocated objects in *regs to the first 81 * GRF for that object. 82 */ 83 uint8_t *ra_reg_to_grf; 84 85 /** 86 * ra class for the aligned pairs we use for PLN, which doesn't 87 * appear in *classes. 88 */ 89 int aligned_pairs_class; 90 } fs_reg_sets[3]; 91 92 void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); 93 void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); 94 95 bool scalar_stage[MESA_SHADER_STAGES]; 96 struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES]; 97 98 /** 99 * Apply workarounds for SIN and COS output range problems. 100 * This can negatively impact performance. 101 */ 102 bool precise_trig; 103 104 /** 105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State 106 * Base Address? (If not, it's a normal GPU address.) 107 */ 108 bool constant_buffer_0_is_relative; 109 110 /** 111 * Whether or not the driver supports pull constants. If not, the compiler 112 * will attempt to push everything. 113 */ 114 bool supports_pull_constants; 115 116 /** 117 * Whether or not the driver supports NIR shader constants. This controls 118 * whether nir_opt_large_constants will be run. 119 */ 120 bool supports_shader_constants; 121}; 122 123/** 124 * We use a constant subgroup size of 32. It really only needs to be a 125 * maximum and, since we do SIMD32 for compute shaders in some cases, it 126 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a 127 * subgroup size of 32 but will act as if 16 or 24 of those channels are 128 * disabled. 129 */ 130#define BRW_SUBGROUP_SIZE 32 131 132/** 133 * Program key structures. 134 * 135 * When drawing, we look for the currently bound shaders in the program 136 * cache. This is essentially a hash table lookup, and these are the keys. 137 * 138 * Sometimes OpenGL features specified as state need to be simulated via 139 * shader code, due to a mismatch between the API and the hardware. This 140 * is often referred to as "non-orthagonal state" or "NOS". We store NOS 141 * in the program key so it's considered when searching for a program. If 142 * we haven't seen a particular combination before, we have to recompile a 143 * new specialized version. 144 * 145 * Shader compilation should not look up state in gl_context directly, but 146 * instead use the copy in the program key. This guarantees recompiles will 147 * happen correctly. 148 * 149 * @{ 150 */ 151 152enum PACKED gen6_gather_sampler_wa { 153 WA_SIGN = 1, /* whether we need to sign extend */ 154 WA_8BIT = 2, /* if we have an 8bit format needing wa */ 155 WA_16BIT = 4, /* if we have a 16bit format needing wa */ 156}; 157 158/** 159 * Sampler information needed by VS, WM, and GS program cache keys. 160 */ 161struct brw_sampler_prog_key_data { 162 /** 163 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles. 164 */ 165 uint16_t swizzles[MAX_SAMPLERS]; 166 167 uint32_t gl_clamp_mask[3]; 168 169 /** 170 * For RG32F, gather4's channel select is broken. 171 */ 172 uint32_t gather_channel_quirk_mask; 173 174 /** 175 * Whether this sampler uses the compressed multisample surface layout. 176 */ 177 uint32_t compressed_multisample_layout_mask; 178 179 /** 180 * Whether this sampler is using 16x multisampling. If so fetching from 181 * this sampler will be handled with a different instruction, ld2dms_w 182 * instead of ld2dms. 183 */ 184 uint32_t msaa_16; 185 186 /** 187 * For Sandybridge, which shader w/a we need for gather quirks. 188 */ 189 enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS]; 190 191 /** 192 * Texture units that have a YUV image bound. 193 */ 194 uint32_t y_u_v_image_mask; 195 uint32_t y_uv_image_mask; 196 uint32_t yx_xuxv_image_mask; 197 uint32_t xy_uxvx_image_mask; 198 uint32_t ayuv_image_mask; 199 uint32_t xyuv_image_mask; 200 201 /* Scale factor for each texture. */ 202 float scale_factors[32]; 203}; 204 205/** 206 * The VF can't natively handle certain types of attributes, such as GL_FIXED 207 * or most 10_10_10_2 types. These flags enable various VS workarounds to 208 * "fix" attributes at the beginning of shaders. 209 */ 210#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */ 211#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */ 212#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */ 213#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */ 214#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */ 215 216/** 217 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range 218 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user 219 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input 220 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0. 221 */ 222#define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX 223#define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28) 224 225/** The program key for Vertex Shaders. */ 226struct brw_vs_prog_key { 227 unsigned program_string_id; 228 229 /** 230 * Per-attribute workaround flags 231 * 232 * For each attribute, a combination of BRW_ATTRIB_WA_*. 233 * 234 * For OpenGL, where we expose a maximum of 16 user input atttributes 235 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan 236 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can 237 * expose up to 28 user input vertex attributes that are mapped to slots 238 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large 239 * enough to hold this many slots. 240 */ 241 uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)]; 242 243 bool copy_edgeflag:1; 244 245 bool clamp_vertex_color:1; 246 247 /** 248 * How many user clipping planes are being uploaded to the vertex shader as 249 * push constants. 250 * 251 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to 252 * clip distances. 253 */ 254 unsigned nr_userclip_plane_consts:4; 255 256 /** 257 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates 258 * are going to be replaced with point coordinates (as a consequence of a 259 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because 260 * our SF thread requires exact matching between VS outputs and FS inputs, 261 * these texture coordinates will need to be unconditionally included in 262 * the VUE, even if they aren't written by the vertex shader. 263 */ 264 uint8_t point_coord_replace; 265 266 struct brw_sampler_prog_key_data tex; 267}; 268 269/** The program key for Tessellation Control Shaders. */ 270struct brw_tcs_prog_key 271{ 272 unsigned program_string_id; 273 274 GLenum tes_primitive_mode; 275 276 unsigned input_vertices; 277 278 /** A bitfield of per-patch outputs written. */ 279 uint32_t patch_outputs_written; 280 281 /** A bitfield of per-vertex outputs written. */ 282 uint64_t outputs_written; 283 284 bool quads_workaround; 285 286 struct brw_sampler_prog_key_data tex; 287}; 288 289/** The program key for Tessellation Evaluation Shaders. */ 290struct brw_tes_prog_key 291{ 292 unsigned program_string_id; 293 294 /** A bitfield of per-patch inputs read. */ 295 uint32_t patch_inputs_read; 296 297 /** A bitfield of per-vertex inputs read. */ 298 uint64_t inputs_read; 299 300 struct brw_sampler_prog_key_data tex; 301}; 302 303/** The program key for Geometry Shaders. */ 304struct brw_gs_prog_key 305{ 306 unsigned program_string_id; 307 308 struct brw_sampler_prog_key_data tex; 309}; 310 311enum brw_sf_primitive { 312 BRW_SF_PRIM_POINTS = 0, 313 BRW_SF_PRIM_LINES = 1, 314 BRW_SF_PRIM_TRIANGLES = 2, 315 BRW_SF_PRIM_UNFILLED_TRIS = 3, 316}; 317 318struct brw_sf_prog_key { 319 uint64_t attrs; 320 bool contains_flat_varying; 321 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ 322 uint8_t point_sprite_coord_replace; 323 enum brw_sf_primitive primitive:2; 324 bool do_twoside_color:1; 325 bool frontface_ccw:1; 326 bool do_point_sprite:1; 327 bool do_point_coord:1; 328 bool sprite_origin_lower_left:1; 329 bool userclip_active:1; 330}; 331 332enum brw_clip_mode { 333 BRW_CLIP_MODE_NORMAL = 0, 334 BRW_CLIP_MODE_CLIP_ALL = 1, 335 BRW_CLIP_MODE_CLIP_NON_REJECTED = 2, 336 BRW_CLIP_MODE_REJECT_ALL = 3, 337 BRW_CLIP_MODE_ACCEPT_ALL = 4, 338 BRW_CLIP_MODE_KERNEL_CLIP = 5, 339}; 340 341enum brw_clip_fill_mode { 342 BRW_CLIP_FILL_MODE_LINE = 0, 343 BRW_CLIP_FILL_MODE_POINT = 1, 344 BRW_CLIP_FILL_MODE_FILL = 2, 345 BRW_CLIP_FILL_MODE_CULL = 3, 346}; 347 348/* Note that if unfilled primitives are being emitted, we have to fix 349 * up polygon offset and flatshading at this point: 350 */ 351struct brw_clip_prog_key { 352 uint64_t attrs; 353 bool contains_flat_varying; 354 bool contains_noperspective_varying; 355 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ 356 unsigned primitive:4; 357 unsigned nr_userclip:4; 358 bool pv_first:1; 359 bool do_unfilled:1; 360 enum brw_clip_fill_mode fill_cw:2; /* includes cull information */ 361 enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */ 362 bool offset_cw:1; 363 bool offset_ccw:1; 364 bool copy_bfc_cw:1; 365 bool copy_bfc_ccw:1; 366 enum brw_clip_mode clip_mode:3; 367 368 float offset_factor; 369 float offset_units; 370 float offset_clamp; 371}; 372 373/* A big lookup table is used to figure out which and how many 374 * additional regs will inserted before the main payload in the WM 375 * program execution. These mainly relate to depth and stencil 376 * processing and the early-depth-test optimization. 377 */ 378enum brw_wm_iz_bits { 379 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1, 380 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2, 381 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4, 382 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8, 383 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10, 384 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20, 385 BRW_WM_IZ_BIT_MAX = 0x40 386}; 387 388enum brw_wm_aa_enable { 389 BRW_WM_AA_NEVER, 390 BRW_WM_AA_SOMETIMES, 391 BRW_WM_AA_ALWAYS 392}; 393 394/** The program key for Fragment/Pixel Shaders. */ 395struct brw_wm_prog_key { 396 /* Some collection of BRW_WM_IZ_* */ 397 uint8_t iz_lookup; 398 bool stats_wm:1; 399 bool flat_shade:1; 400 unsigned nr_color_regions:5; 401 bool alpha_test_replicate_alpha:1; 402 bool alpha_to_coverage:1; 403 bool clamp_fragment_color:1; 404 bool persample_interp:1; 405 bool multisample_fbo:1; 406 bool frag_coord_adds_sample_pos:1; 407 enum brw_wm_aa_enable line_aa:2; 408 bool high_quality_derivatives:1; 409 bool force_dual_color_blend:1; 410 bool coherent_fb_fetch:1; 411 412 uint8_t color_outputs_valid; 413 uint64_t input_slots_valid; 414 unsigned program_string_id; 415 GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */ 416 float alpha_test_ref; 417 418 struct brw_sampler_prog_key_data tex; 419}; 420 421struct brw_cs_prog_key { 422 uint32_t program_string_id; 423 struct brw_sampler_prog_key_data tex; 424}; 425 426/* brw_any_prog_key is any of the keys that map to an API stage */ 427union brw_any_prog_key { 428 struct brw_vs_prog_key vs; 429 struct brw_tcs_prog_key tcs; 430 struct brw_tes_prog_key tes; 431 struct brw_gs_prog_key gs; 432 struct brw_wm_prog_key wm; 433 struct brw_cs_prog_key cs; 434}; 435 436/* 437 * Image metadata structure as laid out in the shader parameter 438 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be 439 * able to use them. That's okay because the padding and any unused 440 * entries [most of them except when we're doing untyped surface 441 * access] will be removed by the uniform packing pass. 442 */ 443#define BRW_IMAGE_PARAM_OFFSET_OFFSET 0 444#define BRW_IMAGE_PARAM_SIZE_OFFSET 4 445#define BRW_IMAGE_PARAM_STRIDE_OFFSET 8 446#define BRW_IMAGE_PARAM_TILING_OFFSET 12 447#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16 448#define BRW_IMAGE_PARAM_SIZE 20 449 450struct brw_image_param { 451 /** Offset applied to the X and Y surface coordinates. */ 452 uint32_t offset[2]; 453 454 /** Surface X, Y and Z dimensions. */ 455 uint32_t size[3]; 456 457 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in 458 * pixels, vertical slice stride in pixels. 459 */ 460 uint32_t stride[4]; 461 462 /** Log2 of the tiling modulus in the X, Y and Z dimension. */ 463 uint32_t tiling[3]; 464 465 /** 466 * Right shift to apply for bit 6 address swizzling. Two different 467 * swizzles can be specified and will be applied one after the other. The 468 * resulting address will be: 469 * 470 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^ 471 * (addr >> swizzling[1]))) 472 * 473 * Use \c 0xff if any of the swizzles is not required. 474 */ 475 uint32_t swizzling[2]; 476}; 477 478/** Max number of render targets in a shader */ 479#define BRW_MAX_DRAW_BUFFERS 8 480 481/** 482 * Max number of binding table entries used for stream output. 483 * 484 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the 485 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64. 486 * 487 * On Gen6, the size of transform feedback data is limited not by the number 488 * of components but by the number of binding table entries we set aside. We 489 * use one binding table entry for a float, one entry for a vector, and one 490 * entry per matrix column. Since the only way we can communicate our 491 * transform feedback capabilities to the client is via 492 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the 493 * worst case, in which all the varyings are floats, so we use up one binding 494 * table entry per component. Therefore we need to set aside at least 64 495 * binding table entries for use by transform feedback. 496 * 497 * Note: since we don't currently pack varyings, it is currently impossible 498 * for the client to actually use up all of these binding table entries--if 499 * all of their varyings were floats, they would run out of varying slots and 500 * fail to link. But that's a bug, so it seems prudent to go ahead and 501 * allocate the number of binding table entries we will need once the bug is 502 * fixed. 503 */ 504#define BRW_MAX_SOL_BINDINGS 64 505 506/** 507 * Binding table index for the first gen6 SOL binding. 508 */ 509#define BRW_GEN6_SOL_BINDING_START 0 510 511/** 512 * Stride in bytes between shader_time entries. 513 * 514 * We separate entries by a cacheline to reduce traffic between EUs writing to 515 * different entries. 516 */ 517#define BRW_SHADER_TIME_STRIDE 64 518 519struct brw_ubo_range 520{ 521 uint16_t block; 522 uint8_t start; 523 uint8_t length; 524}; 525 526/* We reserve the first 2^16 values for builtins */ 527#define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0) 528 529enum brw_param_builtin { 530 BRW_PARAM_BUILTIN_ZERO, 531 532 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X, 533 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y, 534 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z, 535 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W, 536 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X, 537 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y, 538 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z, 539 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W, 540 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X, 541 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y, 542 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z, 543 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W, 544 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X, 545 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y, 546 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z, 547 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W, 548 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X, 549 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y, 550 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z, 551 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W, 552 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X, 553 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y, 554 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z, 555 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W, 556 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X, 557 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y, 558 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z, 559 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W, 560 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X, 561 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y, 562 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z, 563 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W, 564 565 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X, 566 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y, 567 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z, 568 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W, 569 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X, 570 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y, 571 572 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN, 573 574 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X, 575 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y, 576 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z, 577 BRW_PARAM_BUILTIN_SUBGROUP_ID, 578}; 579 580#define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \ 581 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp)) 582 583#define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \ 584 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \ 585 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W) 586 587#define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \ 588 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2) 589 590#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \ 591 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3) 592 593struct brw_stage_prog_data { 594 struct { 595 /** size of our binding table. */ 596 uint32_t size_bytes; 597 598 /** @{ 599 * surface indices for the various groups of surfaces 600 */ 601 uint32_t pull_constants_start; 602 uint32_t texture_start; 603 uint32_t gather_texture_start; 604 uint32_t ubo_start; 605 uint32_t ssbo_start; 606 uint32_t image_start; 607 uint32_t shader_time_start; 608 uint32_t plane_start[3]; 609 /** @} */ 610 } binding_table; 611 612 struct brw_ubo_range ubo_ranges[4]; 613 614 GLuint nr_params; /**< number of float params/constants */ 615 GLuint nr_pull_params; 616 617 unsigned curb_read_length; 618 unsigned total_scratch; 619 unsigned total_shared; 620 621 unsigned program_size; 622 623 /** 624 * Register where the thread expects to find input data from the URB 625 * (typically uniforms, followed by vertex or fragment attributes). 626 */ 627 unsigned dispatch_grf_start_reg; 628 629 bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */ 630 631 /* 32-bit identifiers for all push/pull parameters. These can be anything 632 * the driver wishes them to be; the core of the back-end compiler simply 633 * re-arranges them. The one restriction is that the bottom 2^16 values 634 * are reserved for builtins defined in the brw_param_builtin enum defined 635 * above. 636 */ 637 uint32_t *param; 638 uint32_t *pull_param; 639}; 640 641static inline uint32_t * 642brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data, 643 unsigned nr_new_params) 644{ 645 unsigned old_nr_params = prog_data->nr_params; 646 prog_data->nr_params += nr_new_params; 647 prog_data->param = reralloc(ralloc_parent(prog_data->param), 648 prog_data->param, uint32_t, 649 prog_data->nr_params); 650 return prog_data->param + old_nr_params; 651} 652 653enum brw_barycentric_mode { 654 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0, 655 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1, 656 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2, 657 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3, 658 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4, 659 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5, 660 BRW_BARYCENTRIC_MODE_COUNT = 6 661}; 662#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \ 663 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \ 664 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \ 665 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE)) 666 667enum brw_pixel_shader_computed_depth_mode { 668 BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */ 669 BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */ 670 BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */ 671 BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */ 672}; 673 674/* Data about a particular attempt to compile a program. Note that 675 * there can be many of these, each in a different GL state 676 * corresponding to a different brw_wm_prog_key struct, with different 677 * compiled programs. 678 */ 679struct brw_wm_prog_data { 680 struct brw_stage_prog_data base; 681 682 GLuint num_varying_inputs; 683 684 uint8_t reg_blocks_8; 685 uint8_t reg_blocks_16; 686 uint8_t reg_blocks_32; 687 688 uint8_t dispatch_grf_start_reg_16; 689 uint8_t dispatch_grf_start_reg_32; 690 uint32_t prog_offset_16; 691 uint32_t prog_offset_32; 692 693 struct { 694 /** @{ 695 * surface indices the WM-specific surfaces 696 */ 697 uint32_t render_target_read_start; 698 /** @} */ 699 } binding_table; 700 701 uint8_t computed_depth_mode; 702 bool computed_stencil; 703 704 bool early_fragment_tests; 705 bool post_depth_coverage; 706 bool inner_coverage; 707 bool dispatch_8; 708 bool dispatch_16; 709 bool dispatch_32; 710 bool dual_src_blend; 711 bool replicate_alpha; 712 bool persample_dispatch; 713 bool uses_pos_offset; 714 bool uses_omask; 715 bool uses_kill; 716 bool uses_src_depth; 717 bool uses_src_w; 718 bool uses_sample_mask; 719 bool has_render_target_reads; 720 bool has_side_effects; 721 bool pulls_bary; 722 723 bool contains_flat_varying; 724 bool contains_noperspective_varying; 725 726 /** 727 * Mask of which interpolation modes are required by the fragment shader. 728 * Used in hardware setup on gen6+. 729 */ 730 uint32_t barycentric_interp_modes; 731 732 /** 733 * Mask of which FS inputs are marked flat by the shader source. This is 734 * needed for setting up 3DSTATE_SF/SBE. 735 */ 736 uint32_t flat_inputs; 737 738 /* Mapping of VUE slots to interpolation modes. 739 * Used by the Gen4-5 clip/sf/wm stages. 740 */ 741 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */ 742 743 /** 744 * Map from gl_varying_slot to the position within the FS setup data 745 * payload where the varying's attribute vertex deltas should be delivered. 746 * For varying slots that are not used by the FS, the value is -1. 747 */ 748 int urb_setup[VARYING_SLOT_MAX]; 749}; 750 751/** Returns the SIMD width corresponding to a given KSP index 752 * 753 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for 754 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to 755 * kernel start pointer (KSP) indices that is based on what dispatch widths 756 * are enabled. This function provides, effectively, the reverse mapping. 757 * 758 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD 759 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned. 760 */ 761static inline unsigned 762brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled, 763 bool simd16_enabled, bool simd32_enabled) 764{ 765 /* This function strictly ignores contiguous dispatch */ 766 switch (ksp_idx) { 767 case 0: 768 return simd8_enabled ? 8 : 769 (simd16_enabled && !simd32_enabled) ? 16 : 770 (simd32_enabled && !simd16_enabled) ? 32 : 0; 771 case 1: 772 return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0; 773 case 2: 774 return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0; 775 default: 776 unreachable("Invalid KSP index"); 777 } 778} 779 780#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \ 781 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \ 782 (wm_state)._16PixelDispatchEnable, \ 783 (wm_state)._32PixelDispatchEnable) 784 785#define brw_wm_state_has_ksp(wm_state, ksp_idx) \ 786 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0) 787 788static inline uint32_t 789_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data, 790 unsigned simd_width) 791{ 792 switch (simd_width) { 793 case 8: return 0; 794 case 16: return prog_data->prog_offset_16; 795 case 32: return prog_data->prog_offset_32; 796 default: return 0; 797 } 798} 799 800#define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \ 801 _brw_wm_prog_data_prog_offset(prog_data, \ 802 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) 803 804static inline uint8_t 805_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data, 806 unsigned simd_width) 807{ 808 switch (simd_width) { 809 case 8: return prog_data->base.dispatch_grf_start_reg; 810 case 16: return prog_data->dispatch_grf_start_reg_16; 811 case 32: return prog_data->dispatch_grf_start_reg_32; 812 default: return 0; 813 } 814} 815 816#define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \ 817 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \ 818 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) 819 820static inline uint8_t 821_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data, 822 unsigned simd_width) 823{ 824 switch (simd_width) { 825 case 8: return prog_data->reg_blocks_8; 826 case 16: return prog_data->reg_blocks_16; 827 case 32: return prog_data->reg_blocks_32; 828 default: return 0; 829 } 830} 831 832#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \ 833 _brw_wm_prog_data_reg_blocks(prog_data, \ 834 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx)) 835 836struct brw_push_const_block { 837 unsigned dwords; /* Dword count, not reg aligned */ 838 unsigned regs; 839 unsigned size; /* Bytes, register aligned */ 840}; 841 842struct brw_cs_prog_data { 843 struct brw_stage_prog_data base; 844 845 unsigned local_size[3]; 846 unsigned simd_size; 847 unsigned threads; 848 bool uses_barrier; 849 bool uses_num_work_groups; 850 851 struct { 852 struct brw_push_const_block cross_thread; 853 struct brw_push_const_block per_thread; 854 struct brw_push_const_block total; 855 } push; 856 857 struct { 858 /** @{ 859 * surface indices the CS-specific surfaces 860 */ 861 uint32_t work_groups_start; 862 /** @} */ 863 } binding_table; 864}; 865 866/** 867 * Enum representing the i965-specific vertex results that don't correspond 868 * exactly to any element of gl_varying_slot. The values of this enum are 869 * assigned such that they don't conflict with gl_varying_slot. 870 */ 871typedef enum 872{ 873 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX, 874 BRW_VARYING_SLOT_PAD, 875 /** 876 * Technically this is not a varying but just a placeholder that 877 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord 878 * builtin variable to be compiled correctly. see compile_sf_prog() for 879 * more info. 880 */ 881 BRW_VARYING_SLOT_PNTC, 882 BRW_VARYING_SLOT_COUNT 883} brw_varying_slot; 884 885/** 886 * We always program SF to start reading at an offset of 1 (2 varying slots) 887 * from the start of the vertex URB entry. This causes it to skip: 888 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5 889 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+ 890 */ 891#define BRW_SF_URB_ENTRY_READ_OFFSET 1 892 893/** 894 * Bitmask indicating which fragment shader inputs represent varyings (and 895 * hence have to be delivered to the fragment shader by the SF/SBE stage). 896 */ 897#define BRW_FS_VARYING_INPUT_MASK \ 898 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \ 899 ~VARYING_BIT_POS & ~VARYING_BIT_FACE) 900 901/** 902 * Data structure recording the relationship between the gl_varying_slot enum 903 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a 904 * single octaword within the VUE (128 bits). 905 * 906 * Note that each BRW register contains 256 bits (2 octawords), so when 907 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two 908 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as 909 * in a vertex shader), each register corresponds to a single VUE slot, since 910 * it contains data for two separate vertices. 911 */ 912struct brw_vue_map { 913 /** 914 * Bitfield representing all varying slots that are (a) stored in this VUE 915 * map, and (b) actually written by the shader. Does not include any of 916 * the additional varying slots defined in brw_varying_slot. 917 */ 918 uint64_t slots_valid; 919 920 /** 921 * Is this VUE map for a separate shader pipeline? 922 * 923 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched 924 * without the linker having a chance to dead code eliminate unused varyings. 925 * 926 * This means that we have to use a fixed slot layout, based on the output's 927 * location field, rather than assigning slots in a compact contiguous block. 928 */ 929 bool separate; 930 931 /** 932 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are 933 * not stored in a slot (because they are not written, or because 934 * additional processing is applied before storing them in the VUE), the 935 * value is -1. 936 */ 937 signed char varying_to_slot[VARYING_SLOT_TESS_MAX]; 938 939 /** 940 * Map from VUE slot to gl_varying_slot value. For slots that do not 941 * directly correspond to a gl_varying_slot, the value comes from 942 * brw_varying_slot. 943 * 944 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD. 945 */ 946 signed char slot_to_varying[VARYING_SLOT_TESS_MAX]; 947 948 /** 949 * Total number of VUE slots in use 950 */ 951 int num_slots; 952 953 /** 954 * Number of per-patch VUE slots. Only valid for tessellation control 955 * shader outputs and tessellation evaluation shader inputs. 956 */ 957 int num_per_patch_slots; 958 959 /** 960 * Number of per-vertex VUE slots. Only valid for tessellation control 961 * shader outputs and tessellation evaluation shader inputs. 962 */ 963 int num_per_vertex_slots; 964}; 965 966void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map); 967 968/** 969 * Convert a VUE slot number into a byte offset within the VUE. 970 */ 971static inline GLuint brw_vue_slot_to_offset(GLuint slot) 972{ 973 return 16*slot; 974} 975 976/** 977 * Convert a vertex output (brw_varying_slot) into a byte offset within the 978 * VUE. 979 */ 980static inline 981GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying) 982{ 983 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]); 984} 985 986void brw_compute_vue_map(const struct gen_device_info *devinfo, 987 struct brw_vue_map *vue_map, 988 uint64_t slots_valid, 989 bool separate_shader); 990 991void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map, 992 uint64_t slots_valid, 993 uint32_t is_patch); 994 995/* brw_interpolation_map.c */ 996void brw_setup_vue_interpolation(struct brw_vue_map *vue_map, 997 struct nir_shader *nir, 998 struct brw_wm_prog_data *prog_data); 999 1000enum shader_dispatch_mode { 1001 DISPATCH_MODE_4X1_SINGLE = 0, 1002 DISPATCH_MODE_4X2_DUAL_INSTANCE = 1, 1003 DISPATCH_MODE_4X2_DUAL_OBJECT = 2, 1004 DISPATCH_MODE_SIMD8 = 3, 1005}; 1006 1007/** 1008 * @defgroup Tessellator parameter enumerations. 1009 * 1010 * These correspond to the hardware values in 3DSTATE_TE, and are provided 1011 * as part of the tessellation evaluation shader. 1012 * 1013 * @{ 1014 */ 1015enum brw_tess_partitioning { 1016 BRW_TESS_PARTITIONING_INTEGER = 0, 1017 BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1, 1018 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2, 1019}; 1020 1021enum brw_tess_output_topology { 1022 BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0, 1023 BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1, 1024 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2, 1025 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3, 1026}; 1027 1028enum brw_tess_domain { 1029 BRW_TESS_DOMAIN_QUAD = 0, 1030 BRW_TESS_DOMAIN_TRI = 1, 1031 BRW_TESS_DOMAIN_ISOLINE = 2, 1032}; 1033/** @} */ 1034 1035struct brw_vue_prog_data { 1036 struct brw_stage_prog_data base; 1037 struct brw_vue_map vue_map; 1038 1039 /** Should the hardware deliver input VUE handles for URB pull loads? */ 1040 bool include_vue_handles; 1041 1042 GLuint urb_read_length; 1043 GLuint total_grf; 1044 1045 uint32_t clip_distance_mask; 1046 uint32_t cull_distance_mask; 1047 1048 /* Used for calculating urb partitions. In the VS, this is the size of the 1049 * URB entry used for both input and output to the thread. In the GS, this 1050 * is the size of the URB entry used for output. 1051 */ 1052 GLuint urb_entry_size; 1053 1054 enum shader_dispatch_mode dispatch_mode; 1055}; 1056 1057struct brw_vs_prog_data { 1058 struct brw_vue_prog_data base; 1059 1060 GLbitfield64 inputs_read; 1061 GLbitfield64 double_inputs_read; 1062 1063 unsigned nr_attribute_slots; 1064 1065 bool uses_vertexid; 1066 bool uses_instanceid; 1067 bool uses_is_indexed_draw; 1068 bool uses_firstvertex; 1069 bool uses_baseinstance; 1070 bool uses_drawid; 1071}; 1072 1073struct brw_tcs_prog_data 1074{ 1075 struct brw_vue_prog_data base; 1076 1077 /** Number vertices in output patch */ 1078 int instances; 1079}; 1080 1081 1082struct brw_tes_prog_data 1083{ 1084 struct brw_vue_prog_data base; 1085 1086 enum brw_tess_partitioning partitioning; 1087 enum brw_tess_output_topology output_topology; 1088 enum brw_tess_domain domain; 1089}; 1090 1091struct brw_gs_prog_data 1092{ 1093 struct brw_vue_prog_data base; 1094 1095 unsigned vertices_in; 1096 1097 /** 1098 * Size of an output vertex, measured in HWORDS (32 bytes). 1099 */ 1100 unsigned output_vertex_size_hwords; 1101 1102 unsigned output_topology; 1103 1104 /** 1105 * Size of the control data (cut bits or StreamID bits), in hwords (32 1106 * bytes). 0 if there is no control data. 1107 */ 1108 unsigned control_data_header_size_hwords; 1109 1110 /** 1111 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1112 * if the control data is StreamID bits, or 1113 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits). 1114 * Ignored if control_data_header_size is 0. 1115 */ 1116 unsigned control_data_format; 1117 1118 bool include_primitive_id; 1119 1120 /** 1121 * The number of vertices emitted, if constant - otherwise -1. 1122 */ 1123 int static_vertex_count; 1124 1125 int invocations; 1126 1127 /** 1128 * Gen6: Provoking vertex convention for odd-numbered triangles 1129 * in tristrips. 1130 */ 1131 GLuint pv_first:1; 1132 1133 /** 1134 * Gen6: Number of varyings that are output to transform feedback. 1135 */ 1136 GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */ 1137 1138 /** 1139 * Gen6: Map from the index of a transform feedback binding table entry to the 1140 * gl_varying_slot that should be streamed out through that binding table 1141 * entry. 1142 */ 1143 unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */]; 1144 1145 /** 1146 * Gen6: Map from the index of a transform feedback binding table entry to the 1147 * swizzles that should be used when streaming out data through that 1148 * binding table entry. 1149 */ 1150 unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */]; 1151}; 1152 1153struct brw_sf_prog_data { 1154 uint32_t urb_read_length; 1155 uint32_t total_grf; 1156 1157 /* Each vertex may have upto 12 attributes, 4 components each, 1158 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11 1159 * rows. 1160 * 1161 * Actually we use 4 for each, so call it 12 rows. 1162 */ 1163 unsigned urb_entry_size; 1164}; 1165 1166struct brw_clip_prog_data { 1167 uint32_t curb_read_length; /* user planes? */ 1168 uint32_t clip_mode; 1169 uint32_t urb_read_length; 1170 uint32_t total_grf; 1171}; 1172 1173/* brw_any_prog_data is prog_data for any stage that maps to an API stage */ 1174union brw_any_prog_data { 1175 struct brw_stage_prog_data base; 1176 struct brw_vue_prog_data vue; 1177 struct brw_vs_prog_data vs; 1178 struct brw_tcs_prog_data tcs; 1179 struct brw_tes_prog_data tes; 1180 struct brw_gs_prog_data gs; 1181 struct brw_wm_prog_data wm; 1182 struct brw_cs_prog_data cs; 1183}; 1184 1185#define DEFINE_PROG_DATA_DOWNCAST(stage) \ 1186static inline struct brw_##stage##_prog_data * \ 1187brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \ 1188{ \ 1189 return (struct brw_##stage##_prog_data *) prog_data; \ 1190} 1191DEFINE_PROG_DATA_DOWNCAST(vue) 1192DEFINE_PROG_DATA_DOWNCAST(vs) 1193DEFINE_PROG_DATA_DOWNCAST(tcs) 1194DEFINE_PROG_DATA_DOWNCAST(tes) 1195DEFINE_PROG_DATA_DOWNCAST(gs) 1196DEFINE_PROG_DATA_DOWNCAST(wm) 1197DEFINE_PROG_DATA_DOWNCAST(cs) 1198DEFINE_PROG_DATA_DOWNCAST(ff_gs) 1199DEFINE_PROG_DATA_DOWNCAST(clip) 1200DEFINE_PROG_DATA_DOWNCAST(sf) 1201#undef DEFINE_PROG_DATA_DOWNCAST 1202 1203/** @} */ 1204 1205struct brw_compiler * 1206brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo); 1207 1208/** 1209 * Returns a compiler configuration for use with disk shader cache 1210 * 1211 * This value only needs to change for settings that can cause different 1212 * program generation between two runs on the same hardware. 1213 * 1214 * For example, it doesn't need to be different for gen 8 and gen 9 hardware, 1215 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used. 1216 */ 1217uint64_t 1218brw_get_compiler_config_value(const struct brw_compiler *compiler); 1219 1220unsigned 1221brw_prog_data_size(gl_shader_stage stage); 1222 1223unsigned 1224brw_prog_key_size(gl_shader_stage stage); 1225 1226/** 1227 * Compile a vertex shader. 1228 * 1229 * Returns the final assembly and the program's size. 1230 */ 1231const unsigned * 1232brw_compile_vs(const struct brw_compiler *compiler, void *log_data, 1233 void *mem_ctx, 1234 const struct brw_vs_prog_key *key, 1235 struct brw_vs_prog_data *prog_data, 1236 struct nir_shader *shader, 1237 int shader_time_index, 1238 char **error_str); 1239 1240/** 1241 * Compile a tessellation control shader. 1242 * 1243 * Returns the final assembly and the program's size. 1244 */ 1245const unsigned * 1246brw_compile_tcs(const struct brw_compiler *compiler, 1247 void *log_data, 1248 void *mem_ctx, 1249 const struct brw_tcs_prog_key *key, 1250 struct brw_tcs_prog_data *prog_data, 1251 struct nir_shader *nir, 1252 int shader_time_index, 1253 char **error_str); 1254 1255/** 1256 * Compile a tessellation evaluation shader. 1257 * 1258 * Returns the final assembly and the program's size. 1259 */ 1260const unsigned * 1261brw_compile_tes(const struct brw_compiler *compiler, void *log_data, 1262 void *mem_ctx, 1263 const struct brw_tes_prog_key *key, 1264 const struct brw_vue_map *input_vue_map, 1265 struct brw_tes_prog_data *prog_data, 1266 struct nir_shader *shader, 1267 struct gl_program *prog, 1268 int shader_time_index, 1269 char **error_str); 1270 1271/** 1272 * Compile a vertex shader. 1273 * 1274 * Returns the final assembly and the program's size. 1275 */ 1276const unsigned * 1277brw_compile_gs(const struct brw_compiler *compiler, void *log_data, 1278 void *mem_ctx, 1279 const struct brw_gs_prog_key *key, 1280 struct brw_gs_prog_data *prog_data, 1281 struct nir_shader *shader, 1282 struct gl_program *prog, 1283 int shader_time_index, 1284 char **error_str); 1285 1286/** 1287 * Compile a strips and fans shader. 1288 * 1289 * This is a fixed-function shader determined entirely by the shader key and 1290 * a VUE map. 1291 * 1292 * Returns the final assembly and the program's size. 1293 */ 1294const unsigned * 1295brw_compile_sf(const struct brw_compiler *compiler, 1296 void *mem_ctx, 1297 const struct brw_sf_prog_key *key, 1298 struct brw_sf_prog_data *prog_data, 1299 struct brw_vue_map *vue_map, 1300 unsigned *final_assembly_size); 1301 1302/** 1303 * Compile a clipper shader. 1304 * 1305 * This is a fixed-function shader determined entirely by the shader key and 1306 * a VUE map. 1307 * 1308 * Returns the final assembly and the program's size. 1309 */ 1310const unsigned * 1311brw_compile_clip(const struct brw_compiler *compiler, 1312 void *mem_ctx, 1313 const struct brw_clip_prog_key *key, 1314 struct brw_clip_prog_data *prog_data, 1315 struct brw_vue_map *vue_map, 1316 unsigned *final_assembly_size); 1317 1318/** 1319 * Compile a fragment shader. 1320 * 1321 * Returns the final assembly and the program's size. 1322 */ 1323const unsigned * 1324brw_compile_fs(const struct brw_compiler *compiler, void *log_data, 1325 void *mem_ctx, 1326 const struct brw_wm_prog_key *key, 1327 struct brw_wm_prog_data *prog_data, 1328 struct nir_shader *shader, 1329 struct gl_program *prog, 1330 int shader_time_index8, 1331 int shader_time_index16, 1332 int shader_time_index32, 1333 bool allow_spilling, 1334 bool use_rep_send, struct brw_vue_map *vue_map, 1335 char **error_str); 1336 1337/** 1338 * Compile a compute shader. 1339 * 1340 * Returns the final assembly and the program's size. 1341 */ 1342const unsigned * 1343brw_compile_cs(const struct brw_compiler *compiler, void *log_data, 1344 void *mem_ctx, 1345 const struct brw_cs_prog_key *key, 1346 struct brw_cs_prog_data *prog_data, 1347 const struct nir_shader *shader, 1348 int shader_time_index, 1349 char **error_str); 1350 1351void brw_debug_key_recompile(const struct brw_compiler *c, void *log, 1352 gl_shader_stage stage, 1353 const void *old_key, const void *key); 1354 1355static inline uint32_t 1356encode_slm_size(unsigned gen, uint32_t bytes) 1357{ 1358 uint32_t slm_size = 0; 1359 1360 /* Shared Local Memory is specified as powers of two, and encoded in 1361 * INTERFACE_DESCRIPTOR_DATA with the following representations: 1362 * 1363 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB | 1364 * ------------------------------------------------------------------- 1365 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 | 1366 * ------------------------------------------------------------------- 1367 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1368 */ 1369 assert(bytes <= 64 * 1024); 1370 1371 if (bytes > 0) { 1372 /* Shared Local Memory Size is specified as powers of two. */ 1373 slm_size = util_next_power_of_two(bytes); 1374 1375 if (gen >= 9) { 1376 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */ 1377 slm_size = ffs(MAX2(slm_size, 1024)) - 10; 1378 } else { 1379 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */ 1380 slm_size = MAX2(slm_size, 4096) / 4096; 1381 } 1382 } 1383 1384 return slm_size; 1385} 1386 1387/** 1388 * Return true if the given shader stage is dispatched contiguously by the 1389 * relevant fixed function starting from channel 0 of the SIMD thread, which 1390 * implies that the dispatch mask of a thread can be assumed to have the form 1391 * '2^n - 1' for some n. 1392 */ 1393static inline bool 1394brw_stage_has_packed_dispatch(MAYBE_UNUSED const struct gen_device_info *devinfo, 1395 gl_shader_stage stage, 1396 const struct brw_stage_prog_data *prog_data) 1397{ 1398 /* The code below makes assumptions about the hardware's thread dispatch 1399 * behavior that could be proven wrong in future generations -- Make sure 1400 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to 1401 * the NIR front-end before changing this assertion. 1402 */ 1403 assert(devinfo->gen <= 11); 1404 1405 switch (stage) { 1406 case MESA_SHADER_FRAGMENT: { 1407 /* The PSD discards subspans coming in with no lit samples, which in the 1408 * per-pixel shading case implies that each subspan will either be fully 1409 * lit (due to the VMask being used to allow derivative computations), 1410 * or not dispatched at all. In per-sample dispatch mode individual 1411 * samples from the same subspan have a fixed relative location within 1412 * the SIMD thread, so dispatch of unlit samples cannot be avoided in 1413 * general and we should return false. 1414 */ 1415 const struct brw_wm_prog_data *wm_prog_data = 1416 (const struct brw_wm_prog_data *)prog_data; 1417 return !wm_prog_data->persample_dispatch; 1418 } 1419 case MESA_SHADER_COMPUTE: 1420 /* Compute shaders will be spawned with either a fully enabled dispatch 1421 * mask or with whatever bottom/right execution mask was given to the 1422 * GPGPU walker command to be used along the workgroup edges -- In both 1423 * cases the dispatch mask is required to be tightly packed for our 1424 * invocation index calculations to work. 1425 */ 1426 return true; 1427 default: 1428 /* Most remaining fixed functions are limited to use a packed dispatch 1429 * mask due to the hardware representation of the dispatch mask as a 1430 * single counter representing the number of enabled channels. 1431 */ 1432 return true; 1433 } 1434} 1435 1436/** 1437 * Computes the first varying slot in the URB produced by the previous stage 1438 * that is used in the next stage. We do this by testing the varying slots in 1439 * the previous stage's vue map against the inputs read in the next stage. 1440 * 1441 * Note that: 1442 * 1443 * - Each URB offset contains two varying slots and we can only skip a 1444 * full offset if both slots are unused, so the value we return here is always 1445 * rounded down to the closest multiple of two. 1446 * 1447 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are 1448 * part of the vue header, so if these are read we can't skip anything. 1449 */ 1450static inline int 1451brw_compute_first_urb_slot_required(uint64_t inputs_read, 1452 const struct brw_vue_map *prev_stage_vue_map) 1453{ 1454 if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT)) == 0) { 1455 for (int i = 0; i < prev_stage_vue_map->num_slots; i++) { 1456 int varying = prev_stage_vue_map->slot_to_varying[i]; 1457 if (varying > 0 && (inputs_read & BITFIELD64_BIT(varying)) != 0) 1458 return ROUND_DOWN_TO(i, 2); 1459 } 1460 } 1461 1462 return 0; 1463} 1464 1465#ifdef __cplusplus 1466} /* extern "C" */ 1467#endif 1468 1469#endif /* BRW_COMPILER_H */ 1470