1/* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** 25 * @file brw_inst.h 26 * 27 * A representation of i965 EU assembly instructions, with helper methods to 28 * get and set various fields. This is the actual hardware format. 29 */ 30 31#ifndef BRW_INST_H 32#define BRW_INST_H 33 34#include <assert.h> 35#include <stdint.h> 36 37#include "brw_eu_defines.h" 38#include "brw_reg_type.h" 39#include "dev/gen_device_info.h" 40 41#ifdef __cplusplus 42extern "C" { 43#endif 44 45/* brw_context.h has a forward declaration of brw_inst, so name the struct. */ 46typedef struct brw_inst { 47 uint64_t data[2]; 48} brw_inst; 49 50static inline uint64_t brw_inst_bits(const brw_inst *inst, 51 unsigned high, unsigned low); 52static inline void brw_inst_set_bits(brw_inst *inst, 53 unsigned high, unsigned low, 54 uint64_t value); 55 56#define FC(name, high, low, assertions) \ 57static inline void \ 58brw_inst_set_##name(const struct gen_device_info *devinfo, \ 59 brw_inst *inst, uint64_t v) \ 60{ \ 61 assert(assertions); \ 62 (void) devinfo; \ 63 brw_inst_set_bits(inst, high, low, v); \ 64} \ 65static inline uint64_t \ 66brw_inst_##name(const struct gen_device_info *devinfo, \ 67 const brw_inst *inst) \ 68{ \ 69 assert(assertions); \ 70 (void) devinfo; \ 71 return brw_inst_bits(inst, high, low); \ 72} 73 74/* A simple macro for fields which stay in the same place on all generations. */ 75#define F(name, high, low) FC(name, high, low, true) 76 77#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \ 78 unsigned high, low; \ 79 if (devinfo->gen >= 8) { \ 80 high = hi8; low = lo8; \ 81 } else if (devinfo->gen >= 7) { \ 82 high = hi7; low = lo7; \ 83 } else if (devinfo->gen >= 6) { \ 84 high = hi6; low = lo6; \ 85 } else if (devinfo->gen >= 5) { \ 86 high = hi5; low = lo5; \ 87 } else if (devinfo->is_g4x) { \ 88 high = hi45; low = lo45; \ 89 } else { \ 90 high = hi4; low = lo4; \ 91 } \ 92 assert(((int) high) != -1 && ((int) low) != -1); 93 94/* A general macro for cases where the field has moved to several different 95 * bit locations across generations. GCC appears to combine cases where the 96 * bits are identical, removing some of the inefficiency. 97 */ 98#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\ 99static inline void \ 100brw_inst_set_##name(const struct gen_device_info *devinfo, \ 101 brw_inst *inst, uint64_t value) \ 102{ \ 103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \ 104 brw_inst_set_bits(inst, high, low, value); \ 105} \ 106static inline uint64_t \ 107brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \ 108{ \ 109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \ 110 return brw_inst_bits(inst, high, low); \ 111} 112 113/* A macro for fields which moved as of Gen8+. */ 114#define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \ 115FF(name, \ 116 /* 4: */ gen4_high, gen4_low, \ 117 /* 4.5: */ gen4_high, gen4_low, \ 118 /* 5: */ gen4_high, gen4_low, \ 119 /* 6: */ gen4_high, gen4_low, \ 120 /* 7: */ gen4_high, gen4_low, \ 121 /* 8: */ gen8_high, gen8_low); 122 123F(src1_vstride, 120, 117) 124F(src1_width, 116, 114) 125F(src1_da16_swiz_w, 115, 114) 126F(src1_da16_swiz_z, 113, 112) 127F(src1_hstride, 113, 112) 128F(src1_address_mode, 111, 111) 129/** Src1.SrcMod @{ */ 130F(src1_negate, 110, 110) 131F(src1_abs, 109, 109) 132/** @} */ 133F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105) 134F(src1_da_reg_nr, 108, 101) 135F(src1_da16_subreg_nr, 100, 100) 136F(src1_da1_subreg_nr, 100, 96) 137F(src1_da16_swiz_y, 99, 98) 138F(src1_da16_swiz_x, 97, 96) 139F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91) 140F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89) 141F(src0_vstride, 88, 85) 142F(src0_width, 84, 82) 143F(src0_da16_swiz_w, 83, 82) 144F(src0_da16_swiz_z, 81, 80) 145F(src0_hstride, 81, 80) 146F(src0_address_mode, 79, 79) 147/** Src0.SrcMod @{ */ 148F(src0_negate, 78, 78) 149F(src0_abs, 77, 77) 150/** @} */ 151F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73) 152F(src0_da_reg_nr, 76, 69) 153F(src0_da16_subreg_nr, 68, 68) 154F(src0_da1_subreg_nr, 68, 64) 155F(src0_da16_swiz_y, 67, 66) 156F(src0_da16_swiz_x, 65, 64) 157F(dst_address_mode, 63, 63) 158F(dst_hstride, 62, 61) 159F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57) 160F(dst_da_reg_nr, 60, 53) 161F(dst_da16_subreg_nr, 52, 52) 162F(dst_da1_subreg_nr, 52, 48) 163F(da16_writemask, 51, 48) /* Dst.ChanEn */ 164F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43) 165F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41) 166F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37) 167F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35) 168F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34) 169FF(flag_reg_nr, 170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1, 171 /* 7: */ 90, 90, 172 /* 8: */ 33, 33) 173F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32) 174F(saturate, 31, 31) 175F(debug_control, 30, 30) 176F(cmpt_control, 29, 29) 177FC(branch_control, 28, 28, devinfo->gen >= 8) 178FC(acc_wr_control, 28, 28, devinfo->gen >= 6) 179FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5) 180F(cond_modifier, 27, 24) 181FC(math_function, 27, 24, devinfo->gen >= 6) 182F(exec_size, 23, 21) 183F(pred_inv, 20, 20) 184F(pred_control, 19, 16) 185F(thread_control, 15, 14) 186F(qtr_control, 13, 12) 187FF(nib_control, 188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1, 189 /* 7: */ 47, 47, 190 /* 8: */ 11, 11) 191F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10) 192F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9) 193F(access_mode, 8, 8) 194/* Bit 7 is Reserved (for future Opcode expansion) */ 195F(opcode, 6, 0) 196 197/** 198 * Three-source instructions: 199 * @{ 200 */ 201F(3src_src2_reg_nr, 125, 118) /* same in align1 */ 202F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */ 203F(3src_a16_src2_swizzle, 114, 107) 204F(3src_a16_src2_rep_ctrl, 106, 106) 205F(3src_src1_reg_nr, 104, 97) /* same in align1 */ 206F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */ 207F(3src_a16_src1_swizzle, 93, 86) 208F(3src_a16_src1_rep_ctrl, 85, 85) 209F(3src_src0_reg_nr, 83, 76) /* same in align1 */ 210F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */ 211F(3src_a16_src0_swizzle, 72, 65) 212F(3src_a16_src0_rep_ctrl, 64, 64) 213F(3src_dst_reg_nr, 63, 56) /* same in align1 */ 214F(3src_a16_dst_subreg_nr, 55, 53) 215F(3src_a16_dst_writemask, 52, 49) 216F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */ 217F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */ 218F8(3src_a16_src_hw_type, 43, 42, 45, 43) 219F8(3src_src2_negate, 41, 41, 42, 42) 220F8(3src_src2_abs, 40, 40, 41, 41) 221F8(3src_src1_negate, 39, 39, 40, 40) 222F8(3src_src1_abs, 38, 38, 39, 39) 223F8(3src_src0_negate, 37, 37, 38, 38) 224F8(3src_src0_abs, 36, 36, 37, 37) 225F8(3src_a16_src1_type, -1, -1, 36, 36) 226F8(3src_a16_src2_type, -1, -1, 35, 35) 227F8(3src_a16_flag_reg_nr, 34, 34, 33, 33) 228F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32) 229FF(3src_a16_dst_reg_file, 230 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1, 231 /* 6: */ 32, 32, 232 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1) 233F(3src_saturate, 31, 31) 234F(3src_debug_control, 30, 30) 235F(3src_cmpt_control, 29, 29) 236F(3src_acc_wr_control, 28, 28) 237F(3src_cond_modifier, 27, 24) 238F(3src_exec_size, 23, 21) 239F(3src_pred_inv, 20, 20) 240F(3src_pred_control, 19, 16) 241F(3src_thread_control, 15, 14) 242F(3src_qtr_control, 13, 12) 243F8(3src_no_dd_check, 11, 11, 10, 10) 244F8(3src_no_dd_clear, 10, 10, 9, 9) 245F8(3src_mask_control, 9, 9, 34, 34) 246F(3src_access_mode, 8, 8) 247/* Bit 7 is Reserved (for future Opcode expansion) */ 248F(3src_opcode, 6, 0) 249/** @} */ 250 251#define REG_TYPE(reg) \ 252static inline void \ 253brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \ 254 brw_inst *inst, enum brw_reg_type type) \ 255{ \ 256 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \ 257 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \ 258} \ 259 \ 260static inline enum brw_reg_type \ 261brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \ 262 const brw_inst *inst) \ 263{ \ 264 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \ 265 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \ 266} 267 268REG_TYPE(dst) 269REG_TYPE(src) 270#undef REG_TYPE 271 272/** 273 * Three-source align1 instructions: 274 * @{ 275 */ 276/* Reserved 127:126 */ 277/* src2_reg_nr same in align16 */ 278FC(3src_a1_src2_subreg_nr, 117, 113, devinfo->gen >= 10) 279FC(3src_a1_src2_hstride, 112, 111, devinfo->gen >= 10) 280/* Reserved 110:109. src2 vstride is an implied parameter */ 281FC(3src_a1_src2_hw_type, 108, 106, devinfo->gen >= 10) 282/* Reserved 105 */ 283/* src1_reg_nr same in align16 */ 284FC(3src_a1_src1_subreg_nr, 96, 92, devinfo->gen >= 10) 285FC(3src_a1_src1_hstride, 91, 90, devinfo->gen >= 10) 286FC(3src_a1_src1_vstride, 89, 88, devinfo->gen >= 10) 287FC(3src_a1_src1_hw_type, 87, 85, devinfo->gen >= 10) 288/* Reserved 84 */ 289/* src0_reg_nr same in align16 */ 290FC(3src_a1_src0_subreg_nr, 75, 71, devinfo->gen >= 10) 291FC(3src_a1_src0_hstride, 70, 69, devinfo->gen >= 10) 292FC(3src_a1_src0_vstride, 68, 67, devinfo->gen >= 10) 293FC(3src_a1_src0_hw_type, 66, 64, devinfo->gen >= 10) 294/* dst_reg_nr same in align16 */ 295FC(3src_a1_dst_subreg_nr, 55, 54, devinfo->gen >= 10) 296FC(3src_a1_special_acc, 55, 52, devinfo->gen >= 10) /* aliases dst_subreg_nr */ 297/* Reserved 51:50 */ 298FC(3src_a1_dst_hstride, 49, 49, devinfo->gen >= 10) 299FC(3src_a1_dst_hw_type, 48, 46, devinfo->gen >= 10) 300FC(3src_a1_src2_reg_file, 45, 45, devinfo->gen >= 10) 301FC(3src_a1_src1_reg_file, 44, 44, devinfo->gen >= 10) 302FC(3src_a1_src0_reg_file, 43, 43, devinfo->gen >= 10) 303/* Source Modifier fields same in align16 */ 304FC(3src_a1_dst_reg_file, 36, 36, devinfo->gen >= 10) 305FC(3src_a1_exec_type, 35, 35, devinfo->gen >= 10) 306/* Fields below this same in align16 */ 307/** @} */ 308 309#define REG_TYPE(reg) \ 310static inline void \ 311brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \ 312 brw_inst *inst, enum brw_reg_type type) \ 313{ \ 314 UNUSED enum gen10_align1_3src_exec_type exec_type = \ 315 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ 316 inst); \ 317 if (brw_reg_type_is_floating_point(type)) { \ 318 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ 319 } else { \ 320 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \ 321 } \ 322 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \ 323 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \ 324} \ 325 \ 326static inline enum brw_reg_type \ 327brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \ 328 const brw_inst *inst) \ 329{ \ 330 enum gen10_align1_3src_exec_type exec_type = \ 331 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ 332 inst); \ 333 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \ 334 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ 335} 336 337REG_TYPE(dst) 338REG_TYPE(src0) 339REG_TYPE(src1) 340REG_TYPE(src2) 341#undef REG_TYPE 342 343/** 344 * Three-source align1 instruction immediates: 345 * @{ 346 */ 347static inline uint16_t 348brw_inst_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo, 349 const brw_inst *insn) 350{ 351 assert(devinfo->gen >= 10); 352 return brw_inst_bits(insn, 82, 67); 353} 354 355static inline uint16_t 356brw_inst_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo, 357 const brw_inst *insn) 358{ 359 assert(devinfo->gen >= 10); 360 return brw_inst_bits(insn, 124, 109); 361} 362 363static inline void 364brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo, 365 brw_inst *insn, uint16_t value) 366{ 367 assert(devinfo->gen >= 10); 368 brw_inst_set_bits(insn, 82, 67, value); 369} 370 371static inline void 372brw_inst_set_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo, 373 brw_inst *insn, uint16_t value) 374{ 375 assert(devinfo->gen >= 10); 376 brw_inst_set_bits(insn, 124, 109, value); 377} 378/** @} */ 379 380/** 381 * Flow control instruction bits: 382 * @{ 383 */ 384static inline void 385brw_inst_set_uip(const struct gen_device_info *devinfo, 386 brw_inst *inst, int32_t value) 387{ 388 assert(devinfo->gen >= 6); 389 390 if (devinfo->gen >= 8) { 391 brw_inst_set_bits(inst, 95, 64, (uint32_t)value); 392 } else { 393 assert(value <= (1 << 16) - 1); 394 assert(value > -(1 << 16)); 395 brw_inst_set_bits(inst, 127, 112, (uint16_t)value); 396 } 397} 398 399static inline int32_t 400brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst) 401{ 402 assert(devinfo->gen >= 6); 403 404 if (devinfo->gen >= 8) { 405 return brw_inst_bits(inst, 95, 64); 406 } else { 407 return (int16_t)brw_inst_bits(inst, 127, 112); 408 } 409} 410 411static inline void 412brw_inst_set_jip(const struct gen_device_info *devinfo, 413 brw_inst *inst, int32_t value) 414{ 415 assert(devinfo->gen >= 6); 416 417 if (devinfo->gen >= 8) { 418 brw_inst_set_bits(inst, 127, 96, (uint32_t)value); 419 } else { 420 assert(value <= (1 << 15) - 1); 421 assert(value >= -(1 << 15)); 422 brw_inst_set_bits(inst, 111, 96, (uint16_t)value); 423 } 424} 425 426static inline int32_t 427brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst) 428{ 429 assert(devinfo->gen >= 6); 430 431 if (devinfo->gen >= 8) { 432 return brw_inst_bits(inst, 127, 96); 433 } else { 434 return (int16_t)brw_inst_bits(inst, 111, 96); 435 } 436} 437 438/** Like FC, but using int16_t to handle negative jump targets. */ 439#define FJ(name, high, low, assertions) \ 440static inline void \ 441brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \ 442{ \ 443 assert(assertions); \ 444 (void) devinfo; \ 445 brw_inst_set_bits(inst, high, low, (uint16_t) v); \ 446} \ 447static inline int16_t \ 448brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \ 449{ \ 450 assert(assertions); \ 451 (void) devinfo; \ 452 return brw_inst_bits(inst, high, low); \ 453} 454 455FJ(gen6_jump_count, 63, 48, devinfo->gen == 6) 456FJ(gen4_jump_count, 111, 96, devinfo->gen < 6) 457FC(gen4_pop_count, 115, 112, devinfo->gen < 6) 458/** @} */ 459 460/** 461 * SEND instructions: 462 * @{ 463 */ 464FC(send_ex_desc_ia_subreg_nr, 82, 80, devinfo->gen >= 9) 465FC(send_src0_address_mode, 79, 79, devinfo->gen >= 9) 466FC(send_sel_reg32_desc, 77, 77, devinfo->gen >= 9) 467FC(send_sel_reg32_ex_desc, 61, 61, devinfo->gen >= 9) 468FC(send_src1_reg_nr, 51, 44, devinfo->gen >= 9) 469FC(send_src1_reg_file, 36, 36, devinfo->gen >= 9) 470FC(send_dst_reg_file, 35, 35, devinfo->gen >= 9) 471/** @} */ 472 473/* Message descriptor bits */ 474#define MD(x) ((x) + 96) 475 476/** 477 * Set the SEND(C) message descriptor immediate. 478 * 479 * This doesn't include the SFID nor the EOT field that were considered to be 480 * part of the message descriptor by ancient versions of the BSpec, because 481 * they are present in the instruction even if the message descriptor is 482 * provided indirectly in the address register, so we want to specify them 483 * separately. 484 */ 485static inline void 486brw_inst_set_send_desc(const struct gen_device_info *devinfo, 487 brw_inst *inst, uint32_t value) 488{ 489 if (devinfo->gen >= 9) { 490 brw_inst_set_bits(inst, 126, 96, value); 491 assert(value >> 31 == 0); 492 } else if (devinfo->gen >= 5) { 493 brw_inst_set_bits(inst, 124, 96, value); 494 assert(value >> 29 == 0); 495 } else { 496 brw_inst_set_bits(inst, 119, 96, value); 497 assert(value >> 24 == 0); 498 } 499} 500 501/** 502 * Get the SEND(C) message descriptor immediate. 503 * 504 * \sa brw_inst_set_send_desc(). 505 */ 506static inline uint32_t 507brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst) 508{ 509 if (devinfo->gen >= 9) 510 return brw_inst_bits(inst, 126, 96); 511 else if (devinfo->gen >= 5) 512 return brw_inst_bits(inst, 124, 96); 513 else 514 return brw_inst_bits(inst, 119, 96); 515} 516 517/** 518 * Set the SEND(C) message extended descriptor immediate. 519 * 520 * This doesn't include the SFID nor the EOT field that were considered to be 521 * part of the extended message descriptor by some versions of the BSpec, 522 * because they are present in the instruction even if the extended message 523 * descriptor is provided indirectly in a register, so we want to specify them 524 * separately. 525 */ 526static inline void 527brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo, 528 brw_inst *inst, uint32_t value) 529{ 530 assert(devinfo->gen >= 9); 531 if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND || 532 brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC) { 533 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28)); 534 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24)); 535 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20)); 536 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16)); 537 assert(GET_BITS(value, 15, 0) == 0); 538 } else { 539 assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS || 540 brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC); 541 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16)); 542 assert(GET_BITS(value, 15, 10) == 0); 543 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6)); 544 assert(GET_BITS(value, 5, 0) == 0); 545 } 546} 547 548/** 549 * Get the SEND(C) message extended descriptor immediate. 550 * 551 * \sa brw_inst_set_send_ex_desc(). 552 */ 553static inline uint32_t 554brw_inst_send_ex_desc(const struct gen_device_info *devinfo, 555 const brw_inst *inst) 556{ 557 assert(devinfo->gen >= 9); 558 if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND || 559 brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC) { 560 return (brw_inst_bits(inst, 94, 91) << 28 | 561 brw_inst_bits(inst, 88, 85) << 24 | 562 brw_inst_bits(inst, 83, 80) << 20 | 563 brw_inst_bits(inst, 67, 64) << 16); 564 } else { 565 assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS || 566 brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC); 567 return (brw_inst_bits(inst, 95, 80) << 16 | 568 brw_inst_bits(inst, 67, 64) << 6); 569 } 570} 571 572/** 573 * Fields for SEND messages: 574 * @{ 575 */ 576F(eot, 127, 127) 577FF(mlen, 578 /* 4: */ 119, 116, 579 /* 4.5: */ 119, 116, 580 /* 5: */ 124, 121, 581 /* 6: */ 124, 121, 582 /* 7: */ 124, 121, 583 /* 8: */ 124, 121); 584FF(rlen, 585 /* 4: */ 115, 112, 586 /* 4.5: */ 115, 112, 587 /* 5: */ 120, 116, 588 /* 6: */ 120, 116, 589 /* 7: */ 120, 116, 590 /* 8: */ 120, 116); 591FF(header_present, 592 /* 4: doesn't exist */ -1, -1, -1, -1, 593 /* 5: */ 115, 115, 594 /* 6: */ 115, 115, 595 /* 7: */ 115, 115, 596 /* 8: */ 115, 115) 597F(gateway_notify, MD(16), MD(15)) 598FF(function_control, 599 /* 4: */ 111, 96, 600 /* 4.5: */ 111, 96, 601 /* 5: */ 114, 96, 602 /* 6: */ 114, 96, 603 /* 7: */ 114, 96, 604 /* 8: */ 114, 96) 605FF(gateway_subfuncid, 606 /* 4: */ MD(1), MD(0), 607 /* 4.5: */ MD(1), MD(0), 608 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */ 609 /* 6: */ MD(2), MD(0), 610 /* 7: */ MD(2), MD(0), 611 /* 8: */ MD(2), MD(0)) 612FF(sfid, 613 /* 4: */ 123, 120, /* called msg_target */ 614 /* 4.5 */ 123, 120, 615 /* 5: */ 95, 92, 616 /* 6: */ 27, 24, 617 /* 7: */ 27, 24, 618 /* 8: */ 27, 24) 619FF(null_rt, 620 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 621 /* 8: */ 80, 80) /* actually only Gen11+ */ 622FC(base_mrf, 27, 24, devinfo->gen < 6); 623/** @} */ 624 625/** 626 * URB message function control bits: 627 * @{ 628 */ 629FF(urb_per_slot_offset, 630 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1, 631 /* 7: */ MD(16), MD(16), 632 /* 8: */ MD(17), MD(17)) 633FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8) 634FC(urb_complete, MD(15), MD(15), devinfo->gen < 8) 635FC(urb_used, MD(14), MD(14), devinfo->gen < 7) 636FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7) 637FF(urb_swizzle_control, 638 /* 4: */ MD(11), MD(10), 639 /* 4.5: */ MD(11), MD(10), 640 /* 5: */ MD(11), MD(10), 641 /* 6: */ MD(11), MD(10), 642 /* 7: */ MD(14), MD(14), 643 /* 8: */ MD(15), MD(15)) 644FF(urb_global_offset, 645 /* 4: */ MD( 9), MD(4), 646 /* 4.5: */ MD( 9), MD(4), 647 /* 5: */ MD( 9), MD(4), 648 /* 6: */ MD( 9), MD(4), 649 /* 7: */ MD(13), MD(3), 650 /* 8: */ MD(14), MD(4)) 651FF(urb_opcode, 652 /* 4: */ MD( 3), MD(0), 653 /* 4.5: */ MD( 3), MD(0), 654 /* 5: */ MD( 3), MD(0), 655 /* 6: */ MD( 3), MD(0), 656 /* 7: */ MD( 2), MD(0), 657 /* 8: */ MD( 3), MD(0)) 658/** @} */ 659 660/** 661 * Gen4-5 math messages: 662 * @{ 663 */ 664FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6) 665FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6) 666FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6) 667FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6) 668FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6) 669/** @} */ 670 671/** 672 * Sampler message function control bits: 673 * @{ 674 */ 675FF(sampler_simd_mode, 676 /* 4: doesn't exist */ -1, -1, -1, -1, 677 /* 5: */ MD(17), MD(16), 678 /* 6: */ MD(17), MD(16), 679 /* 7: */ MD(18), MD(17), 680 /* 8: */ MD(18), MD(17)) 681FF(sampler_msg_type, 682 /* 4: */ MD(15), MD(14), 683 /* 4.5: */ MD(15), MD(12), 684 /* 5: */ MD(15), MD(12), 685 /* 6: */ MD(15), MD(12), 686 /* 7: */ MD(16), MD(12), 687 /* 8: */ MD(16), MD(12)) 688FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x) 689F(sampler, MD(11), MD(8)) 690F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */ 691/** @} */ 692 693/** 694 * Data port message function control bits: 695 * @{ 696 */ 697FC(dp_category, MD(18), MD(18), devinfo->gen >= 7) 698 699/* Gen4-5 store fields in different bits for read/write messages. */ 700FF(dp_read_msg_type, 701 /* 4: */ MD(13), MD(12), 702 /* 4.5: */ MD(13), MD(11), 703 /* 5: */ MD(13), MD(11), 704 /* 6: */ MD(16), MD(13), 705 /* 7: */ MD(17), MD(14), 706 /* 8: */ MD(17), MD(14)) 707FF(dp_write_msg_type, 708 /* 4: */ MD(14), MD(12), 709 /* 4.5: */ MD(14), MD(12), 710 /* 5: */ MD(14), MD(12), 711 /* 6: */ MD(16), MD(13), 712 /* 7: */ MD(17), MD(14), 713 /* 8: */ MD(17), MD(14)) 714FF(dp_read_msg_control, 715 /* 4: */ MD(11), MD( 8), 716 /* 4.5: */ MD(10), MD( 8), 717 /* 5: */ MD(10), MD( 8), 718 /* 6: */ MD(12), MD( 8), 719 /* 7: */ MD(13), MD( 8), 720 /* 8: */ MD(13), MD( 8)) 721FF(dp_write_msg_control, 722 /* 4: */ MD(11), MD( 8), 723 /* 4.5: */ MD(11), MD( 8), 724 /* 5: */ MD(11), MD( 8), 725 /* 6: */ MD(12), MD( 8), 726 /* 7: */ MD(13), MD( 8), 727 /* 8: */ MD(13), MD( 8)) 728FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6); 729 730FF(dp_write_commit, 731 /* 4: */ MD(15), MD(15), 732 /* 4.5: */ MD(15), MD(15), 733 /* 5: */ MD(15), MD(15), 734 /* 6: */ MD(17), MD(17), 735 /* 7+: does not exist */ -1, -1, -1, -1) 736 737/* Gen6+ use the same bit locations for everything. */ 738FF(dp_msg_type, 739 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */ 740 -1, -1, -1, -1, -1, -1, 741 /* 6: */ MD(16), MD(13), 742 /* 7: */ MD(17), MD(14), 743 /* 8: */ MD(18), MD(14)) 744FF(dp_msg_control, 745 /* 4: */ MD(11), MD( 8), 746 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1, 747 /* 6: */ MD(12), MD( 8), 748 /* 7: */ MD(13), MD( 8), 749 /* 8: */ MD(13), MD( 8)) 750/** @} */ 751 752/** 753 * Scratch message bits (Gen7+): 754 * @{ 755 */ 756FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */ 757FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */ 758FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7) 759FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7) 760FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7) 761/** @} */ 762 763/** 764 * Render Target message function control bits: 765 * @{ 766 */ 767FF(rt_last, 768 /* 4: */ MD(11), MD(11), 769 /* 4.5: */ MD(11), MD(11), 770 /* 5: */ MD(11), MD(11), 771 /* 6: */ MD(12), MD(12), 772 /* 7: */ MD(12), MD(12), 773 /* 8: */ MD(12), MD(12)) 774FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6) 775F(rt_message_type, MD(10), MD( 8)) 776/** @} */ 777 778/** 779 * Thread Spawn message function control bits: 780 * @{ 781 */ 782F(ts_resource_select, MD( 4), MD( 4)) 783F(ts_request_type, MD( 1), MD( 1)) 784F(ts_opcode, MD( 0), MD( 0)) 785/** @} */ 786 787/** 788 * Pixel Interpolator message function control bits: 789 * @{ 790 */ 791F(pi_simd_mode, MD(16), MD(16)) 792F(pi_nopersp, MD(14), MD(14)) 793F(pi_message_type, MD(13), MD(12)) 794F(pi_slot_group, MD(11), MD(11)) 795F(pi_message_data, MD(7), MD(0)) 796/** @} */ 797 798/** 799 * Immediates: 800 * @{ 801 */ 802static inline int 803brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn) 804{ 805 (void) devinfo; 806 return brw_inst_bits(insn, 127, 96); 807} 808 809static inline unsigned 810brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn) 811{ 812 (void) devinfo; 813 return brw_inst_bits(insn, 127, 96); 814} 815 816static inline uint64_t 817brw_inst_imm_uq(MAYBE_UNUSED const struct gen_device_info *devinfo, 818 const brw_inst *insn) 819{ 820 assert(devinfo->gen >= 8); 821 return brw_inst_bits(insn, 127, 64); 822} 823 824static inline float 825brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn) 826{ 827 union { 828 float f; 829 uint32_t u; 830 } ft; 831 (void) devinfo; 832 ft.u = brw_inst_bits(insn, 127, 96); 833 return ft.f; 834} 835 836static inline double 837brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn) 838{ 839 union { 840 double d; 841 uint64_t u; 842 } dt; 843 (void) devinfo; 844 dt.u = brw_inst_bits(insn, 127, 64); 845 return dt.d; 846} 847 848static inline void 849brw_inst_set_imm_d(const struct gen_device_info *devinfo, 850 brw_inst *insn, int value) 851{ 852 (void) devinfo; 853 return brw_inst_set_bits(insn, 127, 96, value); 854} 855 856static inline void 857brw_inst_set_imm_ud(const struct gen_device_info *devinfo, 858 brw_inst *insn, unsigned value) 859{ 860 (void) devinfo; 861 return brw_inst_set_bits(insn, 127, 96, value); 862} 863 864static inline void 865brw_inst_set_imm_f(const struct gen_device_info *devinfo, 866 brw_inst *insn, float value) 867{ 868 union { 869 float f; 870 uint32_t u; 871 } ft; 872 (void) devinfo; 873 ft.f = value; 874 brw_inst_set_bits(insn, 127, 96, ft.u); 875} 876 877static inline void 878brw_inst_set_imm_df(const struct gen_device_info *devinfo, 879 brw_inst *insn, double value) 880{ 881 union { 882 double d; 883 uint64_t u; 884 } dt; 885 (void) devinfo; 886 dt.d = value; 887 brw_inst_set_bits(insn, 127, 64, dt.u); 888} 889 890static inline void 891brw_inst_set_imm_uq(const struct gen_device_info *devinfo, 892 brw_inst *insn, uint64_t value) 893{ 894 (void) devinfo; 895 brw_inst_set_bits(insn, 127, 64, value); 896} 897 898/** @} */ 899 900#define REG_TYPE(reg) \ 901static inline void \ 902brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \ 903 brw_inst *inst, enum brw_reg_file file, \ 904 enum brw_reg_type type) \ 905{ \ 906 assert(file <= BRW_IMMEDIATE_VALUE); \ 907 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \ 908 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \ 909 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \ 910} \ 911 \ 912static inline enum brw_reg_type \ 913brw_inst_##reg##_type(const struct gen_device_info *devinfo, \ 914 const brw_inst *inst) \ 915{ \ 916 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \ 917 (unsigned) BRW_GENERAL_REGISTER_FILE : \ 918 brw_inst_##reg##_reg_file(devinfo, inst); \ 919 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \ 920 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \ 921} 922 923REG_TYPE(dst) 924REG_TYPE(src0) 925REG_TYPE(src1) 926#undef REG_TYPE 927 928 929/* The AddrImm fields are split into two discontiguous sections on Gen8+ */ 930#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \ 931static inline void \ 932brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \ 933 brw_inst *inst, \ 934 unsigned value) \ 935{ \ 936 assert((value & ~0x3ff) == 0); \ 937 if (devinfo->gen >= 8) { \ 938 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \ 939 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \ 940 } else { \ 941 brw_inst_set_bits(inst, g4_high, g4_low, value); \ 942 } \ 943} \ 944static inline unsigned \ 945brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \ 946 const brw_inst *inst) \ 947{ \ 948 if (devinfo->gen >= 8) { \ 949 return brw_inst_bits(inst, g8_high, g8_low) | \ 950 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ 951 } else { \ 952 return brw_inst_bits(inst, g4_high, g4_low); \ 953 } \ 954} 955 956/* AddrImm[9:0] for Align1 Indirect Addressing */ 957/* -Gen 4- ----Gen8---- */ 958BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96) 959BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64) 960BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48) 961 962#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \ 963static inline void \ 964brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \ 965 brw_inst *inst, unsigned value) \ 966{ \ 967 assert((value & ~0x3ff) == 0); \ 968 if (devinfo->gen >= 8) { \ 969 assert(GET_BITS(value, 3, 0) == 0); \ 970 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \ 971 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \ 972 } else { \ 973 brw_inst_set_bits(inst, g4_high, g4_low, value); \ 974 } \ 975} \ 976static inline unsigned \ 977brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \ 978 const brw_inst *inst) \ 979{ \ 980 if (devinfo->gen >= 8) { \ 981 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \ 982 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ 983 } else { \ 984 return brw_inst_bits(inst, g4_high, g4_low); \ 985 } \ 986} 987 988/* AddrImm[9:0] for Align16 Indirect Addressing: 989 * Compared to Align1, these are missing the low 4 bits. 990 * -Gen 4- ----Gen8---- 991 */ 992BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100) 993BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68) 994BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52) 995BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68) 996BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52) 997 998/** 999 * Fetch a set of contiguous bits from the instruction. 1000 * 1001 * Bits indices range from 0..127; fields may not cross 64-bit boundaries. 1002 */ 1003static inline uint64_t 1004brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low) 1005{ 1006 /* We assume the field doesn't cross 64-bit boundaries. */ 1007 const unsigned word = high / 64; 1008 assert(word == low / 64); 1009 1010 high %= 64; 1011 low %= 64; 1012 1013 const uint64_t mask = (~0ull >> (64 - (high - low + 1))); 1014 1015 return (inst->data[word] >> low) & mask; 1016} 1017 1018/** 1019 * Set bits in the instruction, with proper shifting and masking. 1020 * 1021 * Bits indices range from 0..127; fields may not cross 64-bit boundaries. 1022 */ 1023static inline void 1024brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) 1025{ 1026 const unsigned word = high / 64; 1027 assert(word == low / 64); 1028 1029 high %= 64; 1030 low %= 64; 1031 1032 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low; 1033 1034 /* Make sure the supplied value actually fits in the given bitfield. */ 1035 assert((value & (mask >> low)) == value); 1036 1037 inst->data[word] = (inst->data[word] & ~mask) | (value << low); 1038} 1039 1040#undef BRW_IA16_ADDR_IMM 1041#undef BRW_IA1_ADDR_IMM 1042#undef MD 1043#undef F8 1044#undef FF 1045#undef BOUNDS 1046#undef F 1047#undef FC 1048 1049typedef struct { 1050 uint64_t data; 1051} brw_compact_inst; 1052 1053/** 1054 * Fetch a set of contiguous bits from the compacted instruction. 1055 * 1056 * Bits indices range from 0..63. 1057 */ 1058static inline unsigned 1059brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low) 1060{ 1061 const uint64_t mask = (1ull << (high - low + 1)) - 1; 1062 1063 return (inst->data >> low) & mask; 1064} 1065 1066/** 1067 * Set bits in the compacted instruction. 1068 * 1069 * Bits indices range from 0..63. 1070 */ 1071static inline void 1072brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, 1073 uint64_t value) 1074{ 1075 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low; 1076 1077 /* Make sure the supplied value actually fits in the given bitfield. */ 1078 assert((value & (mask >> low)) == value); 1079 1080 inst->data = (inst->data & ~mask) | (value << low); 1081} 1082 1083#define FC(name, high, low, assertions) \ 1084static inline void \ 1085brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \ 1086 brw_compact_inst *inst, unsigned v) \ 1087{ \ 1088 assert(assertions); \ 1089 (void) devinfo; \ 1090 brw_compact_inst_set_bits(inst, high, low, v); \ 1091} \ 1092static inline unsigned \ 1093brw_compact_inst_##name(const struct gen_device_info *devinfo, \ 1094 const brw_compact_inst *inst) \ 1095{ \ 1096 assert(assertions); \ 1097 (void) devinfo; \ 1098 return brw_compact_inst_bits(inst, high, low); \ 1099} 1100 1101/* A simple macro for fields which stay in the same place on all generations. */ 1102#define F(name, high, low) FC(name, high, low, true) 1103 1104F(src1_reg_nr, 63, 56) 1105F(src0_reg_nr, 55, 48) 1106F(dst_reg_nr, 47, 40) 1107F(src1_index, 39, 35) 1108F(src0_index, 34, 30) 1109F(cmpt_control, 29, 29) /* Same location as brw_inst */ 1110FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6) 1111F(cond_modifier, 27, 24) /* Same location as brw_inst */ 1112FC(acc_wr_control, 23, 23, devinfo->gen >= 6) 1113FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5) 1114F(subreg_index, 22, 18) 1115F(datatype_index, 17, 13) 1116F(control_index, 12, 8) 1117F(debug_control, 7, 7) 1118F(opcode, 6, 0) /* Same location as brw_inst */ 1119 1120/** 1121 * (Gen8+) Compacted three-source instructions: 1122 * @{ 1123 */ 1124FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8) 1125FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8) 1126FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8) 1127FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8) 1128FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8) 1129FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8) 1130FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8) 1131FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8) 1132FC(3src_saturate, 31, 31, devinfo->gen >= 8) 1133FC(3src_debug_control, 30, 30, devinfo->gen >= 8) 1134FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8) 1135FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8) 1136/* Reserved */ 1137FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8) 1138FC(3src_source_index, 11, 10, devinfo->gen >= 8) 1139FC(3src_control_index, 9, 8, devinfo->gen >= 8) 1140/* Bit 7 is Reserved (for future Opcode expansion) */ 1141FC(3src_opcode, 6, 0, devinfo->gen >= 8) 1142/** @} */ 1143 1144#undef F 1145 1146#ifdef __cplusplus 1147} 1148#endif 1149 1150#endif 1151