1b8e80941Smrg/* 2b8e80941Smrg * Copyright © 2018 Intel Corporation 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 9b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21b8e80941Smrg * IN THE SOFTWARE. 22b8e80941Smrg * 23b8e80941Smrg */ 24b8e80941Smrg 25b8e80941Smrg#ifndef INTEL_AUB_READ 26b8e80941Smrg#define INTEL_AUB_READ 27b8e80941Smrg 28b8e80941Smrg#include <stdint.h> 29b8e80941Smrg 30b8e80941Smrg#include "dev/gen_device_info.h" 31b8e80941Smrg#include "drm-uapi/i915_drm.h" 32b8e80941Smrg 33b8e80941Smrg#ifdef __cplusplus 34b8e80941Smrgextern "C" { 35b8e80941Smrg#endif 36b8e80941Smrg 37b8e80941Smrgstruct aub_read { 38b8e80941Smrg /* Caller's data */ 39b8e80941Smrg void *user_data; 40b8e80941Smrg 41b8e80941Smrg void (*error)(void *user_data, const void *aub_data, const char *msg); 42b8e80941Smrg 43b8e80941Smrg void (*info)(void *user_data, int pci_id, const char *app_name); 44b8e80941Smrg 45b8e80941Smrg void (*local_write)(void *user_data, uint64_t phys_addr, const void *data, uint32_t data_len); 46b8e80941Smrg void (*phys_write)(void *user_data, uint64_t phys_addr, const void *data, uint32_t data_len); 47b8e80941Smrg void (*ggtt_write)(void *user_data, uint64_t phys_addr, const void *data, uint32_t data_len); 48b8e80941Smrg void (*ggtt_entry_write)(void *user_data, uint64_t phys_addr, 49b8e80941Smrg const void *data, uint32_t data_len); 50b8e80941Smrg 51b8e80941Smrg void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value); 52b8e80941Smrg 53b8e80941Smrg void (*ring_write)(void *user_data, enum drm_i915_gem_engine_class engine, 54b8e80941Smrg const void *data, uint32_t data_len); 55b8e80941Smrg void (*execlist_write)(void *user_data, enum drm_i915_gem_engine_class engine, 56b8e80941Smrg uint64_t context_descriptor); 57b8e80941Smrg 58b8e80941Smrg /* Reader's data */ 59b8e80941Smrg uint32_t render_elsp[4]; 60b8e80941Smrg int render_elsp_index; 61b8e80941Smrg uint32_t video_elsp[4]; 62b8e80941Smrg int video_elsp_index; 63b8e80941Smrg uint32_t blitter_elsp[4]; 64b8e80941Smrg int blitter_elsp_index; 65b8e80941Smrg 66b8e80941Smrg struct gen_device_info devinfo; 67b8e80941Smrg}; 68b8e80941Smrg 69b8e80941Smrgint aub_read_command(struct aub_read *read, const void *data, uint32_t data_len); 70b8e80941Smrg 71b8e80941Smrg#ifdef __cplusplus 72b8e80941Smrg} 73b8e80941Smrg#endif 74b8e80941Smrg 75b8e80941Smrg#endif /* INTEL_AUB_READ */ 76