1/*
2 * Copyright 2003 VMware, Inc.
3 * Copyright 2009, 2012 Intel Corporation.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include "main/mtypes.h"
28#include "main/condrender.h"
29#include "swrast/swrast.h"
30#include "drivers/common/meta.h"
31
32#include "intel_batchbuffer.h"
33#include "intel_fbo.h"
34#include "intel_mipmap_tree.h"
35
36#include "brw_context.h"
37#include "brw_blorp.h"
38#include "brw_defines.h"
39
40#define FILE_DEBUG_FLAG DEBUG_BLIT
41
42static const char *buffer_names[] = {
43   [BUFFER_FRONT_LEFT] = "front",
44   [BUFFER_BACK_LEFT] = "back",
45   [BUFFER_FRONT_RIGHT] = "front right",
46   [BUFFER_BACK_RIGHT] = "back right",
47   [BUFFER_DEPTH] = "depth",
48   [BUFFER_STENCIL] = "stencil",
49   [BUFFER_ACCUM] = "accum",
50   [BUFFER_AUX0] = "aux0",
51   [BUFFER_COLOR0] = "color0",
52   [BUFFER_COLOR1] = "color1",
53   [BUFFER_COLOR2] = "color2",
54   [BUFFER_COLOR3] = "color3",
55   [BUFFER_COLOR4] = "color4",
56   [BUFFER_COLOR5] = "color5",
57   [BUFFER_COLOR6] = "color6",
58   [BUFFER_COLOR7] = "color7",
59};
60
61static void
62debug_mask(const char *name, GLbitfield mask)
63{
64   GLuint i;
65
66   if (unlikely(INTEL_DEBUG & DEBUG_BLIT)) {
67      DBG("%s clear:", name);
68      for (i = 0; i < BUFFER_COUNT; i++) {
69	 if (mask & (1 << i))
70	    DBG(" %s", buffer_names[i]);
71      }
72      DBG("\n");
73   }
74}
75
76/**
77 * Returns true if the scissor is a noop (cuts out nothing).
78 */
79static bool
80noop_scissor(struct gl_framebuffer *fb)
81{
82   return fb->_Xmin <= 0 &&
83          fb->_Ymin <= 0 &&
84          fb->_Xmax >= fb->Width &&
85          fb->_Ymax >= fb->Height;
86}
87
88/**
89 * Implements fast depth clears on gen6+.
90 *
91 * Fast clears basically work by setting a flag in each of the subspans
92 * represented in the HiZ buffer that says "When you need the depth values for
93 * this subspan, it's the hardware's current clear value."  Then later rendering
94 * can just use the static clear value instead of referencing memory.
95 *
96 * The tricky part of the implementation is that you have to have the clear
97 * value that was used on the depth buffer in place for all further rendering,
98 * at least until a resolve to the real depth buffer happens.
99 */
100static bool
101brw_fast_clear_depth(struct gl_context *ctx)
102{
103   struct brw_context *brw = brw_context(ctx);
104   struct gl_framebuffer *fb = ctx->DrawBuffer;
105   struct intel_renderbuffer *depth_irb =
106      intel_get_renderbuffer(fb, BUFFER_DEPTH);
107   struct intel_mipmap_tree *mt = depth_irb->mt;
108   struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
109   const struct gen_device_info *devinfo = &brw->screen->devinfo;
110
111   if (devinfo->gen < 6)
112      return false;
113
114   if (!intel_renderbuffer_has_hiz(depth_irb))
115      return false;
116
117   /* We only handle full buffer clears -- otherwise you'd have to track whether
118    * a previous clear had happened at a different clear value and resolve it
119    * first.
120    */
121   if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
122      perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
123                 "Possible 5%% performance win if avoided.\n",
124                 mt->surf.logical_level0_px.width,
125                 mt->surf.logical_level0_px.height);
126      return false;
127   }
128
129   switch (mt->format) {
130   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
131   case MESA_FORMAT_Z24_UNORM_S8_UINT:
132      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
133       *
134       *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
135       *      enabled (the legacy method of clearing must be performed):
136       *
137       *      - If the depth buffer format is D32_FLOAT_S8X24_UINT or
138       *        D24_UNORM_S8_UINT.
139       */
140      return false;
141
142   case MESA_FORMAT_Z_UNORM16:
143      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
144       *
145       *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
146       *      enabled (the legacy method of clearing must be performed):
147       *
148       *      - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
149       *        width of the map (LOD0) is not multiple of 16, fast clear
150       *        optimization must be disabled.
151       */
152      if (devinfo->gen == 6 &&
153          (minify(mt->surf.phys_level0_sa.width,
154                  depth_irb->mt_level - mt->first_level) % 16) != 0)
155	 return false;
156      break;
157
158   default:
159      break;
160   }
161
162   /* Quantize the clear value to what can be stored in the actual depth
163    * buffer.  This makes the following check more accurate because it now
164    * checks if the actual depth bits will match.  It also prevents us from
165    * getting a too-accurate depth value during depth testing or when sampling
166    * with HiZ enabled.
167    */
168   float clear_value =
169      mt->format == MESA_FORMAT_Z_FLOAT32 ? ctx->Depth.Clear :
170      _mesa_lroundeven(ctx->Depth.Clear * fb->_DepthMax) / (float)(fb->_DepthMax);
171
172   const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1;
173
174   /* If we're clearing to a new clear value, then we need to resolve any clear
175    * flags out of the HiZ buffer into the real depth buffer.
176    */
177   if (mt->fast_clear_color.f32[0] != clear_value) {
178      for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
179         if (!intel_miptree_level_has_hiz(mt, level))
180            continue;
181
182         const unsigned level_layers = brw_get_num_logical_layers(mt, level);
183
184         for (uint32_t layer = 0; layer < level_layers; layer++) {
185            if (level == depth_irb->mt_level &&
186                layer >= depth_irb->mt_layer &&
187                layer < depth_irb->mt_layer + num_layers) {
188               /* We're going to clear this layer anyway.  Leave it alone. */
189               continue;
190            }
191
192            enum isl_aux_state aux_state =
193               intel_miptree_get_aux_state(mt, level, layer);
194
195            if (aux_state != ISL_AUX_STATE_CLEAR &&
196                aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
197               /* This slice doesn't have any fast-cleared bits. */
198               continue;
199            }
200
201            /* If we got here, then the level may have fast-clear bits that
202             * use the old clear value.  We need to do a depth resolve to get
203             * rid of their use of the clear value before we can change it.
204             * Fortunately, few applications ever change their depth clear
205             * value so this shouldn't happen often.
206             */
207            intel_hiz_exec(brw, mt, level, layer, 1,
208                           ISL_AUX_OP_FULL_RESOLVE);
209            intel_miptree_set_aux_state(brw, mt, level, layer, 1,
210                                        ISL_AUX_STATE_RESOLVED);
211         }
212      }
213
214      const union isl_color_value clear_color = { .f32 = {clear_value, } };
215      intel_miptree_set_clear_color(brw, mt, clear_color);
216   }
217
218   for (unsigned a = 0; a < num_layers; a++) {
219      enum isl_aux_state aux_state =
220         intel_miptree_get_aux_state(mt, depth_irb->mt_level,
221                                     depth_irb->mt_layer + a);
222
223      if (aux_state != ISL_AUX_STATE_CLEAR) {
224         intel_hiz_exec(brw, mt, depth_irb->mt_level,
225                        depth_irb->mt_layer + a, 1,
226                        ISL_AUX_OP_FAST_CLEAR);
227      }
228   }
229
230   intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
231                               depth_irb->mt_layer, num_layers,
232                               ISL_AUX_STATE_CLEAR);
233   return true;
234}
235
236/**
237 * Called by ctx->Driver.Clear.
238 */
239static void
240brw_clear(struct gl_context *ctx, GLbitfield mask)
241{
242   struct brw_context *brw = brw_context(ctx);
243   struct gl_framebuffer *fb = ctx->DrawBuffer;
244   const struct gen_device_info *devinfo = &brw->screen->devinfo;
245   bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
246
247   if (!_mesa_check_conditional_render(ctx))
248      return;
249
250   if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
251      brw->front_buffer_dirty = true;
252   }
253
254   intel_prepare_render(brw);
255   brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
256
257   if (mask & BUFFER_BIT_DEPTH) {
258      if (brw_fast_clear_depth(ctx)) {
259	 DBG("fast clear: depth\n");
260	 mask &= ~BUFFER_BIT_DEPTH;
261      }
262   }
263
264   if (mask & BUFFER_BITS_COLOR) {
265      brw_blorp_clear_color(brw, fb, mask, partial_clear,
266                            ctx->Color.sRGBEnabled);
267      debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
268      mask &= ~BUFFER_BITS_COLOR;
269   }
270
271   if (devinfo->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
272      brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
273      debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
274      mask &= ~BUFFER_BITS_DEPTH_STENCIL;
275   }
276
277   GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
278                                 BUFFER_BIT_DEPTH);
279
280   if (tri_mask) {
281      debug_mask("tri", tri_mask);
282      mask &= ~tri_mask;
283      _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
284   }
285
286   /* Any strange buffers get passed off to swrast.  The only thing that
287    * should be left at this point is the accumulation buffer.
288    */
289   assert((mask & ~BUFFER_BIT_ACCUM) == 0);
290   if (mask) {
291      debug_mask("swrast", mask);
292      _swrast_Clear(ctx, mask);
293   }
294}
295
296
297void
298intelInitClearFuncs(struct dd_function_table *functions)
299{
300   functions->Clear = brw_clear;
301}
302