1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keithw@vmware.com> 30 */ 31 32/** @file brw_curbe.c 33 * 34 * Push constant handling for gen4/5. 35 * 36 * Push constants are constant values (such as GLSL uniforms) that are 37 * pre-loaded into a shader stage's register space at thread spawn time. On 38 * gen4 and gen5, we create a blob in memory containing all the push constants 39 * for all the stages in order. At CMD_CONST_BUFFER time that blob is loaded 40 * into URB space as a constant URB entry (CURBE) so that it can be accessed 41 * quickly at thread setup time. Each individual fixed function unit's state 42 * (brw_vs_state.c for example) tells the hardware which subset of the CURBE 43 * it wants in its register space, and we calculate those areas here under the 44 * BRW_NEW_PUSH_CONSTANT_ALLOCATION state flag. The brw_urb.c allocation will control 45 * how many CURBEs can be loaded into the hardware at once before a pipeline 46 * stall occurs at CMD_CONST_BUFFER time. 47 * 48 * On gen6+, constant handling becomes a much simpler set of per-unit state. 49 * See gen6_upload_vec4_push_constants() in gen6_vs_state.c for that code. 50 */ 51 52 53#include "compiler/nir/nir.h" 54#include "main/context.h" 55#include "main/macros.h" 56#include "main/enums.h" 57#include "program/prog_parameter.h" 58#include "program/prog_print.h" 59#include "program/prog_statevars.h" 60#include "util/bitscan.h" 61#include "intel_batchbuffer.h" 62#include "intel_buffer_objects.h" 63#include "brw_context.h" 64#include "brw_defines.h" 65#include "brw_state.h" 66#include "brw_util.h" 67#include "util/u_math.h" 68 69 70/** 71 * Partition the CURBE between the various users of constant values. 72 * 73 * If the users all fit within the previous allocatation, we avoid changing 74 * the layout because that means reuploading all unit state and uploading new 75 * constant buffers. 76 */ 77static void calculate_curbe_offsets( struct brw_context *brw ) 78{ 79 struct gl_context *ctx = &brw->ctx; 80 /* BRW_NEW_FS_PROG_DATA */ 81 const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16; 82 83 /* BRW_NEW_VS_PROG_DATA */ 84 const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16; 85 GLuint nr_clip_regs = 0; 86 GLuint total_regs; 87 88 /* _NEW_TRANSFORM */ 89 if (ctx->Transform.ClipPlanesEnabled) { 90 GLuint nr_planes = 6 + util_bitcount(ctx->Transform.ClipPlanesEnabled); 91 nr_clip_regs = (nr_planes * 4 + 15) / 16; 92 } 93 94 95 total_regs = nr_fp_regs + nr_vp_regs + nr_clip_regs; 96 97 /* The CURBE allocation size is limited to 32 512-bit units (128 EU 98 * registers, or 1024 floats). See CS_URB_STATE in the gen4 or gen5 99 * (volume 1, part 1) PRMs. 100 * 101 * Note that in brw_fs.cpp we're only loading up to 16 EU registers of 102 * values as push constants before spilling to pull constants, and in 103 * brw_vec4.cpp we're loading up to 32 registers of push constants. An EU 104 * register is 1/2 of one of these URB entry units, so that leaves us 16 EU 105 * regs for clip. 106 */ 107 assert(total_regs <= 32); 108 109 /* Lazy resize: 110 */ 111 if (nr_fp_regs > brw->curbe.wm_size || 112 nr_vp_regs > brw->curbe.vs_size || 113 nr_clip_regs != brw->curbe.clip_size || 114 (total_regs < brw->curbe.total_size / 4 && 115 brw->curbe.total_size > 16)) { 116 117 GLuint reg = 0; 118 119 /* Calculate a new layout: 120 */ 121 reg = 0; 122 brw->curbe.wm_start = reg; 123 brw->curbe.wm_size = nr_fp_regs; reg += nr_fp_regs; 124 brw->curbe.clip_start = reg; 125 brw->curbe.clip_size = nr_clip_regs; reg += nr_clip_regs; 126 brw->curbe.vs_start = reg; 127 brw->curbe.vs_size = nr_vp_regs; reg += nr_vp_regs; 128 brw->curbe.total_size = reg; 129 130 if (0) 131 fprintf(stderr, "curbe wm %d+%d clip %d+%d vs %d+%d\n", 132 brw->curbe.wm_start, 133 brw->curbe.wm_size, 134 brw->curbe.clip_start, 135 brw->curbe.clip_size, 136 brw->curbe.vs_start, 137 brw->curbe.vs_size ); 138 139 brw->ctx.NewDriverState |= BRW_NEW_PUSH_CONSTANT_ALLOCATION; 140 } 141} 142 143 144const struct brw_tracked_state brw_curbe_offsets = { 145 .dirty = { 146 .mesa = _NEW_TRANSFORM, 147 .brw = BRW_NEW_CONTEXT | 148 BRW_NEW_BLORP | 149 BRW_NEW_FS_PROG_DATA | 150 BRW_NEW_VS_PROG_DATA, 151 }, 152 .emit = calculate_curbe_offsets 153}; 154 155 156 157 158/** Uploads the CS_URB_STATE packet. 159 * 160 * Just like brw_vs_state.c and brw_wm_state.c define a URB entry size and 161 * number of entries for their stages, constant buffers do so using this state 162 * packet. Having multiple CURBEs in the URB at the same time allows the 163 * hardware to avoid a pipeline stall between primitives using different 164 * constant buffer contents. 165 */ 166void brw_upload_cs_urb_state(struct brw_context *brw) 167{ 168 BEGIN_BATCH(2); 169 OUT_BATCH(CMD_CS_URB_STATE << 16 | (2-2)); 170 171 /* BRW_NEW_URB_FENCE */ 172 if (brw->urb.csize == 0) { 173 OUT_BATCH(0); 174 } else { 175 /* BRW_NEW_URB_FENCE */ 176 assert(brw->urb.nr_cs_entries); 177 OUT_BATCH((brw->urb.csize - 1) << 4 | brw->urb.nr_cs_entries); 178 } 179 ADVANCE_BATCH(); 180} 181 182static const GLfloat fixed_plane[6][4] = { 183 { 0, 0, -1, 1 }, 184 { 0, 0, 1, 1 }, 185 { 0, -1, 0, 1 }, 186 { 0, 1, 0, 1 }, 187 {-1, 0, 0, 1 }, 188 { 1, 0, 0, 1 } 189}; 190 191/** 192 * Gathers together all the uniform values into a block of memory to be 193 * uploaded into the CURBE, then emits the state packet telling the hardware 194 * the new location. 195 */ 196static void 197brw_upload_constant_buffer(struct brw_context *brw) 198{ 199 const struct gen_device_info *devinfo = &brw->screen->devinfo; 200 struct gl_context *ctx = &brw->ctx; 201 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ 202 const GLuint sz = brw->curbe.total_size; 203 const GLuint bufsz = sz * 16 * sizeof(GLfloat); 204 gl_constant_value *buf; 205 GLuint i; 206 gl_clip_plane *clip_planes; 207 208 /* BRW_NEW_FRAGMENT_PROGRAM */ 209 struct gl_program *fp = brw->programs[MESA_SHADER_FRAGMENT]; 210 211 /* BRW_NEW_VERTEX_PROGRAM */ 212 struct gl_program *vp = brw->programs[MESA_SHADER_VERTEX]; 213 214 if (sz == 0) { 215 goto emit; 216 } 217 218 buf = brw_upload_space(&brw->upload, bufsz, 64, 219 &brw->curbe.curbe_bo, &brw->curbe.curbe_offset); 220 221 STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float)); 222 223 /* fragment shader constants */ 224 if (brw->curbe.wm_size) { 225 _mesa_load_state_parameters(ctx, fp->Parameters); 226 227 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ 228 GLuint offset = brw->curbe.wm_start * 16; 229 230 /* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */ 231 brw_populate_constant_data(brw, fp, &brw->wm.base, &buf[offset], 232 brw->wm.base.prog_data->param, 233 brw->wm.base.prog_data->nr_params); 234 } 235 236 /* clipper constants */ 237 if (brw->curbe.clip_size) { 238 GLuint offset = brw->curbe.clip_start * 16; 239 GLbitfield mask; 240 241 /* If any planes are going this way, send them all this way: 242 */ 243 for (i = 0; i < 6; i++) { 244 buf[offset + i * 4 + 0].f = fixed_plane[i][0]; 245 buf[offset + i * 4 + 1].f = fixed_plane[i][1]; 246 buf[offset + i * 4 + 2].f = fixed_plane[i][2]; 247 buf[offset + i * 4 + 3].f = fixed_plane[i][3]; 248 } 249 250 /* Clip planes: _NEW_TRANSFORM plus _NEW_PROJECTION to get to 251 * clip-space: 252 */ 253 clip_planes = brw_select_clip_planes(ctx); 254 mask = ctx->Transform.ClipPlanesEnabled; 255 while (mask) { 256 const int j = u_bit_scan(&mask); 257 buf[offset + i * 4 + 0].f = clip_planes[j][0]; 258 buf[offset + i * 4 + 1].f = clip_planes[j][1]; 259 buf[offset + i * 4 + 2].f = clip_planes[j][2]; 260 buf[offset + i * 4 + 3].f = clip_planes[j][3]; 261 i++; 262 } 263 } 264 265 /* vertex shader constants */ 266 if (brw->curbe.vs_size) { 267 _mesa_load_state_parameters(ctx, vp->Parameters); 268 269 GLuint offset = brw->curbe.vs_start * 16; 270 271 /* BRW_NEW_VS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */ 272 brw_populate_constant_data(brw, vp, &brw->vs.base, &buf[offset], 273 brw->vs.base.prog_data->param, 274 brw->vs.base.prog_data->nr_params); 275 } 276 277 if (0) { 278 for (i = 0; i < sz*16; i+=4) 279 fprintf(stderr, "curbe %d.%d: %f %f %f %f\n", i/8, i&4, 280 buf[i+0].f, buf[i+1].f, buf[i+2].f, buf[i+3].f); 281 } 282 283 /* Because this provokes an action (ie copy the constants into the 284 * URB), it shouldn't be shortcircuited if identical to the 285 * previous time - because eg. the urb destination may have 286 * changed, or the urb contents different to last time. 287 * 288 * Note that the data referred to is actually copied internally, 289 * not just used in place according to passed pointer. 290 * 291 * It appears that the CS unit takes care of using each available 292 * URB entry (Const URB Entry == CURBE) in turn, and issuing 293 * flushes as necessary when doublebuffering of CURBEs isn't 294 * possible. 295 */ 296 297emit: 298 /* BRW_NEW_URB_FENCE: From the gen4 PRM, volume 1, section 3.9.8 299 * (CONSTANT_BUFFER (CURBE Load)): 300 * 301 * "Modifying the CS URB allocation via URB_FENCE invalidates any 302 * previous CURBE entries. Therefore software must subsequently 303 * [re]issue a CONSTANT_BUFFER command before CURBE data can be used 304 * in the pipeline." 305 */ 306 BEGIN_BATCH(2); 307 if (brw->curbe.total_size == 0) { 308 OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); 309 OUT_BATCH(0); 310 } else { 311 OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2)); 312 OUT_RELOC(brw->curbe.curbe_bo, 0, 313 (brw->curbe.total_size - 1) + brw->curbe.curbe_offset); 314 } 315 ADVANCE_BATCH(); 316 317 /* Work around a Broadwater/Crestline depth interpolator bug. The 318 * following sequence will cause GPU hangs: 319 * 320 * 1. Change state so that all depth related fields in CC_STATE are 321 * disabled, and in WM_STATE, only "PS Use Source Depth" is enabled. 322 * 2. Emit a CONSTANT_BUFFER packet. 323 * 3. Draw via 3DPRIMITIVE. 324 * 325 * The recommended workaround is to emit a non-pipelined state change after 326 * emitting CONSTANT_BUFFER, in order to drain the windowizer pipeline. 327 * 328 * We arbitrarily choose 3DSTATE_GLOBAL_DEPTH_CLAMP_OFFSET (as it's small), 329 * and always emit it when "PS Use Source Depth" is set. We could be more 330 * precise, but the additional complexity is probably not worth it. 331 * 332 * BRW_NEW_FRAGMENT_PROGRAM 333 */ 334 if (devinfo->gen == 4 && !devinfo->is_g4x && 335 (fp->info.inputs_read & (1 << VARYING_SLOT_POS))) { 336 BEGIN_BATCH(2); 337 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); 338 OUT_BATCH(0); 339 ADVANCE_BATCH(); 340 } 341} 342 343const struct brw_tracked_state brw_constant_buffer = { 344 .dirty = { 345 .mesa = _NEW_PROGRAM_CONSTANTS, 346 .brw = BRW_NEW_BATCH | 347 BRW_NEW_BLORP | 348 BRW_NEW_PUSH_CONSTANT_ALLOCATION | 349 BRW_NEW_FRAGMENT_PROGRAM | 350 BRW_NEW_FS_PROG_DATA | 351 BRW_NEW_PSP | /* Implicit - hardware requires this, not used above */ 352 BRW_NEW_URB_FENCE | 353 BRW_NEW_VS_PROG_DATA, 354 }, 355 .emit = brw_upload_constant_buffer, 356}; 357