1/* 2 * Copyright 2003 VMware, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "drm-uapi/drm_fourcc.h" 27#include <errno.h> 28#include <time.h> 29#include <unistd.h> 30#include "main/context.h" 31#include "main/framebuffer.h" 32#include "main/renderbuffer.h" 33#include "main/texobj.h" 34#include "main/hash.h" 35#include "main/fbobject.h" 36#include "main/version.h" 37#include "main/glthread.h" 38#include "swrast/s_renderbuffer.h" 39#include "util/ralloc.h" 40#include "util/disk_cache.h" 41#include "brw_defines.h" 42#include "brw_state.h" 43#include "compiler/nir/nir.h" 44 45#include "utils.h" 46#include "util/disk_cache.h" 47#include "util/xmlpool.h" 48 49#include "common/gen_defines.h" 50 51static const __DRIconfigOptionsExtension brw_config_options = { 52 .base = { __DRI_CONFIG_OPTIONS, 1 }, 53 .xml = 54DRI_CONF_BEGIN 55 DRI_CONF_SECTION_PERFORMANCE 56 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED, 57 * DRI_CONF_BO_REUSE_ALL 58 */ 59 DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1") 60 DRI_CONF_DESC_BEGIN(en, "Buffer object reuse") 61 DRI_CONF_ENUM(0, "Disable buffer object reuse") 62 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects") 63 DRI_CONF_DESC_END 64 DRI_CONF_OPT_END 65 DRI_CONF_MESA_NO_ERROR("false") 66 DRI_CONF_MESA_GLTHREAD("false") 67 DRI_CONF_SECTION_END 68 69 DRI_CONF_SECTION_QUALITY 70 DRI_CONF_PRECISE_TRIG("false") 71 72 DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1) 73 DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the " 74 "given integer. If negative, then do not clamp.") 75 DRI_CONF_OPT_END 76 DRI_CONF_SECTION_END 77 78 DRI_CONF_SECTION_DEBUG 79 DRI_CONF_ALWAYS_FLUSH_BATCH("false") 80 DRI_CONF_ALWAYS_FLUSH_CACHE("false") 81 DRI_CONF_DISABLE_THROTTLING("false") 82 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false") 83 DRI_CONF_FORCE_GLSL_VERSION(0) 84 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false") 85 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false") 86 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false") 87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false") 88 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false") 89 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false") 90 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false") 91 DRI_CONF_FORCE_GLSL_ABS_SQRT("false") 92 93 DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") 94 DRI_CONF_DESC(en, "Perform code generation at shader link time.") 95 DRI_CONF_OPT_END 96 DRI_CONF_SECTION_END 97 98 DRI_CONF_SECTION_MISCELLANEOUS 99 DRI_CONF_GLSL_ZERO_INIT("false") 100 DRI_CONF_ALLOW_RGB10_CONFIGS("false") 101 DRI_CONF_ALLOW_RGB565_CONFIGS("true") 102 DRI_CONF_SECTION_END 103DRI_CONF_END 104}; 105 106#include "intel_batchbuffer.h" 107#include "intel_buffers.h" 108#include "brw_bufmgr.h" 109#include "intel_fbo.h" 110#include "intel_mipmap_tree.h" 111#include "intel_screen.h" 112#include "intel_tex.h" 113#include "intel_image.h" 114 115#include "brw_context.h" 116 117#include "drm-uapi/i915_drm.h" 118 119/** 120 * For debugging purposes, this returns a time in seconds. 121 */ 122double 123get_time(void) 124{ 125 struct timespec tp; 126 127 clock_gettime(CLOCK_MONOTONIC, &tp); 128 129 return tp.tv_sec + tp.tv_nsec / 1000000000.0; 130} 131 132static const __DRItexBufferExtension intelTexBufferExtension = { 133 .base = { __DRI_TEX_BUFFER, 3 }, 134 135 .setTexBuffer = intelSetTexBuffer, 136 .setTexBuffer2 = intelSetTexBuffer2, 137 .releaseTexBuffer = intelReleaseTexBuffer, 138}; 139 140static void 141intel_dri2_flush_with_flags(__DRIcontext *cPriv, 142 __DRIdrawable *dPriv, 143 unsigned flags, 144 enum __DRI2throttleReason reason) 145{ 146 struct brw_context *brw = cPriv->driverPrivate; 147 148 if (!brw) 149 return; 150 151 struct gl_context *ctx = &brw->ctx; 152 153 _mesa_glthread_finish(ctx); 154 155 FLUSH_VERTICES(ctx, 0); 156 157 if (flags & __DRI2_FLUSH_DRAWABLE) 158 intel_resolve_for_dri2_flush(brw, dPriv); 159 160 if (reason == __DRI2_THROTTLE_SWAPBUFFER) 161 brw->need_swap_throttle = true; 162 if (reason == __DRI2_THROTTLE_FLUSHFRONT) 163 brw->need_flush_throttle = true; 164 165 intel_batchbuffer_flush(brw); 166} 167 168/** 169 * Provides compatibility with loaders that only support the older (version 170 * 1-3) flush interface. 171 * 172 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13. 173 */ 174static void 175intel_dri2_flush(__DRIdrawable *drawable) 176{ 177 intel_dri2_flush_with_flags(drawable->driContextPriv, drawable, 178 __DRI2_FLUSH_DRAWABLE, 179 __DRI2_THROTTLE_SWAPBUFFER); 180} 181 182static const struct __DRI2flushExtensionRec intelFlushExtension = { 183 .base = { __DRI2_FLUSH, 4 }, 184 185 .flush = intel_dri2_flush, 186 .invalidate = dri2InvalidateDrawable, 187 .flush_with_flags = intel_dri2_flush_with_flags, 188}; 189 190static const struct intel_image_format intel_image_formats[] = { 191 { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, 192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } }, 193 194 { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, 195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } }, 196 197 { __DRI_IMAGE_FOURCC_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1, 198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } }, 199 200 { __DRI_IMAGE_FOURCC_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1, 201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } }, 202 203 { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, 205 206 { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, 208 209 { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, 211 212 { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, 213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, 214 215 { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, 216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, 217 218 { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, 219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } }, 220 221 { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, 222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, 223 224 { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, 225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, 226 227 { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1, 228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } }, 229 230 { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, 231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, 232 233 { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1, 234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } }, 235 236 { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 238 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, 239 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, 240 241 { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 243 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 244 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 245 246 { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 248 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, 249 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, 250 251 { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 253 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 254 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 255 256 { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 258 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 259 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 260 261 { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 263 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, 264 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, 265 266 { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 268 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 269 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 270 271 { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 273 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, 274 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, 275 276 { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 278 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 279 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 280 281 { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 283 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 284 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 285 286 { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 288 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, 289 290 { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, 292 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, 293 294 { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, 296 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, 297 298 { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 299 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, 300 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, 301 302 { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 303 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 304 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, 305 306 { __DRI_IMAGE_FOURCC_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1, 307 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, 308 309 { __DRI_IMAGE_FOURCC_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1, 310 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } }, 311 312 /* For YUYV and UYVY buffers, we set up two overlapping DRI images 313 * and treat them as planar buffers in the compositors. 314 * Plane 0 is GR88 and samples YU or YV pairs and places Y into 315 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY 316 * clusters and places pairs and places U into the G component and 317 * V into A. This lets the texture sampler interpolate the Y 318 * components correctly when sampling from plane 0, and interpolate 319 * U and V correctly when sampling from plane 1. */ 320 { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, 321 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, 322 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, 323 { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2, 324 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, 325 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } } 326}; 327 328static const struct { 329 uint64_t modifier; 330 unsigned since_gen; 331} supported_modifiers[] = { 332 { .modifier = DRM_FORMAT_MOD_LINEAR , .since_gen = 1 }, 333 { .modifier = I915_FORMAT_MOD_X_TILED , .since_gen = 1 }, 334 { .modifier = I915_FORMAT_MOD_Y_TILED , .since_gen = 6 }, 335 { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 }, 336}; 337 338static bool 339modifier_is_supported(const struct gen_device_info *devinfo, 340 const struct intel_image_format *fmt, int dri_format, 341 uint64_t modifier) 342{ 343 const struct isl_drm_modifier_info *modinfo = 344 isl_drm_modifier_get_info(modifier); 345 int i; 346 347 /* ISL had better know about the modifier */ 348 if (!modinfo) 349 return false; 350 351 if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) { 352 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */ 353 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) 354 return false; 355 356 /* CCS_E is not supported for planar images */ 357 if (fmt && fmt->nplanes > 1) 358 return false; 359 360 if (fmt) { 361 assert(dri_format == 0); 362 dri_format = fmt->planes[0].dri_format; 363 } 364 365 mesa_format format = driImageFormatToGLFormat(dri_format); 366 /* Whether or not we support compression is based on the RGBA non-sRGB 367 * version of the format. 368 */ 369 format = _mesa_format_fallback_rgbx_to_rgba(format); 370 format = _mesa_get_srgb_format_linear(format); 371 if (!isl_format_supports_ccs_e(devinfo, 372 brw_isl_format_for_mesa_format(format))) 373 return false; 374 } 375 376 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) { 377 if (supported_modifiers[i].modifier != modifier) 378 continue; 379 380 return supported_modifiers[i].since_gen <= devinfo->gen; 381 } 382 383 return false; 384} 385 386static uint64_t 387tiling_to_modifier(uint32_t tiling) 388{ 389 static const uint64_t map[] = { 390 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR, 391 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED, 392 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED, 393 }; 394 395 assert(tiling < ARRAY_SIZE(map)); 396 397 return map[tiling]; 398} 399 400static void 401intel_image_warn_if_unaligned(__DRIimage *image, const char *func) 402{ 403 uint32_t tiling, swizzle; 404 brw_bo_get_tiling(image->bo, &tiling, &swizzle); 405 406 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { 407 _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary", 408 func, image->offset); 409 } 410} 411 412static const struct intel_image_format * 413intel_image_format_lookup(int fourcc) 414{ 415 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { 416 if (intel_image_formats[i].fourcc == fourcc) 417 return &intel_image_formats[i]; 418 } 419 420 return NULL; 421} 422 423static boolean 424intel_image_get_fourcc(__DRIimage *image, int *fourcc) 425{ 426 if (image->planar_format) { 427 *fourcc = image->planar_format->fourcc; 428 return true; 429 } 430 431 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { 432 if (intel_image_formats[i].planes[0].dri_format == image->dri_format) { 433 *fourcc = intel_image_formats[i].fourcc; 434 return true; 435 } 436 } 437 return false; 438} 439 440static __DRIimage * 441intel_allocate_image(struct intel_screen *screen, int dri_format, 442 void *loaderPrivate) 443{ 444 __DRIimage *image; 445 446 image = calloc(1, sizeof *image); 447 if (image == NULL) 448 return NULL; 449 450 image->screen = screen; 451 image->dri_format = dri_format; 452 image->offset = 0; 453 454 image->format = driImageFormatToGLFormat(dri_format); 455 if (dri_format != __DRI_IMAGE_FORMAT_NONE && 456 image->format == MESA_FORMAT_NONE) { 457 free(image); 458 return NULL; 459 } 460 461 image->internal_format = _mesa_get_format_base_format(image->format); 462 image->data = loaderPrivate; 463 464 return image; 465} 466 467/** 468 * Sets up a DRIImage structure to point to a slice out of a miptree. 469 */ 470static void 471intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, 472 struct intel_mipmap_tree *mt, GLuint level, 473 GLuint zoffset) 474{ 475 intel_miptree_make_shareable(brw, mt); 476 477 intel_miptree_check_level_layer(mt, level, zoffset); 478 479 image->width = minify(mt->surf.phys_level0_sa.width, 480 level - mt->first_level); 481 image->height = minify(mt->surf.phys_level0_sa.height, 482 level - mt->first_level); 483 image->pitch = mt->surf.row_pitch_B; 484 485 image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, 486 &image->tile_x, 487 &image->tile_y); 488 489 brw_bo_unreference(image->bo); 490 image->bo = mt->bo; 491 brw_bo_reference(mt->bo); 492} 493 494static __DRIimage * 495intel_create_image_from_name(__DRIscreen *dri_screen, 496 int width, int height, int format, 497 int name, int pitch, void *loaderPrivate) 498{ 499 struct intel_screen *screen = dri_screen->driverPrivate; 500 __DRIimage *image; 501 int cpp; 502 503 image = intel_allocate_image(screen, format, loaderPrivate); 504 if (image == NULL) 505 return NULL; 506 507 if (image->format == MESA_FORMAT_NONE) 508 cpp = 1; 509 else 510 cpp = _mesa_get_format_bytes(image->format); 511 512 image->width = width; 513 image->height = height; 514 image->pitch = pitch * cpp; 515 image->bo = brw_bo_gem_create_from_name(screen->bufmgr, "image", 516 name); 517 if (!image->bo) { 518 free(image); 519 return NULL; 520 } 521 image->modifier = tiling_to_modifier(image->bo->tiling_mode); 522 523 return image; 524} 525 526static __DRIimage * 527intel_create_image_from_renderbuffer(__DRIcontext *context, 528 int renderbuffer, void *loaderPrivate) 529{ 530 __DRIimage *image; 531 struct brw_context *brw = context->driverPrivate; 532 struct gl_context *ctx = &brw->ctx; 533 struct gl_renderbuffer *rb; 534 struct intel_renderbuffer *irb; 535 536 rb = _mesa_lookup_renderbuffer(ctx, renderbuffer); 537 if (!rb) { 538 _mesa_error(ctx, GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); 539 return NULL; 540 } 541 542 irb = intel_renderbuffer(rb); 543 intel_miptree_make_shareable(brw, irb->mt); 544 image = calloc(1, sizeof *image); 545 if (image == NULL) 546 return NULL; 547 548 image->internal_format = rb->InternalFormat; 549 image->format = rb->Format; 550 image->modifier = tiling_to_modifier( 551 isl_tiling_to_i915_tiling(irb->mt->surf.tiling)); 552 image->offset = 0; 553 image->data = loaderPrivate; 554 brw_bo_unreference(image->bo); 555 image->bo = irb->mt->bo; 556 brw_bo_reference(irb->mt->bo); 557 image->width = rb->Width; 558 image->height = rb->Height; 559 image->pitch = irb->mt->surf.row_pitch_B; 560 image->dri_format = driGLFormatToImageFormat(image->format); 561 image->has_depthstencil = irb->mt->stencil_mt? true : false; 562 563 rb->NeedsFinishRenderTexture = true; 564 return image; 565} 566 567static __DRIimage * 568intel_create_image_from_texture(__DRIcontext *context, int target, 569 unsigned texture, int zoffset, 570 int level, 571 unsigned *error, 572 void *loaderPrivate) 573{ 574 __DRIimage *image; 575 struct brw_context *brw = context->driverPrivate; 576 struct gl_texture_object *obj; 577 struct intel_texture_object *iobj; 578 GLuint face = 0; 579 580 obj = _mesa_lookup_texture(&brw->ctx, texture); 581 if (!obj || obj->Target != target) { 582 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 583 return NULL; 584 } 585 586 if (target == GL_TEXTURE_CUBE_MAP) 587 face = zoffset; 588 589 _mesa_test_texobj_completeness(&brw->ctx, obj); 590 iobj = intel_texture_object(obj); 591 if (!obj->_BaseComplete || (level > 0 && !obj->_MipmapComplete)) { 592 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 593 return NULL; 594 } 595 596 if (level < obj->BaseLevel || level > obj->_MaxLevel) { 597 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 598 return NULL; 599 } 600 601 if (target == GL_TEXTURE_3D && obj->Image[face][level]->Depth < zoffset) { 602 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 603 return NULL; 604 } 605 image = calloc(1, sizeof *image); 606 if (image == NULL) { 607 *error = __DRI_IMAGE_ERROR_BAD_ALLOC; 608 return NULL; 609 } 610 611 image->internal_format = obj->Image[face][level]->InternalFormat; 612 image->format = obj->Image[face][level]->TexFormat; 613 image->modifier = tiling_to_modifier( 614 isl_tiling_to_i915_tiling(iobj->mt->surf.tiling)); 615 image->data = loaderPrivate; 616 intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset); 617 image->dri_format = driGLFormatToImageFormat(image->format); 618 image->has_depthstencil = iobj->mt->stencil_mt? true : false; 619 image->planar_format = iobj->planar_format; 620 if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) { 621 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 622 free(image); 623 return NULL; 624 } 625 626 *error = __DRI_IMAGE_ERROR_SUCCESS; 627 return image; 628} 629 630static void 631intel_destroy_image(__DRIimage *image) 632{ 633 brw_bo_unreference(image->bo); 634 free(image); 635} 636 637enum modifier_priority { 638 MODIFIER_PRIORITY_INVALID = 0, 639 MODIFIER_PRIORITY_LINEAR, 640 MODIFIER_PRIORITY_X, 641 MODIFIER_PRIORITY_Y, 642 MODIFIER_PRIORITY_Y_CCS, 643}; 644 645const uint64_t priority_to_modifier[] = { 646 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID, 647 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR, 648 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED, 649 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED, 650 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS, 651}; 652 653static uint64_t 654select_best_modifier(struct gen_device_info *devinfo, 655 int dri_format, 656 const uint64_t *modifiers, 657 const unsigned count) 658{ 659 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID; 660 661 for (int i = 0; i < count; i++) { 662 if (!modifier_is_supported(devinfo, NULL, dri_format, modifiers[i])) 663 continue; 664 665 switch (modifiers[i]) { 666 case I915_FORMAT_MOD_Y_TILED_CCS: 667 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS); 668 break; 669 case I915_FORMAT_MOD_Y_TILED: 670 prio = MAX2(prio, MODIFIER_PRIORITY_Y); 671 break; 672 case I915_FORMAT_MOD_X_TILED: 673 prio = MAX2(prio, MODIFIER_PRIORITY_X); 674 break; 675 case DRM_FORMAT_MOD_LINEAR: 676 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR); 677 break; 678 case DRM_FORMAT_MOD_INVALID: 679 default: 680 break; 681 } 682 } 683 684 return priority_to_modifier[prio]; 685} 686 687static __DRIimage * 688intel_create_image_common(__DRIscreen *dri_screen, 689 int width, int height, int format, 690 unsigned int use, 691 const uint64_t *modifiers, 692 unsigned count, 693 void *loaderPrivate) 694{ 695 __DRIimage *image; 696 struct intel_screen *screen = dri_screen->driverPrivate; 697 uint64_t modifier = DRM_FORMAT_MOD_INVALID; 698 bool ok; 699 700 /* Callers of this may specify a modifier, or a dri usage, but not both. The 701 * newer modifier interface deprecates the older usage flags newer modifier 702 * interface deprecates the older usage flags. 703 */ 704 assert(!(use && count)); 705 706 if (use & __DRI_IMAGE_USE_CURSOR) { 707 if (width != 64 || height != 64) 708 return NULL; 709 modifier = DRM_FORMAT_MOD_LINEAR; 710 } 711 712 if (use & __DRI_IMAGE_USE_LINEAR) 713 modifier = DRM_FORMAT_MOD_LINEAR; 714 715 if (modifier == DRM_FORMAT_MOD_INVALID) { 716 if (modifiers) { 717 /* User requested specific modifiers */ 718 modifier = select_best_modifier(&screen->devinfo, format, 719 modifiers, count); 720 if (modifier == DRM_FORMAT_MOD_INVALID) 721 return NULL; 722 } else { 723 /* Historically, X-tiled was the default, and so lack of modifier means 724 * X-tiled. 725 */ 726 modifier = I915_FORMAT_MOD_X_TILED; 727 } 728 } 729 730 image = intel_allocate_image(screen, format, loaderPrivate); 731 if (image == NULL) 732 return NULL; 733 734 const struct isl_drm_modifier_info *mod_info = 735 isl_drm_modifier_get_info(modifier); 736 737 struct isl_surf surf; 738 ok = isl_surf_init(&screen->isl_dev, &surf, 739 .dim = ISL_SURF_DIM_2D, 740 .format = brw_isl_format_for_mesa_format(image->format), 741 .width = width, 742 .height = height, 743 .depth = 1, 744 .levels = 1, 745 .array_len = 1, 746 .samples = 1, 747 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | 748 ISL_SURF_USAGE_TEXTURE_BIT | 749 ISL_SURF_USAGE_STORAGE_BIT, 750 .tiling_flags = (1 << mod_info->tiling)); 751 assert(ok); 752 if (!ok) { 753 free(image); 754 return NULL; 755 } 756 757 struct isl_surf aux_surf; 758 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) { 759 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0); 760 if (!ok) { 761 free(image); 762 return NULL; 763 } 764 } else { 765 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE); 766 aux_surf.size_B = 0; 767 } 768 769 /* We request that the bufmgr zero the buffer for us for two reasons: 770 * 771 * 1) If a buffer gets re-used from the pool, we don't want to leak random 772 * garbage from our process to some other. 773 * 774 * 2) For images with CCS_E, we want to ensure that the CCS starts off in 775 * a valid state. A CCS value of 0 indicates that the given block is 776 * in the pass-through state which is what we want. 777 */ 778 image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", 779 surf.size_B + aux_surf.size_B, 780 BRW_MEMZONE_OTHER, 781 isl_tiling_to_i915_tiling(mod_info->tiling), 782 surf.row_pitch_B, BO_ALLOC_ZEROED); 783 if (image->bo == NULL) { 784 free(image); 785 return NULL; 786 } 787 image->width = width; 788 image->height = height; 789 image->pitch = surf.row_pitch_B; 790 image->modifier = modifier; 791 792 if (aux_surf.size_B) { 793 image->aux_offset = surf.size_B; 794 image->aux_pitch = aux_surf.row_pitch_B; 795 image->aux_size = aux_surf.size_B; 796 } 797 798 return image; 799} 800 801static __DRIimage * 802intel_create_image(__DRIscreen *dri_screen, 803 int width, int height, int format, 804 unsigned int use, 805 void *loaderPrivate) 806{ 807 return intel_create_image_common(dri_screen, width, height, format, use, NULL, 0, 808 loaderPrivate); 809} 810 811static void * 812intel_map_image(__DRIcontext *context, __DRIimage *image, 813 int x0, int y0, int width, int height, 814 unsigned int flags, int *stride, void **map_info) 815{ 816 struct brw_context *brw = NULL; 817 struct brw_bo *bo = NULL; 818 void *raw_data = NULL; 819 GLuint pix_w = 1; 820 GLuint pix_h = 1; 821 GLint pix_bytes = 1; 822 823 if (!context || !image || !stride || !map_info || *map_info) 824 return NULL; 825 826 if (x0 < 0 || x0 >= image->width || width > image->width - x0) 827 return NULL; 828 829 if (y0 < 0 || y0 >= image->height || height > image->height - y0) 830 return NULL; 831 832 if (flags & MAP_INTERNAL_MASK) 833 return NULL; 834 835 brw = context->driverPrivate; 836 bo = image->bo; 837 838 assert(brw); 839 assert(bo); 840 841 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */ 842 raw_data = brw_bo_map(brw, bo, flags); 843 if (!raw_data) 844 return NULL; 845 846 _mesa_get_format_block_size(image->format, &pix_w, &pix_h); 847 pix_bytes = _mesa_get_format_bytes(image->format); 848 849 assert(pix_w); 850 assert(pix_h); 851 assert(pix_bytes > 0); 852 853 raw_data += (x0 / pix_w) * pix_bytes + (y0 / pix_h) * image->pitch; 854 855 brw_bo_reference(bo); 856 857 *stride = image->pitch; 858 *map_info = bo; 859 860 return raw_data; 861} 862 863static void 864intel_unmap_image(__DRIcontext *context, __DRIimage *image, void *map_info) 865{ 866 struct brw_bo *bo = map_info; 867 868 brw_bo_unmap(bo); 869 brw_bo_unreference(bo); 870} 871 872static __DRIimage * 873intel_create_image_with_modifiers(__DRIscreen *dri_screen, 874 int width, int height, int format, 875 const uint64_t *modifiers, 876 const unsigned count, 877 void *loaderPrivate) 878{ 879 return intel_create_image_common(dri_screen, width, height, format, 0, 880 modifiers, count, loaderPrivate); 881} 882 883static GLboolean 884intel_query_image(__DRIimage *image, int attrib, int *value) 885{ 886 switch (attrib) { 887 case __DRI_IMAGE_ATTRIB_STRIDE: 888 *value = image->pitch; 889 return true; 890 case __DRI_IMAGE_ATTRIB_HANDLE: 891 *value = brw_bo_export_gem_handle(image->bo); 892 return true; 893 case __DRI_IMAGE_ATTRIB_NAME: 894 return !brw_bo_flink(image->bo, (uint32_t *) value); 895 case __DRI_IMAGE_ATTRIB_FORMAT: 896 *value = image->dri_format; 897 return true; 898 case __DRI_IMAGE_ATTRIB_WIDTH: 899 *value = image->width; 900 return true; 901 case __DRI_IMAGE_ATTRIB_HEIGHT: 902 *value = image->height; 903 return true; 904 case __DRI_IMAGE_ATTRIB_COMPONENTS: 905 if (image->planar_format == NULL) 906 return false; 907 *value = image->planar_format->components; 908 return true; 909 case __DRI_IMAGE_ATTRIB_FD: 910 return !brw_bo_gem_export_to_prime(image->bo, value); 911 case __DRI_IMAGE_ATTRIB_FOURCC: 912 return intel_image_get_fourcc(image, value); 913 case __DRI_IMAGE_ATTRIB_NUM_PLANES: 914 if (isl_drm_modifier_has_aux(image->modifier)) { 915 assert(!image->planar_format || image->planar_format->nplanes == 1); 916 *value = 2; 917 } else if (image->planar_format) { 918 *value = image->planar_format->nplanes; 919 } else { 920 *value = 1; 921 } 922 return true; 923 case __DRI_IMAGE_ATTRIB_OFFSET: 924 *value = image->offset; 925 return true; 926 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER: 927 *value = (image->modifier & 0xffffffff); 928 return true; 929 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER: 930 *value = ((image->modifier >> 32) & 0xffffffff); 931 return true; 932 933 default: 934 return false; 935 } 936} 937 938static GLboolean 939intel_query_format_modifier_attribs(__DRIscreen *dri_screen, 940 uint32_t fourcc, uint64_t modifier, 941 int attrib, uint64_t *value) 942{ 943 struct intel_screen *screen = dri_screen->driverPrivate; 944 const struct intel_image_format *f = intel_image_format_lookup(fourcc); 945 946 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier)) 947 return false; 948 949 switch (attrib) { 950 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT: 951 *value = isl_drm_modifier_has_aux(modifier) ? 2 : f->nplanes; 952 return true; 953 954 default: 955 return false; 956 } 957} 958 959static __DRIimage * 960intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) 961{ 962 __DRIimage *image; 963 964 image = calloc(1, sizeof *image); 965 if (image == NULL) 966 return NULL; 967 968 brw_bo_reference(orig_image->bo); 969 image->bo = orig_image->bo; 970 image->internal_format = orig_image->internal_format; 971 image->planar_format = orig_image->planar_format; 972 image->dri_format = orig_image->dri_format; 973 image->format = orig_image->format; 974 image->modifier = orig_image->modifier; 975 image->offset = orig_image->offset; 976 image->width = orig_image->width; 977 image->height = orig_image->height; 978 image->pitch = orig_image->pitch; 979 image->tile_x = orig_image->tile_x; 980 image->tile_y = orig_image->tile_y; 981 image->has_depthstencil = orig_image->has_depthstencil; 982 image->data = loaderPrivate; 983 image->aux_offset = orig_image->aux_offset; 984 image->aux_pitch = orig_image->aux_pitch; 985 986 memcpy(image->strides, orig_image->strides, sizeof(image->strides)); 987 memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets)); 988 989 return image; 990} 991 992static GLboolean 993intel_validate_usage(__DRIimage *image, unsigned int use) 994{ 995 if (use & __DRI_IMAGE_USE_CURSOR) { 996 if (image->width != 64 || image->height != 64) 997 return GL_FALSE; 998 } 999 1000 return GL_TRUE; 1001} 1002 1003static __DRIimage * 1004intel_create_image_from_names(__DRIscreen *dri_screen, 1005 int width, int height, int fourcc, 1006 int *names, int num_names, 1007 int *strides, int *offsets, 1008 void *loaderPrivate) 1009{ 1010 const struct intel_image_format *f = NULL; 1011 __DRIimage *image; 1012 int i, index; 1013 1014 if (dri_screen == NULL || names == NULL || num_names != 1) 1015 return NULL; 1016 1017 f = intel_image_format_lookup(fourcc); 1018 if (f == NULL) 1019 return NULL; 1020 1021 image = intel_create_image_from_name(dri_screen, width, height, 1022 __DRI_IMAGE_FORMAT_NONE, 1023 names[0], strides[0], 1024 loaderPrivate); 1025 1026 if (image == NULL) 1027 return NULL; 1028 1029 image->planar_format = f; 1030 for (i = 0; i < f->nplanes; i++) { 1031 index = f->planes[i].buffer_index; 1032 image->offsets[index] = offsets[index]; 1033 image->strides[index] = strides[index]; 1034 } 1035 1036 return image; 1037} 1038 1039static __DRIimage * 1040intel_create_image_from_fds_common(__DRIscreen *dri_screen, 1041 int width, int height, int fourcc, 1042 uint64_t modifier, int *fds, int num_fds, 1043 int *strides, int *offsets, 1044 void *loaderPrivate) 1045{ 1046 struct intel_screen *screen = dri_screen->driverPrivate; 1047 const struct intel_image_format *f; 1048 __DRIimage *image; 1049 int i, index; 1050 bool ok; 1051 1052 if (fds == NULL || num_fds < 1) 1053 return NULL; 1054 1055 f = intel_image_format_lookup(fourcc); 1056 if (f == NULL) 1057 return NULL; 1058 1059 if (modifier != DRM_FORMAT_MOD_INVALID && 1060 !modifier_is_supported(&screen->devinfo, f, 0, modifier)) 1061 return NULL; 1062 1063 if (f->nplanes == 1) 1064 image = intel_allocate_image(screen, f->planes[0].dri_format, 1065 loaderPrivate); 1066 else 1067 image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE, 1068 loaderPrivate); 1069 1070 if (image == NULL) 1071 return NULL; 1072 1073 image->width = width; 1074 image->height = height; 1075 image->pitch = strides[0]; 1076 1077 image->planar_format = f; 1078 1079 if (modifier != DRM_FORMAT_MOD_INVALID) { 1080 const struct isl_drm_modifier_info *mod_info = 1081 isl_drm_modifier_get_info(modifier); 1082 uint32_t tiling = isl_tiling_to_i915_tiling(mod_info->tiling); 1083 image->bo = brw_bo_gem_create_from_prime_tiled(screen->bufmgr, fds[0], 1084 tiling, strides[0]); 1085 } else { 1086 image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]); 1087 } 1088 1089 if (image->bo == NULL) { 1090 free(image); 1091 return NULL; 1092 } 1093 1094 /* We only support all planes from the same bo. 1095 * brw_bo_gem_create_from_prime() should return the same pointer for all 1096 * fds received here */ 1097 for (i = 1; i < num_fds; i++) { 1098 struct brw_bo *aux = brw_bo_gem_create_from_prime(screen->bufmgr, fds[i]); 1099 brw_bo_unreference(aux); 1100 if (aux != image->bo) { 1101 brw_bo_unreference(image->bo); 1102 free(image); 1103 return NULL; 1104 } 1105 } 1106 1107 if (modifier != DRM_FORMAT_MOD_INVALID) 1108 image->modifier = modifier; 1109 else 1110 image->modifier = tiling_to_modifier(image->bo->tiling_mode); 1111 1112 const struct isl_drm_modifier_info *mod_info = 1113 isl_drm_modifier_get_info(image->modifier); 1114 1115 int size = 0; 1116 struct isl_surf surf; 1117 for (i = 0; i < f->nplanes; i++) { 1118 index = f->planes[i].buffer_index; 1119 image->offsets[index] = offsets[index]; 1120 image->strides[index] = strides[index]; 1121 1122 mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format); 1123 /* The images we will create are actually based on the RGBA non-sRGB 1124 * version of the format. 1125 */ 1126 format = _mesa_format_fallback_rgbx_to_rgba(format); 1127 format = _mesa_get_srgb_format_linear(format); 1128 1129 ok = isl_surf_init(&screen->isl_dev, &surf, 1130 .dim = ISL_SURF_DIM_2D, 1131 .format = brw_isl_format_for_mesa_format(format), 1132 .width = image->width >> f->planes[i].width_shift, 1133 .height = image->height >> f->planes[i].height_shift, 1134 .depth = 1, 1135 .levels = 1, 1136 .array_len = 1, 1137 .samples = 1, 1138 .row_pitch_B = strides[index], 1139 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT | 1140 ISL_SURF_USAGE_TEXTURE_BIT | 1141 ISL_SURF_USAGE_STORAGE_BIT, 1142 .tiling_flags = (1 << mod_info->tiling)); 1143 if (!ok) { 1144 brw_bo_unreference(image->bo); 1145 free(image); 1146 return NULL; 1147 } 1148 1149 const int end = offsets[index] + surf.size_B; 1150 if (size < end) 1151 size = end; 1152 } 1153 1154 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) { 1155 /* Even though we initialize surf in the loop above, we know that 1156 * anything with CCS_E will have exactly one plane so surf is properly 1157 * initialized when we get here. 1158 */ 1159 assert(f->nplanes == 1); 1160 1161 image->aux_offset = offsets[1]; 1162 image->aux_pitch = strides[1]; 1163 1164 /* Scanout hardware requires that the CCS be placed after the main 1165 * surface in memory. We consider any CCS that is placed any earlier in 1166 * memory to be invalid and reject it. 1167 * 1168 * At some point in the future, this restriction may be relaxed if the 1169 * hardware becomes less strict but we may need a new modifier for that. 1170 */ 1171 assert(size > 0); 1172 if (image->aux_offset < size) { 1173 brw_bo_unreference(image->bo); 1174 free(image); 1175 return NULL; 1176 } 1177 1178 struct isl_surf aux_surf; 1179 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 1180 image->aux_pitch); 1181 if (!ok) { 1182 brw_bo_unreference(image->bo); 1183 free(image); 1184 return NULL; 1185 } 1186 1187 image->aux_size = aux_surf.size_B; 1188 1189 const int end = image->aux_offset + aux_surf.size_B; 1190 if (size < end) 1191 size = end; 1192 } else { 1193 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE); 1194 } 1195 1196 /* Check that the requested image actually fits within the BO. 'size' 1197 * is already relative to the offsets, so we don't need to add that. */ 1198 if (image->bo->size == 0) { 1199 image->bo->size = size; 1200 } else if (size > image->bo->size) { 1201 brw_bo_unreference(image->bo); 1202 free(image); 1203 return NULL; 1204 } 1205 1206 if (f->nplanes == 1) { 1207 image->offset = image->offsets[0]; 1208 intel_image_warn_if_unaligned(image, __func__); 1209 } 1210 1211 return image; 1212} 1213 1214static __DRIimage * 1215intel_create_image_from_fds(__DRIscreen *dri_screen, 1216 int width, int height, int fourcc, 1217 int *fds, int num_fds, int *strides, int *offsets, 1218 void *loaderPrivate) 1219{ 1220 return intel_create_image_from_fds_common(dri_screen, width, height, fourcc, 1221 DRM_FORMAT_MOD_INVALID, 1222 fds, num_fds, strides, offsets, 1223 loaderPrivate); 1224} 1225 1226static __DRIimage * 1227intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen, 1228 int width, int height, 1229 int fourcc, uint64_t modifier, 1230 int *fds, int num_fds, 1231 int *strides, int *offsets, 1232 enum __DRIYUVColorSpace yuv_color_space, 1233 enum __DRISampleRange sample_range, 1234 enum __DRIChromaSiting horizontal_siting, 1235 enum __DRIChromaSiting vertical_siting, 1236 unsigned *error, 1237 void *loaderPrivate) 1238{ 1239 __DRIimage *image; 1240 const struct intel_image_format *f = intel_image_format_lookup(fourcc); 1241 1242 if (!f) { 1243 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 1244 return NULL; 1245 } 1246 1247 image = intel_create_image_from_fds_common(dri_screen, width, height, 1248 fourcc, modifier, 1249 fds, num_fds, strides, offsets, 1250 loaderPrivate); 1251 1252 /* 1253 * Invalid parameters and any inconsistencies between are assumed to be 1254 * checked by the caller. Therefore besides unsupported formats one can fail 1255 * only in allocation. 1256 */ 1257 if (!image) { 1258 *error = __DRI_IMAGE_ERROR_BAD_ALLOC; 1259 return NULL; 1260 } 1261 1262 image->yuv_color_space = yuv_color_space; 1263 image->sample_range = sample_range; 1264 image->horizontal_siting = horizontal_siting; 1265 image->vertical_siting = vertical_siting; 1266 1267 *error = __DRI_IMAGE_ERROR_SUCCESS; 1268 return image; 1269} 1270 1271static __DRIimage * 1272intel_create_image_from_dma_bufs(__DRIscreen *dri_screen, 1273 int width, int height, int fourcc, 1274 int *fds, int num_fds, 1275 int *strides, int *offsets, 1276 enum __DRIYUVColorSpace yuv_color_space, 1277 enum __DRISampleRange sample_range, 1278 enum __DRIChromaSiting horizontal_siting, 1279 enum __DRIChromaSiting vertical_siting, 1280 unsigned *error, 1281 void *loaderPrivate) 1282{ 1283 return intel_create_image_from_dma_bufs2(dri_screen, width, height, 1284 fourcc, DRM_FORMAT_MOD_INVALID, 1285 fds, num_fds, strides, offsets, 1286 yuv_color_space, 1287 sample_range, 1288 horizontal_siting, 1289 vertical_siting, 1290 error, 1291 loaderPrivate); 1292} 1293 1294static bool 1295intel_image_format_is_supported(const struct gen_device_info *devinfo, 1296 const struct intel_image_format *fmt) 1297{ 1298 /* Currently, all formats with an intel_image_format are available on all 1299 * platforms so there's really nothing to check there. 1300 */ 1301 1302#ifndef NDEBUG 1303 if (fmt->nplanes == 1) { 1304 mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format); 1305 /* The images we will create are actually based on the RGBA non-sRGB 1306 * version of the format. 1307 */ 1308 format = _mesa_format_fallback_rgbx_to_rgba(format); 1309 format = _mesa_get_srgb_format_linear(format); 1310 enum isl_format isl_format = brw_isl_format_for_mesa_format(format); 1311 assert(isl_format_supports_rendering(devinfo, isl_format)); 1312 } 1313#endif 1314 1315 return true; 1316} 1317 1318static GLboolean 1319intel_query_dma_buf_formats(__DRIscreen *_screen, int max, 1320 int *formats, int *count) 1321{ 1322 struct intel_screen *screen = _screen->driverPrivate; 1323 int num_formats = 0, i; 1324 1325 for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { 1326 /* These two formats are valid DRI formats but do not exist in 1327 * drm_fourcc.h in the Linux kernel. We don't want to accidentally 1328 * advertise them through the EGL layer. 1329 */ 1330 if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 || 1331 intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888) 1332 continue; 1333 1334 if (!intel_image_format_is_supported(&screen->devinfo, 1335 &intel_image_formats[i])) 1336 continue; 1337 1338 num_formats++; 1339 if (max == 0) 1340 continue; 1341 1342 formats[num_formats - 1] = intel_image_formats[i].fourcc; 1343 if (num_formats >= max) 1344 break; 1345 } 1346 1347 *count = num_formats; 1348 return true; 1349} 1350 1351static GLboolean 1352intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max, 1353 uint64_t *modifiers, 1354 unsigned int *external_only, 1355 int *count) 1356{ 1357 struct intel_screen *screen = _screen->driverPrivate; 1358 const struct intel_image_format *f; 1359 int num_mods = 0, i; 1360 1361 f = intel_image_format_lookup(fourcc); 1362 if (f == NULL) 1363 return false; 1364 1365 if (!intel_image_format_is_supported(&screen->devinfo, f)) 1366 return false; 1367 1368 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) { 1369 uint64_t modifier = supported_modifiers[i].modifier; 1370 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier)) 1371 continue; 1372 1373 num_mods++; 1374 if (max == 0) 1375 continue; 1376 1377 modifiers[num_mods - 1] = modifier; 1378 if (num_mods >= max) 1379 break; 1380 } 1381 1382 if (external_only != NULL) { 1383 for (i = 0; i < num_mods && i < max; i++) { 1384 if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V || 1385 f->components == __DRI_IMAGE_COMPONENTS_Y_UV || 1386 f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV || 1387 f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) { 1388 external_only[i] = GL_TRUE; 1389 } 1390 else { 1391 external_only[i] = GL_FALSE; 1392 } 1393 } 1394 } 1395 1396 *count = num_mods; 1397 return true; 1398} 1399 1400static __DRIimage * 1401intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) 1402{ 1403 int width, height, offset, stride, size, dri_format; 1404 __DRIimage *image; 1405 1406 if (parent == NULL) 1407 return NULL; 1408 1409 width = parent->width; 1410 height = parent->height; 1411 1412 const struct intel_image_format *f = parent->planar_format; 1413 1414 if (f && plane < f->nplanes) { 1415 /* Use the planar format definition. */ 1416 width >>= f->planes[plane].width_shift; 1417 height >>= f->planes[plane].height_shift; 1418 dri_format = f->planes[plane].dri_format; 1419 int index = f->planes[plane].buffer_index; 1420 offset = parent->offsets[index]; 1421 stride = parent->strides[index]; 1422 size = height * stride; 1423 } else if (plane == 0) { 1424 /* The only plane of a non-planar image: copy the parent definition 1425 * directly. */ 1426 dri_format = parent->dri_format; 1427 offset = parent->offset; 1428 stride = parent->pitch; 1429 size = height * stride; 1430 } else if (plane == 1 && parent->modifier != DRM_FORMAT_MOD_INVALID && 1431 isl_drm_modifier_has_aux(parent->modifier)) { 1432 /* Auxiliary plane */ 1433 dri_format = parent->dri_format; 1434 offset = parent->aux_offset; 1435 stride = parent->aux_pitch; 1436 size = parent->aux_size; 1437 } else { 1438 return NULL; 1439 } 1440 1441 if (offset + size > parent->bo->size) { 1442 _mesa_warning(NULL, "intel_from_planar: subimage out of bounds"); 1443 return NULL; 1444 } 1445 1446 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate); 1447 if (image == NULL) 1448 return NULL; 1449 1450 image->bo = parent->bo; 1451 brw_bo_reference(parent->bo); 1452 image->modifier = parent->modifier; 1453 1454 image->width = width; 1455 image->height = height; 1456 image->pitch = stride; 1457 image->offset = offset; 1458 1459 intel_image_warn_if_unaligned(image, __func__); 1460 1461 return image; 1462} 1463 1464static const __DRIimageExtension intelImageExtension = { 1465 .base = { __DRI_IMAGE, 16 }, 1466 1467 .createImageFromName = intel_create_image_from_name, 1468 .createImageFromRenderbuffer = intel_create_image_from_renderbuffer, 1469 .destroyImage = intel_destroy_image, 1470 .createImage = intel_create_image, 1471 .queryImage = intel_query_image, 1472 .dupImage = intel_dup_image, 1473 .validateUsage = intel_validate_usage, 1474 .createImageFromNames = intel_create_image_from_names, 1475 .fromPlanar = intel_from_planar, 1476 .createImageFromTexture = intel_create_image_from_texture, 1477 .createImageFromFds = intel_create_image_from_fds, 1478 .createImageFromDmaBufs = intel_create_image_from_dma_bufs, 1479 .blitImage = NULL, 1480 .getCapabilities = NULL, 1481 .mapImage = intel_map_image, 1482 .unmapImage = intel_unmap_image, 1483 .createImageWithModifiers = intel_create_image_with_modifiers, 1484 .createImageFromDmaBufs2 = intel_create_image_from_dma_bufs2, 1485 .queryDmaBufFormats = intel_query_dma_buf_formats, 1486 .queryDmaBufModifiers = intel_query_dma_buf_modifiers, 1487 .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs, 1488}; 1489 1490static uint64_t 1491get_aperture_size(int fd) 1492{ 1493 struct drm_i915_gem_get_aperture aperture; 1494 1495 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture) != 0) 1496 return 0; 1497 1498 return aperture.aper_size; 1499} 1500 1501static int 1502brw_query_renderer_integer(__DRIscreen *dri_screen, 1503 int param, unsigned int *value) 1504{ 1505 const struct intel_screen *const screen = 1506 (struct intel_screen *) dri_screen->driverPrivate; 1507 1508 switch (param) { 1509 case __DRI2_RENDERER_VENDOR_ID: 1510 value[0] = 0x8086; 1511 return 0; 1512 case __DRI2_RENDERER_DEVICE_ID: 1513 value[0] = screen->deviceID; 1514 return 0; 1515 case __DRI2_RENDERER_ACCELERATED: 1516 value[0] = 1; 1517 return 0; 1518 case __DRI2_RENDERER_VIDEO_MEMORY: { 1519 /* Once a batch uses more than 75% of the maximum mappable size, we 1520 * assume that there's some fragmentation, and we start doing extra 1521 * flushing, etc. That's the big cliff apps will care about. 1522 */ 1523 const unsigned gpu_mappable_megabytes = 1524 screen->aperture_threshold / (1024 * 1024); 1525 1526 const long system_memory_pages = sysconf(_SC_PHYS_PAGES); 1527 const long system_page_size = sysconf(_SC_PAGE_SIZE); 1528 1529 if (system_memory_pages <= 0 || system_page_size <= 0) 1530 return -1; 1531 1532 const uint64_t system_memory_bytes = (uint64_t) system_memory_pages 1533 * (uint64_t) system_page_size; 1534 1535 const unsigned system_memory_megabytes = 1536 (unsigned) (system_memory_bytes / (1024 * 1024)); 1537 1538 value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes); 1539 return 0; 1540 } 1541 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE: 1542 value[0] = 1; 1543 return 0; 1544 case __DRI2_RENDERER_HAS_TEXTURE_3D: 1545 value[0] = 1; 1546 return 0; 1547 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY: 1548 value[0] = 0; 1549 if (brw_hw_context_set_priority(screen->bufmgr, 1550 0, GEN_CONTEXT_HIGH_PRIORITY) == 0) 1551 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH; 1552 if (brw_hw_context_set_priority(screen->bufmgr, 1553 0, GEN_CONTEXT_LOW_PRIORITY) == 0) 1554 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW; 1555 /* reset to default last, just in case */ 1556 if (brw_hw_context_set_priority(screen->bufmgr, 1557 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0) 1558 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM; 1559 return 0; 1560 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB: 1561 value[0] = 1; 1562 return 0; 1563 default: 1564 return driQueryRendererIntegerCommon(dri_screen, param, value); 1565 } 1566 1567 return -1; 1568} 1569 1570static int 1571brw_query_renderer_string(__DRIscreen *dri_screen, 1572 int param, const char **value) 1573{ 1574 const struct intel_screen *screen = 1575 (struct intel_screen *) dri_screen->driverPrivate; 1576 1577 switch (param) { 1578 case __DRI2_RENDERER_VENDOR_ID: 1579 value[0] = brw_vendor_string; 1580 return 0; 1581 case __DRI2_RENDERER_DEVICE_ID: 1582 value[0] = brw_get_renderer_string(screen); 1583 return 0; 1584 default: 1585 break; 1586 } 1587 1588 return -1; 1589} 1590 1591static void 1592brw_set_cache_funcs(__DRIscreen *dri_screen, 1593 __DRIblobCacheSet set, __DRIblobCacheGet get) 1594{ 1595 const struct intel_screen *const screen = 1596 (struct intel_screen *) dri_screen->driverPrivate; 1597 1598 if (!screen->disk_cache) 1599 return; 1600 1601 disk_cache_set_callbacks(screen->disk_cache, set, get); 1602} 1603 1604static const __DRI2rendererQueryExtension intelRendererQueryExtension = { 1605 .base = { __DRI2_RENDERER_QUERY, 1 }, 1606 1607 .queryInteger = brw_query_renderer_integer, 1608 .queryString = brw_query_renderer_string 1609}; 1610 1611static const __DRIrobustnessExtension dri2Robustness = { 1612 .base = { __DRI2_ROBUSTNESS, 1 } 1613}; 1614 1615static const __DRI2blobExtension intelBlobExtension = { 1616 .base = { __DRI2_BLOB, 1 }, 1617 .set_cache_funcs = brw_set_cache_funcs 1618}; 1619 1620static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = { 1621 .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 }, 1622}; 1623 1624static const __DRIextension *screenExtensions[] = { 1625 &intelTexBufferExtension.base, 1626 &intelFenceExtension.base, 1627 &intelFlushExtension.base, 1628 &intelImageExtension.base, 1629 &intelRendererQueryExtension.base, 1630 &intelMutableRenderBufferExtension.base, 1631 &dri2ConfigQueryExtension.base, 1632 &dri2NoErrorExtension.base, 1633 &intelBlobExtension.base, 1634 NULL 1635}; 1636 1637static const __DRIextension *intelRobustScreenExtensions[] = { 1638 &intelTexBufferExtension.base, 1639 &intelFenceExtension.base, 1640 &intelFlushExtension.base, 1641 &intelImageExtension.base, 1642 &intelRendererQueryExtension.base, 1643 &intelMutableRenderBufferExtension.base, 1644 &dri2ConfigQueryExtension.base, 1645 &dri2Robustness.base, 1646 &dri2NoErrorExtension.base, 1647 &intelBlobExtension.base, 1648 NULL 1649}; 1650 1651static int 1652intel_get_param(struct intel_screen *screen, int param, int *value) 1653{ 1654 int ret = 0; 1655 struct drm_i915_getparam gp; 1656 1657 memset(&gp, 0, sizeof(gp)); 1658 gp.param = param; 1659 gp.value = value; 1660 1661 if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { 1662 ret = -errno; 1663 if (ret != -EINVAL) 1664 _mesa_warning(NULL, "drm_i915_getparam: %d", ret); 1665 } 1666 1667 return ret; 1668} 1669 1670static bool 1671intel_get_boolean(struct intel_screen *screen, int param) 1672{ 1673 int value = 0; 1674 return (intel_get_param(screen, param, &value) == 0) && value; 1675} 1676 1677static int 1678intel_get_integer(struct intel_screen *screen, int param) 1679{ 1680 int value = -1; 1681 1682 if (intel_get_param(screen, param, &value) == 0) 1683 return value; 1684 1685 return -1; 1686} 1687 1688static void 1689intelDestroyScreen(__DRIscreen * sPriv) 1690{ 1691 struct intel_screen *screen = sPriv->driverPrivate; 1692 1693 brw_bufmgr_destroy(screen->bufmgr); 1694 driDestroyOptionInfo(&screen->optionCache); 1695 1696 disk_cache_destroy(screen->disk_cache); 1697 1698 ralloc_free(screen); 1699 sPriv->driverPrivate = NULL; 1700} 1701 1702 1703/** 1704 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate. 1705 * 1706 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls 1707 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name, 1708 * this does not allocate GPU memory. 1709 */ 1710static GLboolean 1711intelCreateBuffer(__DRIscreen *dri_screen, 1712 __DRIdrawable * driDrawPriv, 1713 const struct gl_config * mesaVis, GLboolean isPixmap) 1714{ 1715 struct intel_renderbuffer *rb; 1716 struct intel_screen *screen = (struct intel_screen *) 1717 dri_screen->driverPrivate; 1718 mesa_format rgbFormat; 1719 unsigned num_samples = 1720 intel_quantize_num_samples(screen, mesaVis->samples); 1721 1722 if (isPixmap) 1723 return false; 1724 1725 struct gl_framebuffer *fb = CALLOC_STRUCT(gl_framebuffer); 1726 if (!fb) 1727 return false; 1728 1729 _mesa_initialize_window_framebuffer(fb, mesaVis); 1730 1731 if (screen->winsys_msaa_samples_override != -1) { 1732 num_samples = screen->winsys_msaa_samples_override; 1733 fb->Visual.samples = num_samples; 1734 } 1735 1736 if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { 1737 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM 1738 : MESA_FORMAT_R10G10B10A2_UNORM; 1739 } else if (mesaVis->redBits == 10) { 1740 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM 1741 : MESA_FORMAT_R10G10B10X2_UNORM; 1742 } else if (mesaVis->redBits == 5) { 1743 rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM 1744 : MESA_FORMAT_B5G6R5_UNORM; 1745 } else if (mesaVis->sRGBCapable) { 1746 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB 1747 : MESA_FORMAT_B8G8R8A8_SRGB; 1748 } else if (mesaVis->alphaBits == 0) { 1749 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM 1750 : MESA_FORMAT_B8G8R8X8_UNORM; 1751 } else { 1752 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB 1753 : MESA_FORMAT_B8G8R8A8_SRGB; 1754 fb->Visual.sRGBCapable = true; 1755 } 1756 1757 /* mesaVis->sRGBCapable was set, user is asking for sRGB */ 1758 bool srgb_cap_set = mesaVis->redBits >= 8 && mesaVis->sRGBCapable; 1759 1760 /* setup the hardware-based renderbuffers */ 1761 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples); 1762 _mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base); 1763 rb->need_srgb = srgb_cap_set; 1764 1765 if (mesaVis->doubleBufferMode) { 1766 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples); 1767 _mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base); 1768 rb->need_srgb = srgb_cap_set; 1769 } 1770 1771 /* 1772 * Assert here that the gl_config has an expected depth/stencil bit 1773 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(), 1774 * which constructs the advertised configs.) 1775 */ 1776 if (mesaVis->depthBits == 24) { 1777 assert(mesaVis->stencilBits == 8); 1778 1779 if (screen->devinfo.has_hiz_and_separate_stencil) { 1780 rb = intel_create_private_renderbuffer(screen, 1781 MESA_FORMAT_Z24_UNORM_X8_UINT, 1782 num_samples); 1783 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base); 1784 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_S_UINT8, 1785 num_samples); 1786 _mesa_attach_and_own_rb(fb, BUFFER_STENCIL, &rb->Base.Base); 1787 } else { 1788 /* 1789 * Use combined depth/stencil. Note that the renderbuffer is 1790 * attached to two attachment points. 1791 */ 1792 rb = intel_create_private_renderbuffer(screen, 1793 MESA_FORMAT_Z24_UNORM_S8_UINT, 1794 num_samples); 1795 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base); 1796 _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base); 1797 } 1798 } 1799 else if (mesaVis->depthBits == 16) { 1800 assert(mesaVis->stencilBits == 0); 1801 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_Z_UNORM16, 1802 num_samples); 1803 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base); 1804 } 1805 else { 1806 assert(mesaVis->depthBits == 0); 1807 assert(mesaVis->stencilBits == 0); 1808 } 1809 1810 /* now add any/all software-based renderbuffers we may need */ 1811 _swrast_add_soft_renderbuffers(fb, 1812 false, /* never sw color */ 1813 false, /* never sw depth */ 1814 false, /* never sw stencil */ 1815 mesaVis->accumRedBits > 0, 1816 false, /* never sw alpha */ 1817 false /* never sw aux */ ); 1818 driDrawPriv->driverPrivate = fb; 1819 1820 return true; 1821} 1822 1823static void 1824intelDestroyBuffer(__DRIdrawable * driDrawPriv) 1825{ 1826 struct gl_framebuffer *fb = driDrawPriv->driverPrivate; 1827 1828 _mesa_reference_framebuffer(&fb, NULL); 1829} 1830 1831static void 1832intel_cs_timestamp_frequency(struct intel_screen *screen) 1833{ 1834 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to 1835 * gen10, PCI-id is enough to figure it out. 1836 */ 1837 assert(screen->devinfo.gen >= 10); 1838 1839 int ret, freq; 1840 1841 ret = intel_get_param(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY, 1842 &freq); 1843 if (ret < 0) { 1844 _mesa_warning(NULL, 1845 "Kernel 4.15 required to read the CS timestamp frequency.\n"); 1846 return; 1847 } 1848 1849 screen->devinfo.timestamp_frequency = freq; 1850} 1851 1852static void 1853intel_detect_sseu(struct intel_screen *screen) 1854{ 1855 assert(screen->devinfo.gen >= 8); 1856 int ret; 1857 1858 screen->subslice_total = -1; 1859 screen->eu_total = -1; 1860 1861 ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL, 1862 &screen->subslice_total); 1863 if (ret < 0 && ret != -EINVAL) 1864 goto err_out; 1865 1866 ret = intel_get_param(screen, 1867 I915_PARAM_EU_TOTAL, &screen->eu_total); 1868 if (ret < 0 && ret != -EINVAL) 1869 goto err_out; 1870 1871 /* Without this information, we cannot get the right Braswell brandstrings, 1872 * and we have to use conservative numbers for GPGPU on many platforms, but 1873 * otherwise, things will just work. 1874 */ 1875 if (screen->subslice_total < 1 || screen->eu_total < 1) 1876 _mesa_warning(NULL, 1877 "Kernel 4.1 required to properly query GPU properties.\n"); 1878 1879 return; 1880 1881err_out: 1882 screen->subslice_total = -1; 1883 screen->eu_total = -1; 1884 _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret)); 1885} 1886 1887static bool 1888intel_init_bufmgr(struct intel_screen *screen) 1889{ 1890 __DRIscreen *dri_screen = screen->driScrnPriv; 1891 1892 if (getenv("INTEL_NO_HW") != NULL) 1893 screen->no_hw = true; 1894 1895 screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd); 1896 if (screen->bufmgr == NULL) { 1897 fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", 1898 __func__, __LINE__); 1899 return false; 1900 } 1901 1902 if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) { 1903 fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__); 1904 return false; 1905 } 1906 1907 return true; 1908} 1909 1910static bool 1911intel_detect_swizzling(struct intel_screen *screen) 1912{ 1913 /* Broadwell PRM says: 1914 * 1915 * "Before Gen8, there was a historical configuration control field to 1916 * swizzle address bit[6] for in X/Y tiling modes. This was set in three 1917 * different places: TILECTL[1:0], ARB_MODE[5:4], and 1918 * DISP_ARB_CTL[14:13]. 1919 * 1920 * For Gen8 and subsequent generations, the swizzle fields are all 1921 * reserved, and the CPU's memory controller performs all address 1922 * swizzling modifications." 1923 */ 1924 if (screen->devinfo.gen >= 8) 1925 return false; 1926 1927 uint32_t tiling = I915_TILING_X; 1928 uint32_t swizzle_mode = 0; 1929 struct brw_bo *buffer = 1930 brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768, 1931 BRW_MEMZONE_OTHER, tiling, 512, 0); 1932 if (buffer == NULL) 1933 return false; 1934 1935 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode); 1936 brw_bo_unreference(buffer); 1937 1938 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE; 1939} 1940 1941static int 1942intel_detect_timestamp(struct intel_screen *screen) 1943{ 1944 uint64_t dummy = 0, last = 0; 1945 int upper, lower, loops; 1946 1947 /* On 64bit systems, some old kernels trigger a hw bug resulting in the 1948 * TIMESTAMP register being shifted and the low 32bits always zero. 1949 * 1950 * More recent kernels offer an interface to read the full 36bits 1951 * everywhere. 1952 */ 1953 if (brw_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0) 1954 return 3; 1955 1956 /* Determine if we have a 32bit or 64bit kernel by inspecting the 1957 * upper 32bits for a rapidly changing timestamp. 1958 */ 1959 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &last)) 1960 return 0; 1961 1962 upper = lower = 0; 1963 for (loops = 0; loops < 10; loops++) { 1964 /* The TIMESTAMP should change every 80ns, so several round trips 1965 * through the kernel should be enough to advance it. 1966 */ 1967 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) 1968 return 0; 1969 1970 upper += (dummy >> 32) != (last >> 32); 1971 if (upper > 1) /* beware 32bit counter overflow */ 1972 return 2; /* upper dword holds the low 32bits of the timestamp */ 1973 1974 lower += (dummy & 0xffffffff) != (last & 0xffffffff); 1975 if (lower > 1) 1976 return 1; /* timestamp is unshifted */ 1977 1978 last = dummy; 1979 } 1980 1981 /* No advancement? No timestamp! */ 1982 return 0; 1983} 1984 1985 /** 1986 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer. 1987 * 1988 * Some combinations of hardware and kernel versions allow this feature, 1989 * while others don't. Instead of trying to enumerate every case, just 1990 * try and write a register and see if works. 1991 */ 1992static bool 1993intel_detect_pipelined_register(struct intel_screen *screen, 1994 int reg, uint32_t expected_value, bool reset) 1995{ 1996 if (screen->no_hw) 1997 return false; 1998 1999 struct brw_bo *results, *bo; 2000 uint32_t *batch; 2001 uint32_t offset = 0; 2002 void *map; 2003 bool success = false; 2004 2005 /* Create a zero'ed temporary buffer for reading our results */ 2006 results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER); 2007 if (results == NULL) 2008 goto err; 2009 2010 bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER); 2011 if (bo == NULL) 2012 goto err_results; 2013 2014 map = brw_bo_map(NULL, bo, MAP_WRITE); 2015 if (!map) 2016 goto err_batch; 2017 2018 batch = map; 2019 2020 /* Write the register. */ 2021 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2); 2022 *batch++ = reg; 2023 *batch++ = expected_value; 2024 2025 /* Save the register's value back to the buffer. */ 2026 *batch++ = MI_STORE_REGISTER_MEM | (3 - 2); 2027 *batch++ = reg; 2028 struct drm_i915_gem_relocation_entry reloc = { 2029 .offset = (char *) batch - (char *) map, 2030 .delta = offset * sizeof(uint32_t), 2031 .target_handle = results->gem_handle, 2032 .read_domains = I915_GEM_DOMAIN_INSTRUCTION, 2033 .write_domain = I915_GEM_DOMAIN_INSTRUCTION, 2034 }; 2035 *batch++ = reloc.presumed_offset + reloc.delta; 2036 2037 /* And afterwards clear the register */ 2038 if (reset) { 2039 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2); 2040 *batch++ = reg; 2041 *batch++ = 0; 2042 } 2043 2044 *batch++ = MI_BATCH_BUFFER_END; 2045 2046 struct drm_i915_gem_exec_object2 exec_objects[2] = { 2047 { 2048 .handle = results->gem_handle, 2049 }, 2050 { 2051 .handle = bo->gem_handle, 2052 .relocation_count = 1, 2053 .relocs_ptr = (uintptr_t) &reloc, 2054 } 2055 }; 2056 2057 struct drm_i915_gem_execbuffer2 execbuf = { 2058 .buffers_ptr = (uintptr_t) exec_objects, 2059 .buffer_count = 2, 2060 .batch_len = ALIGN((char *) batch - (char *) map, 8), 2061 .flags = I915_EXEC_RENDER, 2062 }; 2063 2064 /* Don't bother with error checking - if the execbuf fails, the 2065 * value won't be written and we'll just report that there's no access. 2066 */ 2067 __DRIscreen *dri_screen = screen->driScrnPriv; 2068 drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); 2069 2070 /* Check whether the value got written. */ 2071 void *results_map = brw_bo_map(NULL, results, MAP_READ); 2072 if (results_map) { 2073 success = *((uint32_t *)results_map + offset) == expected_value; 2074 brw_bo_unmap(results); 2075 } 2076 2077err_batch: 2078 brw_bo_unreference(bo); 2079err_results: 2080 brw_bo_unreference(results); 2081err: 2082 return success; 2083} 2084 2085static bool 2086intel_detect_pipelined_so(struct intel_screen *screen) 2087{ 2088 const struct gen_device_info *devinfo = &screen->devinfo; 2089 2090 /* Supposedly, Broadwell just works. */ 2091 if (devinfo->gen >= 8) 2092 return true; 2093 2094 if (devinfo->gen <= 6) 2095 return false; 2096 2097 /* See the big explanation about command parser versions below */ 2098 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2)) 2099 return true; 2100 2101 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the 2102 * statistics registers), and we already reset it to zero before using it. 2103 */ 2104 return intel_detect_pipelined_register(screen, 2105 GEN7_SO_WRITE_OFFSET(0), 2106 0x1337d0d0, 2107 false); 2108} 2109 2110/** 2111 * Return array of MSAA modes supported by the hardware. The array is 2112 * zero-terminated and sorted in decreasing order. 2113 */ 2114const int* 2115intel_supported_msaa_modes(const struct intel_screen *screen) 2116{ 2117 static const int gen9_modes[] = {16, 8, 4, 2, 0, -1}; 2118 static const int gen8_modes[] = {8, 4, 2, 0, -1}; 2119 static const int gen7_modes[] = {8, 4, 0, -1}; 2120 static const int gen6_modes[] = {4, 0, -1}; 2121 static const int gen4_modes[] = {0, -1}; 2122 2123 if (screen->devinfo.gen >= 9) { 2124 return gen9_modes; 2125 } else if (screen->devinfo.gen >= 8) { 2126 return gen8_modes; 2127 } else if (screen->devinfo.gen >= 7) { 2128 return gen7_modes; 2129 } else if (screen->devinfo.gen == 6) { 2130 return gen6_modes; 2131 } else { 2132 return gen4_modes; 2133 } 2134} 2135 2136static unsigned 2137intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap) 2138{ 2139 if (dri_screen->dri2.loader && dri_screen->dri2.loader->base.version >= 4 && 2140 dri_screen->dri2.loader->getCapability) 2141 return dri_screen->dri2.loader->getCapability(dri_screen->loaderPrivate, cap); 2142 2143 if (dri_screen->image.loader && dri_screen->image.loader->base.version >= 2 && 2144 dri_screen->image.loader->getCapability) 2145 return dri_screen->image.loader->getCapability(dri_screen->loaderPrivate, cap); 2146 2147 return 0; 2148} 2149 2150static __DRIconfig** 2151intel_screen_make_configs(__DRIscreen *dri_screen) 2152{ 2153 static const mesa_format formats[] = { 2154 MESA_FORMAT_B5G6R5_UNORM, 2155 MESA_FORMAT_B8G8R8A8_UNORM, 2156 MESA_FORMAT_B8G8R8X8_UNORM, 2157 2158 MESA_FORMAT_B8G8R8A8_SRGB, 2159 2160 /* For 10 bpc, 30 bit depth framebuffers. */ 2161 MESA_FORMAT_B10G10R10A2_UNORM, 2162 MESA_FORMAT_B10G10R10X2_UNORM, 2163 2164 /* The 32-bit RGBA format must not precede the 32-bit BGRA format. 2165 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX 2166 * server may disagree on which format the GLXFBConfig represents, 2167 * resulting in swapped color channels. 2168 * 2169 * The problem, as of 2017-05-30: 2170 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel 2171 * order and chooses the first __DRIconfig with the expected channel 2172 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's 2173 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK. 2174 * 2175 * EGL does not suffer from this problem. It correctly compares the 2176 * channel masks when matching EGLConfig to __DRIconfig. 2177 */ 2178 2179 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */ 2180 MESA_FORMAT_R8G8B8A8_UNORM, 2181 2182 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */ 2183 MESA_FORMAT_R8G8B8X8_UNORM, 2184 2185 MESA_FORMAT_R8G8B8A8_SRGB, 2186 }; 2187 2188 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */ 2189 static const GLenum back_buffer_modes[] = { 2190 __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE 2191 }; 2192 2193 static const uint8_t singlesample_samples[1] = {0}; 2194 2195 struct intel_screen *screen = dri_screen->driverPrivate; 2196 const struct gen_device_info *devinfo = &screen->devinfo; 2197 uint8_t depth_bits[4], stencil_bits[4]; 2198 __DRIconfig **configs = NULL; 2199 2200 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ 2201 unsigned num_formats; 2202 if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) 2203 num_formats = ARRAY_SIZE(formats); 2204 else 2205 num_formats = ARRAY_SIZE(formats) - 3; /* all - RGBA_ORDERING formats */ 2206 2207 /* Shall we expose 10 bpc formats? */ 2208 bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, 2209 "allow_rgb10_configs"); 2210 /* Shall we expose 565 formats? */ 2211 bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache, 2212 "allow_rgb565_configs"); 2213 2214 /* Generate singlesample configs, each without accumulation buffer 2215 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. 2216 */ 2217 for (unsigned i = 0; i < num_formats; i++) { 2218 __DRIconfig **new_configs; 2219 int num_depth_stencil_bits = 2; 2220 2221 if (!allow_rgb10_configs && 2222 (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || 2223 formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) 2224 continue; 2225 2226 if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) 2227 continue; 2228 2229 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil 2230 * buffer that has a different number of bits per pixel than the color 2231 * buffer, gen >= 6 supports this. 2232 */ 2233 depth_bits[0] = 0; 2234 stencil_bits[0] = 0; 2235 2236 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 2237 depth_bits[1] = 16; 2238 stencil_bits[1] = 0; 2239 if (devinfo->gen >= 6) { 2240 depth_bits[2] = 24; 2241 stencil_bits[2] = 8; 2242 num_depth_stencil_bits = 3; 2243 } 2244 } else { 2245 depth_bits[1] = 24; 2246 stencil_bits[1] = 8; 2247 } 2248 2249 new_configs = driCreateConfigs(formats[i], 2250 depth_bits, 2251 stencil_bits, 2252 num_depth_stencil_bits, 2253 back_buffer_modes, 2, 2254 singlesample_samples, 1, 2255 false, false, 2256 /*mutable_render_buffer*/ true); 2257 configs = driConcatConfigs(configs, new_configs); 2258 } 2259 2260 /* Generate the minimum possible set of configs that include an 2261 * accumulation buffer. 2262 */ 2263 for (unsigned i = 0; i < num_formats; i++) { 2264 __DRIconfig **new_configs; 2265 2266 if (!allow_rgb10_configs && 2267 (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || 2268 formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) 2269 continue; 2270 2271 if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) 2272 continue; 2273 2274 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 2275 depth_bits[0] = 16; 2276 stencil_bits[0] = 0; 2277 } else { 2278 depth_bits[0] = 24; 2279 stencil_bits[0] = 8; 2280 } 2281 2282 new_configs = driCreateConfigs(formats[i], 2283 depth_bits, stencil_bits, 1, 2284 back_buffer_modes, 1, 2285 singlesample_samples, 1, 2286 true, false, false); 2287 configs = driConcatConfigs(configs, new_configs); 2288 } 2289 2290 /* Generate multisample configs. 2291 * 2292 * This loop breaks early, and hence is a no-op, on gen < 6. 2293 * 2294 * Multisample configs must follow the singlesample configs in order to 2295 * work around an X server bug present in 1.12. The X server chooses to 2296 * associate the first listed RGBA888-Z24S8 config, regardless of its 2297 * sample count, with the 32-bit depth visual used for compositing. 2298 * 2299 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are 2300 * supported. Singlebuffer configs are not supported because no one wants 2301 * them. 2302 */ 2303 for (unsigned i = 0; i < num_formats; i++) { 2304 if (devinfo->gen < 6) 2305 break; 2306 2307 if (!allow_rgb10_configs && 2308 (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || 2309 formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) 2310 continue; 2311 2312 if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM) 2313 continue; 2314 2315 __DRIconfig **new_configs; 2316 const int num_depth_stencil_bits = 2; 2317 int num_msaa_modes = 0; 2318 const uint8_t *multisample_samples = NULL; 2319 2320 depth_bits[0] = 0; 2321 stencil_bits[0] = 0; 2322 2323 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 2324 depth_bits[1] = 16; 2325 stencil_bits[1] = 0; 2326 } else { 2327 depth_bits[1] = 24; 2328 stencil_bits[1] = 8; 2329 } 2330 2331 if (devinfo->gen >= 9) { 2332 static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16}; 2333 multisample_samples = multisample_samples_gen9; 2334 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9); 2335 } else if (devinfo->gen == 8) { 2336 static const uint8_t multisample_samples_gen8[] = {2, 4, 8}; 2337 multisample_samples = multisample_samples_gen8; 2338 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8); 2339 } else if (devinfo->gen == 7) { 2340 static const uint8_t multisample_samples_gen7[] = {4, 8}; 2341 multisample_samples = multisample_samples_gen7; 2342 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7); 2343 } else if (devinfo->gen == 6) { 2344 static const uint8_t multisample_samples_gen6[] = {4}; 2345 multisample_samples = multisample_samples_gen6; 2346 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6); 2347 } 2348 2349 new_configs = driCreateConfigs(formats[i], 2350 depth_bits, 2351 stencil_bits, 2352 num_depth_stencil_bits, 2353 back_buffer_modes, 1, 2354 multisample_samples, 2355 num_msaa_modes, 2356 false, false, false); 2357 configs = driConcatConfigs(configs, new_configs); 2358 } 2359 2360 if (configs == NULL) { 2361 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 2362 __LINE__); 2363 return NULL; 2364 } 2365 2366 return configs; 2367} 2368 2369static void 2370set_max_gl_versions(struct intel_screen *screen) 2371{ 2372 __DRIscreen *dri_screen = screen->driScrnPriv; 2373 const bool has_astc = screen->devinfo.gen >= 9; 2374 2375 switch (screen->devinfo.gen) { 2376 case 11: 2377 case 10: 2378 case 9: 2379 case 8: 2380 dri_screen->max_gl_core_version = 45; 2381 dri_screen->max_gl_compat_version = 30; 2382 dri_screen->max_gl_es1_version = 11; 2383 dri_screen->max_gl_es2_version = has_astc ? 32 : 31; 2384 break; 2385 case 7: 2386 dri_screen->max_gl_core_version = 33; 2387 if (can_do_pipelined_register_writes(screen)) { 2388 dri_screen->max_gl_core_version = 42; 2389 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen)) 2390 dri_screen->max_gl_core_version = 43; 2391 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen)) 2392 dri_screen->max_gl_core_version = 45; 2393 } 2394 dri_screen->max_gl_compat_version = 30; 2395 dri_screen->max_gl_es1_version = 11; 2396 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; 2397 break; 2398 case 6: 2399 dri_screen->max_gl_core_version = 33; 2400 dri_screen->max_gl_compat_version = 30; 2401 dri_screen->max_gl_es1_version = 11; 2402 dri_screen->max_gl_es2_version = 30; 2403 break; 2404 case 5: 2405 case 4: 2406 dri_screen->max_gl_core_version = 0; 2407 dri_screen->max_gl_compat_version = 21; 2408 dri_screen->max_gl_es1_version = 11; 2409 dri_screen->max_gl_es2_version = 20; 2410 break; 2411 default: 2412 unreachable("unrecognized intel_screen::gen"); 2413 } 2414} 2415 2416/** 2417 * Return the revision (generally the revid field of the PCI header) of the 2418 * graphics device. 2419 */ 2420static int 2421intel_device_get_revision(int fd) 2422{ 2423 struct drm_i915_getparam gp; 2424 int revision; 2425 int ret; 2426 2427 memset(&gp, 0, sizeof(gp)); 2428 gp.param = I915_PARAM_REVISION; 2429 gp.value = &revision; 2430 2431 ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); 2432 if (ret) 2433 revision = -1; 2434 2435 return revision; 2436} 2437 2438static void 2439shader_debug_log_mesa(void *data, const char *fmt, ...) 2440{ 2441 struct brw_context *brw = (struct brw_context *)data; 2442 va_list args; 2443 2444 va_start(args, fmt); 2445 GLuint msg_id = 0; 2446 _mesa_gl_vdebugf(&brw->ctx, &msg_id, 2447 MESA_DEBUG_SOURCE_SHADER_COMPILER, 2448 MESA_DEBUG_TYPE_OTHER, 2449 MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); 2450 va_end(args); 2451} 2452 2453static void 2454shader_perf_log_mesa(void *data, const char *fmt, ...) 2455{ 2456 struct brw_context *brw = (struct brw_context *)data; 2457 2458 va_list args; 2459 va_start(args, fmt); 2460 2461 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { 2462 va_list args_copy; 2463 va_copy(args_copy, args); 2464 vfprintf(stderr, fmt, args_copy); 2465 va_end(args_copy); 2466 } 2467 2468 if (brw->perf_debug) { 2469 GLuint msg_id = 0; 2470 _mesa_gl_vdebugf(&brw->ctx, &msg_id, 2471 MESA_DEBUG_SOURCE_SHADER_COMPILER, 2472 MESA_DEBUG_TYPE_PERFORMANCE, 2473 MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); 2474 } 2475 va_end(args); 2476} 2477 2478/** 2479 * This is the driver specific part of the createNewScreen entry point. 2480 * Called when using DRI2. 2481 * 2482 * \return the struct gl_config supported by this driver 2483 */ 2484static const 2485__DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) 2486{ 2487 struct intel_screen *screen; 2488 2489 if (dri_screen->image.loader) { 2490 } else if (dri_screen->dri2.loader->base.version <= 2 || 2491 dri_screen->dri2.loader->getBuffersWithFormat == NULL) { 2492 fprintf(stderr, 2493 "\nERROR! DRI2 loader with getBuffersWithFormat() " 2494 "support required\n"); 2495 return NULL; 2496 } 2497 2498 /* Allocate the private area */ 2499 screen = rzalloc(NULL, struct intel_screen); 2500 if (!screen) { 2501 fprintf(stderr, "\nERROR! Allocating private area failed\n"); 2502 return NULL; 2503 } 2504 /* parse information in __driConfigOptions */ 2505 driOptionCache options; 2506 memset(&options, 0, sizeof(options)); 2507 2508 driParseOptionInfo(&options, brw_config_options.xml); 2509 driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, 2510 "i965", NULL); 2511 driDestroyOptionCache(&options); 2512 2513 screen->driScrnPriv = dri_screen; 2514 dri_screen->driverPrivate = (void *) screen; 2515 2516 screen->deviceID = gen_get_pci_device_id_override(); 2517 if (screen->deviceID < 0) 2518 screen->deviceID = intel_get_integer(screen, I915_PARAM_CHIPSET_ID); 2519 else 2520 screen->no_hw = true; 2521 2522 if (!gen_get_device_info(screen->deviceID, &screen->devinfo)) 2523 return NULL; 2524 2525 screen->devinfo.revision = intel_device_get_revision(dri_screen->fd); 2526 2527 if (!intel_init_bufmgr(screen)) 2528 return NULL; 2529 2530 const struct gen_device_info *devinfo = &screen->devinfo; 2531 2532 brw_process_intel_debug_variable(); 2533 2534 if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) { 2535 fprintf(stderr, 2536 "shader_time debugging requires gen7 (Ivybridge) or better.\n"); 2537 INTEL_DEBUG &= ~DEBUG_SHADER_TIME; 2538 } 2539 2540 if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) { 2541 /* Theorectically unlimited! At least for individual objects... 2542 * 2543 * Currently the entire (global) address space for all GTT maps is 2544 * limited to 64bits. That is all objects on the system that are 2545 * setup for GTT mmapping must fit within 64bits. An attempt to use 2546 * one that exceeds the limit with fail in brw_bo_map_gtt(). 2547 * 2548 * Long before we hit that limit, we will be practically limited by 2549 * that any single object must fit in physical memory (RAM). The upper 2550 * limit on the CPU's address space is currently 48bits (Skylake), of 2551 * which only 39bits can be physical memory. (The GPU itself also has 2552 * a 48bit addressable virtual space.) We can fit over 32 million 2553 * objects of the current maximum allocable size before running out 2554 * of mmap space. 2555 */ 2556 screen->max_gtt_map_object_size = UINT64_MAX; 2557 } else { 2558 /* Estimate the size of the mappable aperture into the GTT. There's an 2559 * ioctl to get the whole GTT size, but not one to get the mappable subset. 2560 * It turns out it's basically always 256MB, though some ancient hardware 2561 * was smaller. 2562 */ 2563 uint32_t gtt_size = 256 * 1024 * 1024; 2564 2565 /* We don't want to map two objects such that a memcpy between them would 2566 * just fault one mapping in and then the other over and over forever. So 2567 * we would need to divide the GTT size by 2. Additionally, some GTT is 2568 * taken up by things like the framebuffer and the ringbuffer and such, so 2569 * be more conservative. 2570 */ 2571 screen->max_gtt_map_object_size = gtt_size / 4; 2572 } 2573 2574 screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4; 2575 2576 screen->hw_has_swizzling = intel_detect_swizzling(screen); 2577 screen->hw_has_timestamp = intel_detect_timestamp(screen); 2578 2579 isl_device_init(&screen->isl_dev, &screen->devinfo, 2580 screen->hw_has_swizzling); 2581 2582 if (devinfo->gen >= 10) 2583 intel_cs_timestamp_frequency(screen); 2584 2585 /* GENs prior to 8 do not support EU/Subslice info */ 2586 if (devinfo->gen >= 8) { 2587 intel_detect_sseu(screen); 2588 } else if (devinfo->gen == 7) { 2589 screen->subslice_total = 1 << (devinfo->gt - 1); 2590 } 2591 2592 /* Gen7-7.5 kernel requirements / command parser saga: 2593 * 2594 * - pre-v3.16: 2595 * Haswell and Baytrail cannot use any privileged batchbuffer features. 2596 * 2597 * Ivybridge has aliasing PPGTT on by default, which accidentally marks 2598 * all batches secure, allowing them to use any feature with no checking. 2599 * This is effectively equivalent to a command parser version of 2600 * \infinity - everything is possible. 2601 * 2602 * The command parser does not exist, and querying the version will 2603 * return -EINVAL. 2604 * 2605 * - v3.16: 2606 * The kernel enables the command parser by default, for systems with 2607 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the 2608 * hardware checker is still enabled, so Haswell and Baytrail cannot 2609 * do anything. 2610 * 2611 * Ivybridge goes from "everything is possible" to "only what the 2612 * command parser allows" (if the user boots with i915.cmd_parser=0, 2613 * then everything is possible again). We can only safely use features 2614 * allowed by the supported command parser version. 2615 * 2616 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version 2617 * implemented by the kernel, even if it's turned off. So, checking 2618 * for version > 0 does not mean that you can write registers. We have 2619 * to try it and see. The version does, however, indicate the age of 2620 * the kernel. 2621 * 2622 * Instead of matching the hardware checker's behavior of converting 2623 * privileged commands to MI_NOOP, it makes execbuf2 start returning 2624 * -EINVAL, making it dangerous to try and use privileged features. 2625 * 2626 * Effective command parser versions: 2627 * - Haswell: 0 (reporting 1, writes don't work) 2628 * - Baytrail: 0 (reporting 1, writes don't work) 2629 * - Ivybridge: 1 (enabled) or infinite (disabled) 2630 * 2631 * - v3.17: 2632 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge: 2633 * effectively version 1 (enabled) or infinite (disabled). 2634 * 2635 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b 2636 * Command parser v2 supports predicate writes. 2637 * 2638 * - Haswell: 0 (reporting 1, writes don't work) 2639 * - Baytrail: 2 (enabled) or infinite (disabled) 2640 * - Ivybridge: 2 (enabled) or infinite (disabled) 2641 * 2642 * So version >= 2 is enough to know that Ivybridge and Baytrail 2643 * will work. Haswell still can't do anything. 2644 * 2645 * - v4.0: Version 3 happened. Largely not relevant. 2646 * 2647 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b 2648 * L3 config registers are properly saved and restored as part 2649 * of the hardware context. We can approximately detect this point 2650 * in time by checking if I915_PARAM_REVISION is recognized - it 2651 * landed in a later commit, but in the same release cycle. 2652 * 2653 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284 2654 * Command parser finally gains secure batch promotion. On Haswell, 2655 * the hardware checker gets disabled, which finally allows it to do 2656 * privileged commands. 2657 * 2658 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions: 2659 * - Haswell: 3 (enabled) or 0 (disabled) 2660 * - Baytrail: 3 (enabled) or infinite (disabled) 2661 * - Ivybridge: 3 (enabled) or infinite (disabled) 2662 * 2663 * Unfortunately, detecting this point in time is tricky, because 2664 * no version bump happened when this important change occurred. 2665 * On Haswell, if we can write any register, then the kernel is at 2666 * least this new, and we can start trusting the version number. 2667 * 2668 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and 2669 * Command parser reaches version 4, allowing access to Haswell 2670 * atomic scratch and chicken3 registers. If version >= 4, we know 2671 * the kernel is new enough to support privileged features on all 2672 * hardware. However, the user might have disabled it...and the 2673 * kernel will still report version 4. So we still have to guess 2674 * and check. 2675 * 2676 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8 2677 * Command parser v5 whitelists indirect compute shader dispatch 2678 * registers, needed for OpenGL 4.3 and later. 2679 * 2680 * - v4.8: 2681 * Command parser v7 lets us use MI_MATH on Haswell. 2682 * 2683 * Additionally, the kernel begins reporting version 0 when 2684 * the command parser is disabled, allowing us to skip the 2685 * guess-and-check step on Haswell. Unfortunately, this also 2686 * means that we can no longer use it as an indicator of the 2687 * age of the kernel. 2688 */ 2689 if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION, 2690 &screen->cmd_parser_version) < 0) { 2691 /* Command parser does not exist - getparam is unrecognized */ 2692 screen->cmd_parser_version = 0; 2693 } 2694 2695 /* Kernel 4.13 retuired for exec object capture */ 2696 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) { 2697 screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE; 2698 } 2699 2700 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_BATCH_FIRST)) { 2701 screen->kernel_features |= KERNEL_ALLOWS_EXEC_BATCH_FIRST; 2702 } 2703 2704 if (!intel_detect_pipelined_so(screen)) { 2705 /* We can't do anything, so the effective version is 0. */ 2706 screen->cmd_parser_version = 0; 2707 } else { 2708 screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES; 2709 } 2710 2711 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2) 2712 screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES; 2713 2714 /* Haswell requires command parser version 4 in order to have L3 2715 * atomic scratch1 and chicken3 bits 2716 */ 2717 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { 2718 screen->kernel_features |= 2719 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; 2720 } 2721 2722 /* Haswell requires command parser version 6 in order to write to the 2723 * MI_MATH GPR registers, and version 7 in order to use 2724 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). 2725 */ 2726 if (devinfo->gen >= 8 || 2727 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { 2728 screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; 2729 } 2730 2731 /* Gen7 needs at least command parser version 5 to support compute */ 2732 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5) 2733 screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH; 2734 2735 if (intel_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION)) 2736 screen->kernel_features |= KERNEL_ALLOWS_CONTEXT_ISOLATION; 2737 2738 const char *force_msaa = getenv("INTEL_FORCE_MSAA"); 2739 if (force_msaa) { 2740 screen->winsys_msaa_samples_override = 2741 intel_quantize_num_samples(screen, atoi(force_msaa)); 2742 printf("Forcing winsys sample count to %d\n", 2743 screen->winsys_msaa_samples_override); 2744 } else { 2745 screen->winsys_msaa_samples_override = -1; 2746 } 2747 2748 set_max_gl_versions(screen); 2749 2750 /* Notification of GPU resets requires hardware contexts and a kernel new 2751 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is 2752 * supported, calling it with a context of 0 will either generate EPERM or 2753 * no error. If the ioctl is not supported, it always generate EINVAL. 2754 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS 2755 * extension to the loader. 2756 * 2757 * Don't even try on pre-Gen6, since we don't attempt to use contexts there. 2758 */ 2759 if (devinfo->gen >= 6) { 2760 struct drm_i915_reset_stats stats; 2761 memset(&stats, 0, sizeof(stats)); 2762 2763 const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); 2764 2765 screen->has_context_reset_notification = 2766 (ret != -1 || errno != EINVAL); 2767 } 2768 2769 dri_screen->extensions = !screen->has_context_reset_notification 2770 ? screenExtensions : intelRobustScreenExtensions; 2771 2772 screen->compiler = brw_compiler_create(screen, devinfo); 2773 screen->compiler->shader_debug_log = shader_debug_log_mesa; 2774 screen->compiler->shader_perf_log = shader_perf_log_mesa; 2775 2776 /* Changing the meaning of constant buffer pointers from a dynamic state 2777 * offset to an absolute address is only safe if the kernel isolates other 2778 * contexts from our changes. 2779 */ 2780 screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 || 2781 !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION); 2782 2783 screen->compiler->supports_pull_constants = true; 2784 2785 screen->has_exec_fence = 2786 intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE); 2787 2788 intel_screen_init_surface_formats(screen); 2789 2790 if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) { 2791 unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER); 2792 if (caps) { 2793 fprintf(stderr, "Kernel scheduler detected: %08x\n", caps); 2794 if (caps & I915_SCHEDULER_CAP_PRIORITY) 2795 fprintf(stderr, " - User priority sorting enabled\n"); 2796 if (caps & I915_SCHEDULER_CAP_PREEMPTION) 2797 fprintf(stderr, " - Preemption enabled\n"); 2798 } 2799 } 2800 2801 brw_disk_cache_init(screen); 2802 2803 return (const __DRIconfig**) intel_screen_make_configs(dri_screen); 2804} 2805 2806struct intel_buffer { 2807 __DRIbuffer base; 2808 struct brw_bo *bo; 2809}; 2810 2811static __DRIbuffer * 2812intelAllocateBuffer(__DRIscreen *dri_screen, 2813 unsigned attachment, unsigned format, 2814 int width, int height) 2815{ 2816 struct intel_buffer *intelBuffer; 2817 struct intel_screen *screen = dri_screen->driverPrivate; 2818 2819 assert(attachment == __DRI_BUFFER_FRONT_LEFT || 2820 attachment == __DRI_BUFFER_BACK_LEFT); 2821 2822 intelBuffer = calloc(1, sizeof *intelBuffer); 2823 if (intelBuffer == NULL) 2824 return NULL; 2825 2826 /* The front and back buffers are color buffers, which are X tiled. GEN9+ 2827 * supports Y tiled and compressed buffers, but there is no way to plumb that 2828 * through to here. */ 2829 uint32_t pitch; 2830 int cpp = format / 8; 2831 intelBuffer->bo = brw_bo_alloc_tiled_2d(screen->bufmgr, 2832 "intelAllocateBuffer", 2833 width, 2834 height, 2835 cpp, 2836 BRW_MEMZONE_OTHER, 2837 I915_TILING_X, &pitch, 2838 BO_ALLOC_BUSY); 2839 2840 if (intelBuffer->bo == NULL) { 2841 free(intelBuffer); 2842 return NULL; 2843 } 2844 2845 brw_bo_flink(intelBuffer->bo, &intelBuffer->base.name); 2846 2847 intelBuffer->base.attachment = attachment; 2848 intelBuffer->base.cpp = cpp; 2849 intelBuffer->base.pitch = pitch; 2850 2851 return &intelBuffer->base; 2852} 2853 2854static void 2855intelReleaseBuffer(__DRIscreen *dri_screen, __DRIbuffer *buffer) 2856{ 2857 struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer; 2858 2859 brw_bo_unreference(intelBuffer->bo); 2860 free(intelBuffer); 2861} 2862 2863static const struct __DriverAPIRec brw_driver_api = { 2864 .InitScreen = intelInitScreen2, 2865 .DestroyScreen = intelDestroyScreen, 2866 .CreateContext = brwCreateContext, 2867 .DestroyContext = intelDestroyContext, 2868 .CreateBuffer = intelCreateBuffer, 2869 .DestroyBuffer = intelDestroyBuffer, 2870 .MakeCurrent = intelMakeCurrent, 2871 .UnbindContext = intelUnbindContext, 2872 .AllocateBuffer = intelAllocateBuffer, 2873 .ReleaseBuffer = intelReleaseBuffer 2874}; 2875 2876static const struct __DRIDriverVtableExtensionRec brw_vtable = { 2877 .base = { __DRI_DRIVER_VTABLE, 1 }, 2878 .vtable = &brw_driver_api, 2879}; 2880 2881static const __DRIextension *brw_driver_extensions[] = { 2882 &driCoreExtension.base, 2883 &driImageDriverExtension.base, 2884 &driDRI2Extension.base, 2885 &brw_vtable.base, 2886 &brw_config_options.base, 2887 NULL 2888}; 2889 2890PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void) 2891{ 2892 globalDriverAPI = &brw_driver_api; 2893 2894 return brw_driver_extensions; 2895} 2896