1/* 2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Gareth Hughes <gareth@valinux.com> 27 * Keith Whitwell <keithw@vmware.com> 28 */ 29 30#include "main/errors.h" 31#include "main/glheader.h" 32#include "main/imports.h" 33#include "main/api_arrayelt.h" 34 35#include "swrast/swrast.h" 36#include "vbo/vbo.h" 37#include "tnl/t_pipeline.h" 38#include "swrast_setup/swrast_setup.h" 39 40#include "radeon_context.h" 41#include "radeon_mipmap_tree.h" 42#include "radeon_ioctl.h" 43#include "radeon_state.h" 44#include "radeon_queryobj.h" 45 46#include "../r200/r200_reg.h" 47 48#include "util/xmlpool.h" 49 50/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 51 * 1.3 cmdbuffers allow all previous state to be updated as well as 52 * the tcl scalar and vector areas. 53 */ 54static struct { 55 int start; 56 int len; 57 const char *name; 58} packet[RADEON_MAX_STATE_PACKETS] = { 59 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 60 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 61 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 62 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 63 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 64 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 65 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 66 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 67 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 68 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 69 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 70 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 71 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 72 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 73 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 74 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 75 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 76 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 77 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 78 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 79 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 80 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 81 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 82 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 83 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 84 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 85 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 86 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 87 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 88 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 89 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 90 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 91 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 92 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 93 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 94 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 95 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 96 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 97 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 98 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 99 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 100 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 101 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 102 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 103 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 104 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 105 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 106 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 107 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 108 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 109 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 110 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 111 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 112 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 113 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 114 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 115 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 116 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 117 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 118 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 119 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 120 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 121 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 122 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 123 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 124 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 125 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 126 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 127 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 128 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 129 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 130 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 131 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 132 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 133 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 134 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 135 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 136 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 137 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 138 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 139 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 140 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 141 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 142 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 143 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 144 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 145 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 146 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 147 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 148 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 149 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 150 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 151 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 152 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 153 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 154 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 155 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 156 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 157}; 158 159/* ============================================================= 160 * State initialization 161 */ 162static int cmdpkt( r100ContextPtr rmesa, int id ) 163{ 164 return CP_PACKET0(packet[id].start, packet[id].len - 1); 165} 166 167static int cmdvec( int offset, int stride, int count ) 168{ 169 drm_radeon_cmd_header_t h; 170 h.i = 0; 171 h.vectors.cmd_type = RADEON_CMD_VECTORS; 172 h.vectors.offset = offset; 173 h.vectors.stride = stride; 174 h.vectors.count = count; 175 return h.i; 176} 177 178static int cmdscl( int offset, int stride, int count ) 179{ 180 drm_radeon_cmd_header_t h; 181 h.i = 0; 182 h.scalars.cmd_type = RADEON_CMD_SCALARS; 183 h.scalars.offset = offset; 184 h.scalars.stride = stride; 185 h.scalars.count = count; 186 return h.i; 187} 188 189#define CHECK( NM, FLAG, ADD ) \ 190static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 191{ \ 192 return FLAG ? atom->cmd_size + (ADD) : 0; \ 193} 194 195#define TCL_CHECK( NM, FLAG, ADD ) \ 196static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 197{ \ 198 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 199 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 200} 201 202 203CHECK( always, GL_TRUE, 0 ) 204CHECK( always_add2, GL_TRUE, 2 ) 205CHECK( always_add4, GL_TRUE, 4 ) 206CHECK( tex0_mm, GL_TRUE, 3 ) 207CHECK( tex1_mm, GL_TRUE, 3 ) 208/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ 209CHECK( tex2_mm, GL_TRUE, 3 ) 210CHECK( cube0_mm, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) 211CHECK( cube1_mm, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) 212CHECK( cube2_mm, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_CUBE_MAP), 2 + 4*5 - CUBE_STATE_SIZE ) 213CHECK( fog_add4, ctx->Fog.Enabled, 4 ) 214TCL_CHECK( tcl_add4, GL_TRUE, 4 ) 215TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._Current, 4 ) 216TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._Current, 4 ) 217TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._Current, 4 ) 218TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) 219TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) 220TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 ) 221TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 ) 222TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 ) 223TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 ) 224TCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 ) 225TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 ) 226TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 ) 227TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 ) 228TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 ) 229TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 ) 230TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 ) 231TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 ) 232TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 ) 233TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 ) 234TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 ) 235TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 ) 236 237CHECK( txr0, (ctx->Texture.Unit[0]._Current && ctx->Texture.Unit[0]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) 238CHECK( txr1, (ctx->Texture.Unit[1]._Current && ctx->Texture.Unit[1]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) 239CHECK( txr2, (ctx->Texture.Unit[2]._Current && ctx->Texture.Unit[2]._Current->Target == GL_TEXTURE_RECTANGLE), 0 ) 240 241#define OUT_VEC(hdr, data) do { \ 242 drm_radeon_cmd_header_t h; \ 243 h.i = hdr; \ 244 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 245 OUT_BATCH(0); \ 246 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 247 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 248 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 249 OUT_BATCH_TABLE((data), h.vectors.count); \ 250 } while(0) 251 252#define OUT_SCL(hdr, data) do { \ 253 drm_radeon_cmd_header_t h; \ 254 h.i = hdr; \ 255 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 256 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 257 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 258 OUT_BATCH_TABLE((data), h.scalars.count); \ 259 } while(0) 260 261static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 262{ 263 r100ContextPtr r100 = R100_CONTEXT(ctx); 264 BATCH_LOCALS(&r100->radeon); 265 uint32_t dwords = atom->check(ctx, atom); 266 267 BEGIN_BATCH(dwords); 268 OUT_SCL(atom->cmd[0], atom->cmd+1); 269 END_BATCH(); 270} 271 272 273static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 274{ 275 r100ContextPtr r100 = R100_CONTEXT(ctx); 276 BATCH_LOCALS(&r100->radeon); 277 uint32_t dwords = atom->check(ctx, atom); 278 279 BEGIN_BATCH(dwords); 280 OUT_VEC(atom->cmd[0], atom->cmd+1); 281 END_BATCH(); 282} 283 284 285static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 286{ 287 r100ContextPtr r100 = R100_CONTEXT(ctx); 288 BATCH_LOCALS(&r100->radeon); 289 uint32_t dwords = atom->check(ctx, atom); 290 291 BEGIN_BATCH(dwords); 292 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); 293 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); 294 END_BATCH(); 295} 296 297static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) 298{ 299 r100ContextPtr r100 = R100_CONTEXT(ctx); 300 struct radeon_renderbuffer *rrb, *drb; 301 uint32_t dwords; 302 303 rrb = radeon_get_colorbuffer(&r100->radeon); 304 if (!rrb || !rrb->bo) { 305 return 0; 306 } 307 308 drb = radeon_get_depthbuffer(&r100->radeon); 309 310 dwords = 10; 311 if (drb) 312 dwords += 6; 313 if (rrb) 314 dwords += 8; 315 316 return dwords; 317} 318 319static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 320{ 321 r100ContextPtr r100 = R100_CONTEXT(ctx); 322 BATCH_LOCALS(&r100->radeon); 323 struct radeon_renderbuffer *rrb, *drb; 324 uint32_t cbpitch = 0; 325 uint32_t zbpitch = 0; 326 uint32_t dwords = atom->check(ctx, atom); 327 uint32_t depth_fmt; 328 329 rrb = radeon_get_colorbuffer(&r100->radeon); 330 if (!rrb || !rrb->bo) { 331 fprintf(stderr, "no rrb\n"); 332 return; 333 } 334 335 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 336 if (rrb->cpp == 4) 337 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 338 else switch (rrb->base.Base.Format) { 339 case MESA_FORMAT_B5G6R5_UNORM: 340 case MESA_FORMAT_R5G6B5_UNORM: 341 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 342 break; 343 case MESA_FORMAT_B4G4R4A4_UNORM: 344 case MESA_FORMAT_A4R4G4B4_UNORM: 345 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; 346 break; 347 case MESA_FORMAT_B5G5R5A1_UNORM: 348 case MESA_FORMAT_A1R5G5B5_UNORM: 349 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; 350 break; 351 default: 352 _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); 353 } 354 355 cbpitch = (rrb->pitch / rrb->cpp); 356 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 357 cbpitch |= R200_COLOR_TILE_ENABLE; 358 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 359 cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; 360 361 drb = radeon_get_depthbuffer(&r100->radeon); 362 if (drb) { 363 zbpitch = (drb->pitch / drb->cpp); 364 if (drb->cpp == 4) 365 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 366 else 367 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 368 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 369 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 370 371 } 372 373 BEGIN_BATCH(dwords); 374 375 /* In the CS case we need to split this up */ 376 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 377 OUT_BATCH_TABLE((atom->cmd + 1), 4); 378 379 if (drb) { 380 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 381 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 382 383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 384 OUT_BATCH(zbpitch); 385 } 386 387 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 388 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 389 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 390 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 391 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 392 393 if (rrb) { 394 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 395 OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); 396 397 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 398 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); 399 } 400 401 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 402 // OUT_BATCH_TABLE((atom->cmd + 14), 4); 403 // } 404 405 END_BATCH(); 406 BEGIN_BATCH(4); 407 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 408 OUT_BATCH(0); 409 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 410 if (rrb) { 411 OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | 412 ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); 413 } else { 414 OUT_BATCH(0); 415 } 416 END_BATCH(); 417} 418 419static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 420{ 421 r100ContextPtr r100 = R100_CONTEXT(ctx); 422 BATCH_LOCALS(&r100->radeon); 423 uint32_t dwords = atom->check(ctx, atom); 424 int i = atom->idx, j; 425 radeonTexObj *t = r100->state.texture.unit[i].texobj; 426 radeon_mipmap_level *lvl; 427 uint32_t base_reg; 428 429 if (!ctx->Texture.Unit[i]._Current || 430 ctx->Texture.Unit[i]._Current->Target != GL_TEXTURE_CUBE_MAP) 431 return; 432 433 if (!t) 434 return; 435 436 if (!t->mt) 437 return; 438 439 switch(i) { 440 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 441 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 442 default: 443 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 444 } 445 BEGIN_BATCH(dwords); 446 OUT_BATCH_TABLE(atom->cmd, 2); 447 lvl = &t->mt->levels[0]; 448 for (j = 0; j < 5; j++) { 449 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); 450 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 451 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 452 } 453 END_BATCH(); 454} 455 456static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 457{ 458 r100ContextPtr r100 = R100_CONTEXT(ctx); 459 BATCH_LOCALS(&r100->radeon); 460 uint32_t dwords = atom->cmd_size; 461 int i = atom->idx; 462 radeonTexObj *t = r100->state.texture.unit[i].texobj; 463 radeon_mipmap_level *lvl; 464 int hastexture = 1; 465 466 if (!t) 467 hastexture = 0; 468 else { 469 if (!t->mt && !t->bo) 470 hastexture = 0; 471 } 472 dwords += 1; 473 if (hastexture) 474 dwords += 2; 475 else 476 dwords -= 2; 477 BEGIN_BATCH(dwords); 478 479 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); 480 OUT_BATCH_TABLE((atom->cmd + 1), 2); 481 482 if (hastexture) { 483 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); 484 if (t->mt && !t->image_override) { 485 if (ctx->Texture.Unit[i]._Current && 486 ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) { 487 lvl = &t->mt->levels[t->minLod]; 488 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, 489 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 490 } else { 491 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), 492 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 493 } 494 } else { 495 if (t->bo) 496 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 497 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 498 } 499 } 500 501 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); 502 OUT_BATCH_TABLE((atom->cmd+4), 2); 503 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); 504 OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); 505 END_BATCH(); 506} 507 508/* Initialize the context's hardware state. 509 */ 510void radeonInitState( r100ContextPtr rmesa ) 511{ 512 struct gl_context *ctx = &rmesa->radeon.glCtx; 513 GLuint i; 514 515 rmesa->radeon.Fallback = 0; 516 517 518 rmesa->radeon.hw.max_state_size = 0; 519 520#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ 521 do { \ 522 rmesa->hw.ATOM.cmd_size = SZ; \ 523 rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ 524 rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ 525 rmesa->hw.ATOM.name = NM; \ 526 rmesa->hw.ATOM.is_tcl = FLAG; \ 527 rmesa->hw.ATOM.check = check_##CHK; \ 528 rmesa->hw.ATOM.dirty = GL_TRUE; \ 529 rmesa->hw.ATOM.idx = IDX; \ 530 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 531 } while (0) 532 533#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 534 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) 535 536 /* Allocate state buffers: 537 */ 538 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 ); 539 rmesa->hw.ctx.emit = ctx_emit_cs; 540 rmesa->hw.ctx.check = check_always_ctx; 541 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 542 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 543 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 544 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 545 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 546 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 547 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 548 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 549 ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 550 ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 ); 551 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 ); 552 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 553 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); 554 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); 555 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); 556 ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 557 ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 ); 558 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 559 ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 560 ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 561 ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 ); 562 ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 ); 563 ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); 564 ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 ); 565 ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 ); 566 ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 ); 567 ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 ); 568 ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 569 ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 ); 570 ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 571 ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 572 ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 573 ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 574 ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 575 ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 576 ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); 577 578 for (i = 0; i < 3; i++) { 579 rmesa->hw.tex[i].emit = tex_emit_cs; 580 } 581 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); 582 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); 583 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); 584 for (i = 0; i < 3; i++) 585 rmesa->hw.cube[i].emit = cube_emit_cs; 586 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); 588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); 589 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); 590 591 radeonSetUpAtomList( rmesa ); 592 593 /* Fill in the packet headers: 594 */ 595 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 596 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 597 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 598 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 599 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 600 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 601 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 602 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 603 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS); 604 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 605 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0); 606 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0); 607 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1); 608 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1); 609 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2); 610 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2); 611 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0); 612 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0); 613 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1); 614 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1); 615 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2); 616 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); 617 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 618 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 619 rmesa->hw.mtl.cmd[MTL_CMD_0] = 620 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 621 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); 622 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); 623 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); 624 rmesa->hw.grd.cmd[GRD_CMD_0] = 625 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 626 rmesa->hw.fog.cmd[FOG_CMD_0] = 627 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 628 rmesa->hw.glt.cmd[GLT_CMD_0] = 629 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 630 rmesa->hw.eye.cmd[EYE_CMD_0] = 631 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 632 633 for (i = 0 ; i < 6; i++) { 634 rmesa->hw.mat[i].cmd[MAT_CMD_0] = 635 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 636 } 637 638 for (i = 0 ; i < 8; i++) { 639 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 640 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 641 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 642 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 643 } 644 645 for (i = 0 ; i < 6; i++) { 646 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 647 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 648 } 649 650 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); 651 rmesa->hw.stp.cmd[STP_DATA_0] = 0; 652 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); 653 654 rmesa->hw.grd.emit = scl_emit; 655 rmesa->hw.fog.emit = vec_emit; 656 rmesa->hw.glt.emit = vec_emit; 657 rmesa->hw.eye.emit = vec_emit; 658 for (i = 0; i < 6; i++) 659 rmesa->hw.mat[i].emit = vec_emit; 660 661 for (i = 0; i < 8; i++) 662 rmesa->hw.lit[i].emit = lit_emit; 663 664 for (i = 0; i < 6; i++) 665 rmesa->hw.ucp[i].emit = vec_emit; 666 667 /* Initial Harware state: 668 */ 669 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 670 RADEON_CHROMA_FUNC_FAIL | 671 RADEON_CHROMA_KEY_NEAREST | 672 RADEON_SHADOW_FUNC_EQUAL | 673 RADEON_SHADOW_PASS_1 /*| 674 RADEON_RIGHT_HAND_CUBE_OGL */); 675 676 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 677 /* this bit unused for vertex fog */ 678 RADEON_FOG_USE_DEPTH); 679 680 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 681 682 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 683 RADEON_SRC_BLEND_GL_ONE | 684 RADEON_DST_BLEND_GL_ZERO ); 685 686 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS | 687 RADEON_STENCIL_TEST_ALWAYS | 688 RADEON_STENCIL_FAIL_KEEP | 689 RADEON_STENCIL_ZPASS_KEEP | 690 RADEON_STENCIL_ZFAIL_KEEP | 691 RADEON_Z_WRITE_ENABLE); 692 693 if (rmesa->using_hyperz) { 694 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | 695 RADEON_Z_DECOMPRESSION_ENABLE; 696 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 697 /* works for q3, but slight rendering errors with glxgears ? */ 698/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 699 /* need this otherwise get lots of lockups with q3 ??? */ 700 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; 701 } 702 } 703 704 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 705 RADEON_ANTI_ALIAS_NONE); 706 707 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 708 RADEON_ZBLOCK16); 709 710 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 711 case DRI_CONF_DITHER_XERRORDIFFRESET: 712 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 713 break; 714 case DRI_CONF_DITHER_ORDERED: 715 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 716 break; 717 } 718 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 719 DRI_CONF_ROUND_ROUND ) 720 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE; 721 else 722 rmesa->radeon.state.color.roundEnable = 0; 723 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 724 DRI_CONF_COLOR_REDUCTION_DITHER ) 725 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 726 else 727 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 728 729 730 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 731 RADEON_BFACE_SOLID | 732 RADEON_FFACE_SOLID | 733/* RADEON_BADVTX_CULL_DISABLE | */ 734 RADEON_FLAT_SHADE_VTX_LAST | 735 RADEON_DIFFUSE_SHADE_GOURAUD | 736 RADEON_ALPHA_SHADE_GOURAUD | 737 RADEON_SPECULAR_SHADE_GOURAUD | 738 RADEON_FOG_SHADE_GOURAUD | 739 RADEON_VPORT_XY_XFORM_ENABLE | 740 RADEON_VPORT_Z_XFORM_ENABLE | 741 RADEON_VTX_PIX_CENTER_OGL | 742 RADEON_ROUND_MODE_TRUNC | 743 RADEON_ROUND_PREC_8TH_PIX); 744 745 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 746#ifdef MESA_BIG_ENDIAN 747 RADEON_VC_32BIT_SWAP; 748#else 749 RADEON_VC_NO_SWAP; 750#endif 751 752 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 753 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 754 } 755 756 rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 757 RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 758 RADEON_TEX1_W_ROUTING_USE_Q1); 759 760 761 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 762 763 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 764 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 765 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 766 767 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 768 769 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 770 ((0x00 << RADEON_STENCIL_REF_SHIFT) | 771 (0xff << RADEON_STENCIL_MASK_SHIFT) | 772 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 773 774 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 775 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 776 777 rmesa->hw.msc.cmd[MSC_RE_MISC] = 778 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 779 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 780 RADEON_STIPPLE_BIG_BIT_ORDER); 781 782 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 783 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 784 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 785 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 786 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 787 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 788 789 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 790 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 791 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 792 (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 793 RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 794 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 795 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 796 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 797 798 /* Initialize the texture offset to the start of the card texture heap */ 799 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 800 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 801 802 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 803 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 804 (RADEON_COLOR_ARG_A_ZERO | 805 RADEON_COLOR_ARG_B_ZERO | 806 RADEON_COLOR_ARG_C_CURRENT_COLOR | 807 RADEON_BLEND_CTL_ADD | 808 RADEON_SCALE_1X | 809 RADEON_CLAMP_TX); 810 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 811 (RADEON_ALPHA_ARG_A_ZERO | 812 RADEON_ALPHA_ARG_B_ZERO | 813 RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 814 RADEON_BLEND_CTL_ADD | 815 RADEON_SCALE_1X | 816 RADEON_CLAMP_TX); 817 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 818 819 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 820 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = 821 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 822 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = 823 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 824 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = 825 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 826 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = 827 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 828 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = 829 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 830 } 831 832 /* Can only add ST1 at the time of doing some multitex but can keep 833 * it after that. Errors if DIFFUSE is missing. 834 */ 835 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 836 (RADEON_TCL_VTX_Z0 | 837 RADEON_TCL_VTX_W0 | 838 RADEON_TCL_VTX_PK_DIFFUSE 839 ); /* need to keep this uptodate */ 840 841 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 842 ( RADEON_TCL_COMPUTE_XYZW | 843 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 844 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 845 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 846 847 848 /* XXX */ 849 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 850 ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 851 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 852 853 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 854 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 855 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 856 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | 857 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); 858 859 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 860 (RADEON_UCP_IN_CLIP_SPACE | 861 RADEON_CULL_FRONT_IS_CCW); 862 863 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 864 865 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 866 (RADEON_SPECULAR_LIGHTS | 867 RADEON_DIFFUSE_SPECULAR_COMBINE | 868 RADEON_LOCAL_LIGHT_VEC_GL | 869 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 870 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 871 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 872 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 873 874 for (i = 0 ; i < 8; i++) { 875 struct gl_light *l = &ctx->Light.Light[i]; 876 GLenum p = GL_LIGHT0 + i; 877 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 878 879 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 880 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 881 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 882 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 883 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 884 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 885 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 886 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 887 &l->ConstantAttenuation ); 888 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 889 &l->LinearAttenuation ); 890 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 891 &l->QuadraticAttenuation ); 892 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 893 } 894 895 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 896 ctx->Light.Model.Ambient ); 897 898 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 899 900 for (i = 0 ; i < 6; i++) { 901 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 902 } 903 904 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 905 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 906 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 907 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 908 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 909 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 910 911 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 912 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 913 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 914 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 915 916 rmesa->hw.eye.cmd[EYE_X] = 0; 917 rmesa->hw.eye.cmd[EYE_Y] = 0; 918 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 919 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 920 921 radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); 922 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); 923 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; 924 925 rmesa->radeon.hw.all_dirty = GL_TRUE; 926 927 rcommonInitCmdBuf(&rmesa->radeon); 928} 929