1848b8605Smrg/* 2848b8605Smrg * SPARC assembly matrix code. 3848b8605Smrg */ 4848b8605Smrg 5848b8605Smrg#ifndef _SPARC_MATRIX_H 6848b8605Smrg#define _SPARC_MATRIX_H 7848b8605Smrg 8848b8605Smrg#ifdef __arch64__ 9848b8605Smrg#define LDPTR ldx 10848b8605Smrg#define MAT_M 0x00 11848b8605Smrg#define MAT_INV 0x08 12848b8605Smrg#define V4F_DATA 0x00 13848b8605Smrg#define V4F_START 0x08 14848b8605Smrg#define V4F_COUNT 0x10 15848b8605Smrg#define V4F_STRIDE 0x14 16848b8605Smrg#define V4F_SIZE 0x18 17848b8605Smrg#define V4F_FLAGS 0x1c 18848b8605Smrg#else 19848b8605Smrg#define LDPTR ld 20848b8605Smrg#define MAT_M 0x00 21848b8605Smrg#define MAT_INV 0x04 22848b8605Smrg#define V4F_DATA 0x00 23848b8605Smrg#define V4F_START 0x04 24848b8605Smrg#define V4F_COUNT 0x08 25848b8605Smrg#define V4F_STRIDE 0x0c 26848b8605Smrg#define V4F_SIZE 0x10 27848b8605Smrg#define V4F_FLAGS 0x14 28848b8605Smrg#endif 29848b8605Smrg 30848b8605Smrg#define VEC_SIZE_1 1 31848b8605Smrg#define VEC_SIZE_2 3 32848b8605Smrg#define VEC_SIZE_3 7 33848b8605Smrg#define VEC_SIZE_4 15 34848b8605Smrg 35848b8605Smrg#define M0 %f16 36848b8605Smrg#define M1 %f17 37848b8605Smrg#define M2 %f18 38848b8605Smrg#define M3 %f19 39848b8605Smrg#define M4 %f20 40848b8605Smrg#define M5 %f21 41848b8605Smrg#define M6 %f22 42848b8605Smrg#define M7 %f23 43848b8605Smrg#define M8 %f24 44848b8605Smrg#define M9 %f25 45848b8605Smrg#define M10 %f26 46848b8605Smrg#define M11 %f27 47848b8605Smrg#define M12 %f28 48848b8605Smrg#define M13 %f29 49848b8605Smrg#define M14 %f30 50848b8605Smrg#define M15 %f31 51848b8605Smrg 52848b8605Smrg#define LDMATRIX_0_1_2_3_12_13_14_15(BASE) \ 53848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 54848b8605Smrg ldd [BASE + ( 2 * 0x4)], M2; \ 55848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 56848b8605Smrg ldd [BASE + (14 * 0x4)], M14 57848b8605Smrg 58848b8605Smrg#define LDMATRIX_0_1_12_13(BASE) \ 59848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 60848b8605Smrg ldd [BASE + (12 * 0x4)], M12 61848b8605Smrg 62848b8605Smrg#define LDMATRIX_0_12_13(BASE) \ 63848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 64848b8605Smrg ldd [BASE + (12 * 0x4)], M12 65848b8605Smrg 66848b8605Smrg#define LDMATRIX_0_1_2_12_13_14(BASE) \ 67848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 68848b8605Smrg ld [BASE + ( 2 * 0x4)], M2; \ 69848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 70848b8605Smrg ld [BASE + (14 * 0x4)], M14 71848b8605Smrg 72848b8605Smrg#define LDMATRIX_0_12_13_14(BASE) \ 73848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 74848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 75848b8605Smrg ld [BASE + (14 * 0x4)], M14 76848b8605Smrg 77848b8605Smrg#define LDMATRIX_0_14(BASE) \ 78848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 79848b8605Smrg ld [BASE + (14 * 0x4)], M14 80848b8605Smrg 81848b8605Smrg#define LDMATRIX_0_1_2_3_4_5_6_7_12_13_14_15(BASE) \ 82848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 83848b8605Smrg ldd [BASE + ( 2 * 0x4)], M2; \ 84848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 85848b8605Smrg ldd [BASE + ( 6 * 0x4)], M6; \ 86848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 87848b8605Smrg ldd [BASE + (14 * 0x4)], M14 88848b8605Smrg 89848b8605Smrg#define LDMATRIX_0_5_12_13(BASE) \ 90848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 91848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 92848b8605Smrg ldd [BASE + (12 * 0x4)], M12 93848b8605Smrg 94848b8605Smrg#define LDMATRIX_0_1_2_3_4_5_6_12_13_14(BASE) \ 95848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 96848b8605Smrg ldd [BASE + ( 2 * 0x4)], M2; \ 97848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 98848b8605Smrg ld [BASE + ( 6 * 0x4)], M6; \ 99848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 100848b8605Smrg ld [BASE + (14 * 0x4)], M14 101848b8605Smrg 102848b8605Smrg#define LDMATRIX_0_5_12_13_14(BASE) \ 103848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 104848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 105848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 106848b8605Smrg ld [BASE + (14 * 0x4)], M14 107848b8605Smrg 108848b8605Smrg#define LDMATRIX_0_5_14(BASE) \ 109848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 110848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 111848b8605Smrg ld [BASE + (14 * 0x4)], M14 112848b8605Smrg 113848b8605Smrg#define LDMATRIX_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15(BASE) \ 114848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 115848b8605Smrg ldd [BASE + ( 2 * 0x4)], M2; \ 116848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 117848b8605Smrg ldd [BASE + ( 6 * 0x4)], M6; \ 118848b8605Smrg ldd [BASE + ( 8 * 0x4)], M8; \ 119848b8605Smrg ldd [BASE + (10 * 0x4)], M10; \ 120848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 121848b8605Smrg ldd [BASE + (14 * 0x4)], M14 122848b8605Smrg 123848b8605Smrg#define LDMATRIX_0_1_4_5_12_13(BASE) \ 124848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 125848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 126848b8605Smrg ldd [BASE + (12 * 0x4)], M12 127848b8605Smrg 128848b8605Smrg#define LDMATRIX_0_5_12_13(BASE) \ 129848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 130848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 131848b8605Smrg ldd [BASE + (12 * 0x4)], M12 132848b8605Smrg 133848b8605Smrg#define LDMATRIX_0_1_2_4_5_6_8_9_10(BASE) \ 134848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 135848b8605Smrg ld [BASE + ( 2 * 0x4)], M2; \ 136848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 137848b8605Smrg ld [BASE + ( 6 * 0x4)], M6; \ 138848b8605Smrg ldd [BASE + ( 8 * 0x4)], M8; \ 139848b8605Smrg ld [BASE + (10 * 0x4)], M10 140848b8605Smrg 141848b8605Smrg#define LDMATRIX_0_1_2_4_5_6_8_9_10_12_13_14(BASE) \ 142848b8605Smrg ldd [BASE + ( 0 * 0x4)], M0; \ 143848b8605Smrg ld [BASE + ( 2 * 0x4)], M2; \ 144848b8605Smrg ldd [BASE + ( 4 * 0x4)], M4; \ 145848b8605Smrg ld [BASE + ( 6 * 0x4)], M6; \ 146848b8605Smrg ldd [BASE + ( 8 * 0x4)], M8; \ 147848b8605Smrg ld [BASE + (10 * 0x4)], M10; \ 148848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 149848b8605Smrg ld [BASE + (14 * 0x4)], M14 150848b8605Smrg 151848b8605Smrg#define LDMATRIX_0_5_10(BASE) \ 152848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 153848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 154b8e80941Smrg ld [BASE + (10 * 0x4)], M10; 155848b8605Smrg 156848b8605Smrg#define LDMATRIX_0_5_10_12_13_14(BASE) \ 157848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 158848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 159848b8605Smrg ld [BASE + (10 * 0x4)], M10; \ 160848b8605Smrg ldd [BASE + (12 * 0x4)], M12; \ 161848b8605Smrg ld [BASE + (14 * 0x4)], M14 162848b8605Smrg 163848b8605Smrg#define LDMATRIX_0_5_8_9_10_14(BASE) \ 164848b8605Smrg ld [BASE + ( 0 * 0x4)], M0; \ 165848b8605Smrg ld [BASE + ( 5 * 0x4)], M5; \ 166848b8605Smrg ldd [BASE + ( 8 * 0x4)], M8; \ 167848b8605Smrg ld [BASE + (10 * 0x4)], M10; \ 168848b8605Smrg ld [BASE + (14 * 0x4)], M14 169848b8605Smrg 170848b8605Smrg#endif /* !(_SPARC_MATRIX_H) */ 171