17ec681f3SmrgMesa 11.0.8 Release Notes / December 9, 2015
27ec681f3Smrg============================================
37ec681f3Smrg
47ec681f3SmrgMesa 11.0.8 is a bug fix release which fixes bugs found since the 11.0.7
57ec681f3Smrgrelease.
67ec681f3Smrg
77ec681f3SmrgMesa 11.0.8 implements the OpenGL 4.1 API, but the version reported by
87ec681f3SmrgglGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
97ec681f3SmrgglGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
107ec681f3Smrgused. Some drivers don't support all the features required in OpenGL
117ec681f3Smrg4.1. OpenGL 4.1 is **only** available if requested at context creation
127ec681f3Smrgbecause compatibility contexts are not supported.
137ec681f3Smrg
147ec681f3SmrgSHA256 checksums
157ec681f3Smrg----------------
167ec681f3Smrg
177ec681f3Smrg::
187ec681f3Smrg
197ec681f3Smrg   ab9db87b54d7525e4b611b82577ea9a9eae55927558df57b190059d5ecd9406f  mesa-11.0.8.tar.gz
207ec681f3Smrg   5696e4730518b6805d2ed5def393c4293f425a2c2c01bd5ed4bdd7ad62f7ad75  mesa-11.0.8.tar.xz
217ec681f3Smrg
227ec681f3SmrgNew features
237ec681f3Smrg------------
247ec681f3Smrg
257ec681f3SmrgNone
267ec681f3Smrg
277ec681f3SmrgBug fixes
287ec681f3Smrg---------
297ec681f3Smrg
307ec681f3SmrgThis list is likely incomplete.
317ec681f3Smrg
327ec681f3Smrg-  `Bug 91806 <https://bugs.freedesktop.org/show_bug.cgi?id=91806>`__ -
337ec681f3Smrg   configure does not test whether assembler supports sse4.1
347ec681f3Smrg-  `Bug 92849 <https://bugs.freedesktop.org/show_bug.cgi?id=92849>`__ -
357ec681f3Smrg   [IVB HSW BDW] piglit image load/store
367ec681f3Smrg   load-from-cleared-image.shader_test fails
377ec681f3Smrg-  `Bug 92909 <https://bugs.freedesktop.org/show_bug.cgi?id=92909>`__ -
387ec681f3Smrg   Offset/alignment issue with layout std140 and vec3
397ec681f3Smrg-  `Bug 93004 <https://bugs.freedesktop.org/show_bug.cgi?id=93004>`__ -
407ec681f3Smrg   Guild Wars 2 crash on nouveau DX11 cards
417ec681f3Smrg-  `Bug 93215 <https://bugs.freedesktop.org/show_bug.cgi?id=93215>`__ -
427ec681f3Smrg   [Regression bisected] Ogles1conform Automatic mipmap generation test
437ec681f3Smrg   is fail
447ec681f3Smrg-  `Bug 93266 <https://bugs.freedesktop.org/show_bug.cgi?id=93266>`__ -
457ec681f3Smrg   gl_arb_shading_language_420pack does not allow binding of image
467ec681f3Smrg   variables
477ec681f3Smrg
487ec681f3SmrgChanges
497ec681f3Smrg-------
507ec681f3Smrg
517ec681f3SmrgBoyuan Zhang (1):
527ec681f3Smrg
537ec681f3Smrg-  radeon/uvd: uv pitch separation for stoney
547ec681f3Smrg
557ec681f3SmrgDave Airlie (9):
567ec681f3Smrg
577ec681f3Smrg-  r600: do SQ flush ES ring rolling workaround
587ec681f3Smrg-  r600: SMX returns CONTEXT_DONE early workaround
597ec681f3Smrg-  r600/shader: split address get out to a function.
607ec681f3Smrg-  r600/shader: add utility functions to do single slot arithmatic
617ec681f3Smrg-  r600g: fix geom shader input indirect indexing.
627ec681f3Smrg-  r600: handle geometry dynamic input array index
637ec681f3Smrg-  radeonsi: handle doubles in lds load path.
647ec681f3Smrg-  mesa/varray: set double arrays to non-normalised.
657ec681f3Smrg-  mesa/shader: return correct attribute location for double matrix
667ec681f3Smrg   arrays
677ec681f3Smrg
687ec681f3SmrgEmil Velikov (8):
697ec681f3Smrg
707ec681f3Smrg-  docs: add sha256 checksums for 11.0.7
717ec681f3Smrg-  cherry-ignore: don't pick a specific i965 formats patch
727ec681f3Smrg-  Revert "i965/nir: Remove unused indirect handling"
737ec681f3Smrg-  Revert "i965/state: Get rid of dword_pitch arguments to buffer
747ec681f3Smrg   functions"
757ec681f3Smrg-  Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"
767ec681f3Smrg-  Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"
777ec681f3Smrg-  Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
787ec681f3Smrg-  Update version to 11.0.8
797ec681f3Smrg
807ec681f3SmrgFrancisco Jerez (1):
817ec681f3Smrg
827ec681f3Smrg-  i965: Resolve color and flush for all active shader images in
837ec681f3Smrg   intel_update_state().
847ec681f3Smrg
857ec681f3SmrgIan Romanick (1):
867ec681f3Smrg
877ec681f3Smrg-  meta/generate_mipmap: Work-around GLES 1.x problem with
887ec681f3Smrg   GL_DRAW_FRAMEBUFFER
897ec681f3Smrg
907ec681f3SmrgIlia Mirkin (17):
917ec681f3Smrg
927ec681f3Smrg-  freedreno/a4xx: support lod_bias
937ec681f3Smrg-  freedreno/a4xx: fix 5_5_5_1 texture sampler format
947ec681f3Smrg-  freedreno/a4xx: point regid to "red" even for alpha-only rb formats
957ec681f3Smrg-  nvc0/ir: fold postfactor into immediate
967ec681f3Smrg-  nv50/ir: deal with loops with no breaks
977ec681f3Smrg-  nv50/ir: the mad source might not have a defining instruction
987ec681f3Smrg-  nv50/ir: fix instruction permutation logic
997ec681f3Smrg-  nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
1007ec681f3Smrg-  nv50/ir: fix DCE to not generate 96-bit loads
1017ec681f3Smrg-  nv50/ir: avoid looking at uninitialized srcMods entries
1027ec681f3Smrg-  gk110/ir: fix imul hi emission with limm arg
1037ec681f3Smrg-  gk104/ir: sampler doesn't matter for txf
1047ec681f3Smrg-  gk110/ir: fix imad sat/hi flag emission for immediate args
1057ec681f3Smrg-  nv50/ir: fix cutoff for using r63 vs r127 when replacing zero
1067ec681f3Smrg-  nv50/ir: can't have predication and immediates
1077ec681f3Smrg-  glsl: assign varying locations to tess shaders when doing SSO
1087ec681f3Smrg-  ttn: add TEX2 support
1097ec681f3Smrg
1107ec681f3SmrgJason Ekstrand (5):
1117ec681f3Smrg
1127ec681f3Smrg-  i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
1137ec681f3Smrg-  i965/fs: Use a stride of 1 and byte offsets for UBOs
1147ec681f3Smrg-  i965/vec4: Use a stride of 1 and byte offsets for UBOs
1157ec681f3Smrg-  i965/state: Get rid of dword_pitch arguments to buffer functions
1167ec681f3Smrg-  i965/nir: Remove unused indirect handling
1177ec681f3Smrg
1187ec681f3SmrgJonathan Gray (2):
1197ec681f3Smrg
1207ec681f3Smrg-  configure.ac: use pkg-config for libelf
1217ec681f3Smrg-  configure: check for python2.7 for PYTHON2
1227ec681f3Smrg
1237ec681f3SmrgKenneth Graunke (2):
1247ec681f3Smrg
1257ec681f3Smrg-  i965: Fix fragment shader struct inputs.
1267ec681f3Smrg-  i965: Fix scalar vertex shader struct outputs.
1277ec681f3Smrg
1287ec681f3SmrgMarek Olšák (8):
1297ec681f3Smrg
1307ec681f3Smrg-  radeonsi: fix occlusion queries on Fiji
1317ec681f3Smrg-  radeonsi: fix a hang due to uninitialized border color registers
1327ec681f3Smrg-  radeonsi: fix Fiji for LLVM <= 3.7
1337ec681f3Smrg-  radeonsi: don't call of u_prims_for_vertices for patches and
1347ec681f3Smrg   rectangles
1357ec681f3Smrg-  radeonsi: apply the streamout workaround to Fiji as well
1367ec681f3Smrg-  gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1
1377ec681f3Smrg   correctly
1387ec681f3Smrg-  tgsi/scan: add flag colors_written
1397ec681f3Smrg-  r600g: write all MRTs only if there is exactly one output (fixes a
1407ec681f3Smrg   hang)
1417ec681f3Smrg
1427ec681f3SmrgMatt Turner (1):
1437ec681f3Smrg
1447ec681f3Smrg-  glsl: Allow binding of image variables with 420pack.
1457ec681f3Smrg
1467ec681f3SmrgNeil Roberts (2):
1477ec681f3Smrg
1487ec681f3Smrg-  i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
1497ec681f3Smrg-  i965: Add B8G8R8X8_SRGB to the alpha format override
1507ec681f3Smrg
1517ec681f3SmrgOded Gabbay (1):
1527ec681f3Smrg
1537ec681f3Smrg-  configura.ac: fix test for SSE4.1 assembler support
1547ec681f3Smrg
1557ec681f3SmrgPatrick Rudolph (2):
1567ec681f3Smrg
1577ec681f3Smrg-  nv50,nvc0: fix use-after-free when vertex buffers are unbound
1587ec681f3Smrg-  gallium/util: return correct number of bound vertex buffers
1597ec681f3Smrg
1607ec681f3SmrgSamuel Pitoiset (1):
1617ec681f3Smrg
1627ec681f3Smrg-  nvc0: free memory allocated by the prog which reads MP perf counters
1637ec681f3Smrg
1647ec681f3SmrgTapani Pälli (1):
1657ec681f3Smrg
1667ec681f3Smrg-  i965: use \_Shader to get fragment program when updating surface
1677ec681f3Smrg   state
1687ec681f3Smrg
1697ec681f3SmrgTom Stellard (2):
1707ec681f3Smrg
1717ec681f3Smrg-  radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}
1727ec681f3Smrg-  radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC\* register
1737ec681f3Smrg   values
174