17.2.6.rst revision 7ec681f3
17ec681f3SmrgMesa 17.2.6 Release Notes / November 25, 2017
27ec681f3Smrg=============================================
37ec681f3Smrg
47ec681f3SmrgMesa 17.2.6 is a bug fix release which fixes bugs found since the 17.2.5
57ec681f3Smrgrelease.
67ec681f3Smrg
77ec681f3SmrgMesa 17.2.6 implements the OpenGL 4.5 API, but the version reported by
87ec681f3SmrgglGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
97ec681f3SmrgglGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
107ec681f3Smrgused. Some drivers don't support all the features required in OpenGL
117ec681f3Smrg4.5. OpenGL 4.5 is **only** available if requested at context creation
127ec681f3Smrgbecause compatibility contexts are not supported.
137ec681f3Smrg
147ec681f3SmrgSHA256 checksums
157ec681f3Smrg----------------
167ec681f3Smrg
177ec681f3Smrg::
187ec681f3Smrg
197ec681f3Smrg   a9ed76702ffb14ad674ad48899f5c8c7e3a0f987911878a5dfdc4117dce5b415  mesa-17.2.6.tar.gz
207ec681f3Smrg   6ad85224620330be26ab68c8fc78381b12b38b610ade2db8716b38faaa8f30de  mesa-17.2.6.tar.xz
217ec681f3Smrg
227ec681f3SmrgNew features
237ec681f3Smrg------------
247ec681f3Smrg
257ec681f3SmrgNone
267ec681f3Smrg
277ec681f3SmrgBug fixes
287ec681f3Smrg---------
297ec681f3Smrg
307ec681f3Smrg-  `Bug 100438 <https://bugs.freedesktop.org/show_bug.cgi?id=100438>`__
317ec681f3Smrg   - glsl/ir.cpp:1376:
327ec681f3Smrg   ir_dereference_variable::ir_dereference_variable(ir_variable*):
337ec681f3Smrg   Assertion \`var != NULL' failed.
347ec681f3Smrg-  `Bug 102177 <https://bugs.freedesktop.org/show_bug.cgi?id=102177>`__
357ec681f3Smrg   - [SKL] ES31-CTS.core.sepshaderobjs.StateInteraction fails
367ec681f3Smrg   sporadically
377ec681f3Smrg-  `Bug 103115 <https://bugs.freedesktop.org/show_bug.cgi?id=103115>`__
387ec681f3Smrg   - [BSW BXT GLK]
397ec681f3Smrg   dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
407ec681f3Smrg-  `Bug 103519 <https://bugs.freedesktop.org/show_bug.cgi?id=103519>`__
417ec681f3Smrg   - wayland egl apps crash on start with mesa 17.2
427ec681f3Smrg-  `Bug 103529 <https://bugs.freedesktop.org/show_bug.cgi?id=103529>`__
437ec681f3Smrg   - [GM45] GPU hang with mpv fullscreen (bisected)
447ec681f3Smrg-  `Bug 103628 <https://bugs.freedesktop.org/show_bug.cgi?id=103628>`__
457ec681f3Smrg   - [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
467ec681f3Smrg-  `Bug 103787 <https://bugs.freedesktop.org/show_bug.cgi?id=103787>`__
477ec681f3Smrg   - [BDW,BSW] gpu hang on
487ec681f3Smrg   spec.arb_pipeline_statistics_query.arb_pipeline_statistics_query-comp
497ec681f3Smrg
507ec681f3SmrgChanges
517ec681f3Smrg-------
527ec681f3Smrg
537ec681f3SmrgAdam Jackson (2):
547ec681f3Smrg
557ec681f3Smrg-  glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
567ec681f3Smrg-  glx/dri3: Fix passing renderType into glXCreateContext
577ec681f3Smrg
587ec681f3SmrgAlex Smith (2):
597ec681f3Smrg
607ec681f3Smrg-  spirv: Use correct type for sampled images
617ec681f3Smrg-  nir/spirv: tg4 requires a sampler
627ec681f3Smrg
637ec681f3SmrgAndres Gomez (14):
647ec681f3Smrg
657ec681f3Smrg-  docs: add sha256 checksums for 17.2.5
667ec681f3Smrg-  cherry-ignore: intel/fs: Use a pure vertical stride for large
677ec681f3Smrg   register strides
687ec681f3Smrg-  cherry-ignore: intel/nir: Use the correct indirect lowering masks in
697ec681f3Smrg   link_shaders
707ec681f3Smrg-  cherry-ignore: intel/fs: Use the original destination region for int
717ec681f3Smrg   MUL lowering
727ec681f3Smrg-  cherry-ignore: intel/fs: refactors
737ec681f3Smrg-  cherry-ignore: r600/shader: reserve first register of vertex shader.
747ec681f3Smrg-  cherry-ignore: anv/cmd_buffer: Advance the address when initializing
757ec681f3Smrg   clear colors
767ec681f3Smrg-  cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast
777ec681f3Smrg   clear state addresses
787ec681f3Smrg-  cherry-ignore: i965: Mark BOs as external when we export their handle
797ec681f3Smrg-  cherry-ignore: added 17.3 nominations.
807ec681f3Smrg-  cherry-ignore: glsl: Fix typo fragement -> fragment
817ec681f3Smrg-  cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions
827ec681f3Smrg-  cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large
837ec681f3Smrg   register strides"
847ec681f3Smrg-  Update version to 17.2.6
857ec681f3Smrg
867ec681f3SmrgAnuj Phogat (2):
877ec681f3Smrg
887ec681f3Smrg-  i965: Program DWord Length in MI_FLUSH_DW
897ec681f3Smrg-  i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
907ec681f3Smrg
917ec681f3SmrgBas Nieuwenhuizen (2):
927ec681f3Smrg
937ec681f3Smrg-  radv: Free syncobj with multiple imports.
947ec681f3Smrg-  radv: Free temporary syncobj after waiting on it.
957ec681f3Smrg
967ec681f3SmrgDave Airlie (1):
977ec681f3Smrg
987ec681f3Smrg-  r600: fix isoline tess factor component swapping.
997ec681f3Smrg
1007ec681f3SmrgDerek Foreman (1):
1017ec681f3Smrg
1027ec681f3Smrg-  egl/wayland: Add a fallback when fourcc query isn't supported
1037ec681f3Smrg
1047ec681f3SmrgDylan Baker (1):
1057ec681f3Smrg
1067ec681f3Smrg-  autotools: Set C++ visibility flags on Intel
1077ec681f3Smrg
1087ec681f3SmrgEmil Velikov (3):
1097ec681f3Smrg
1107ec681f3Smrg-  targets/opencl: don't hardcode the icd file install to /etc/...
1117ec681f3Smrg-  configure.ac: loosen --enable-glvnd check to honour egl
1127ec681f3Smrg-  configure.ac: require xcb\* for the omx/va/... when using x11
1137ec681f3Smrg   platform
1147ec681f3Smrg
1157ec681f3SmrgGeorge Barrett (1):
1167ec681f3Smrg
1177ec681f3Smrg-  glsl: Catch subscripted calls to undeclared subroutines
1187ec681f3Smrg
1197ec681f3SmrgJason Ekstrand (9):
1207ec681f3Smrg
1217ec681f3Smrg-  intel/fs: Use ANY/ALL32 predicates in SIMD32
1227ec681f3Smrg-  intel/fs: Use an explicit D type for vote any/all/eq intrinsics
1237ec681f3Smrg-  intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
1247ec681f3Smrg-  intel/eu/reg: Add a subscript() helper
1257ec681f3Smrg-  intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
1267ec681f3Smrg-  intel/fs: Fix integer multiplication lowering for src/dst hazards
1277ec681f3Smrg-  intel/fs: Mark 64-bit values as being contiguous
1287ec681f3Smrg-  intel/fs: Rework zero-length URB write handling
1297ec681f3Smrg-  i965: Add stencil buffers to cache set regardless of stencil
1307ec681f3Smrg   texturing
1317ec681f3Smrg
1327ec681f3SmrgKenneth Graunke (5):
1337ec681f3Smrg
1347ec681f3Smrg-  i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
1357ec681f3Smrg-  i965: Make L3 configuration atom listen for TCS/TES program updates.
1367ec681f3Smrg-  intel/tools: Fix detection of enabled shader stages.
1377ec681f3Smrg-  i965: Implement another VF cache invalidate workaround on Gen8+.
1387ec681f3Smrg-  i965: Upload invariant state once at the start of the batch on
1397ec681f3Smrg   Gen4-5.
1407ec681f3Smrg
1417ec681f3SmrgMatt Turner (2):
1427ec681f3Smrg
1437ec681f3Smrg-  i965/fs: Fix extract_i8/u8 to a 64-bit destination
1447ec681f3Smrg-  i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
1457ec681f3Smrg
1467ec681f3SmrgNeil Roberts (1):
1477ec681f3Smrg
1487ec681f3Smrg-  glsl: Transform fb buffers are only active if a variable uses them
1497ec681f3Smrg
1507ec681f3SmrgNicolai Hähnle (1):
1517ec681f3Smrg
1527ec681f3Smrg-  ddebug: fix use-after-free of streamout targets
1537ec681f3Smrg
1547ec681f3SmrgTim Rowley (2):
1557ec681f3Smrg
1567ec681f3Smrg-  swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
1577ec681f3Smrg-  swr/rast: Faster emulated simd16 permute
1587ec681f3Smrg
1597ec681f3SmrgTimothy Arceri (3):
1607ec681f3Smrg
1617ec681f3Smrg-  glsl: drop cache_fallback
1627ec681f3Smrg-  glsl: use the correct parent when allocating program data members
1637ec681f3Smrg-  mesa: rework how we free gl_shader_program_data
164