1ed98bd31Smaya/* 27ec681f3Smrg * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3ed98bd31Smaya * All Rights Reserved. 4ed98bd31Smaya * 5ed98bd31Smaya * Permission is hereby granted, free of charge, to any person obtaining 6ed98bd31Smaya * a copy of this software and associated documentation files (the 7ed98bd31Smaya * "Software"), to deal in the Software without restriction, including 8ed98bd31Smaya * without limitation the rights to use, copy, modify, merge, publish, 9ed98bd31Smaya * distribute, sub license, and/or sell copies of the Software, and to 10ed98bd31Smaya * permit persons to whom the Software is furnished to do so, subject to 11ed98bd31Smaya * the following conditions: 12ed98bd31Smaya * 13ed98bd31Smaya * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14ed98bd31Smaya * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15ed98bd31Smaya * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16ed98bd31Smaya * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17ed98bd31Smaya * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18ed98bd31Smaya * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ed98bd31Smaya * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20ed98bd31Smaya * USE OR OTHER DEALINGS IN THE SOFTWARE. 21ed98bd31Smaya * 22ed98bd31Smaya * The above copyright notice and this permission notice (including the 23ed98bd31Smaya * next paragraph) shall be included in all copies or substantial portions 24ed98bd31Smaya * of the Software. 25ed98bd31Smaya */ 26ed98bd31Smaya 27ed98bd31Smaya/** 28ed98bd31Smaya**************************************************************************************************** 29ed98bd31Smaya* @file addrinterface.h 30ed98bd31Smaya* @brief Contains the addrlib interfaces declaration and parameter defines 31ed98bd31Smaya**************************************************************************************************** 32ed98bd31Smaya*/ 33ed98bd31Smaya#ifndef __ADDR_INTERFACE_H__ 34ed98bd31Smaya#define __ADDR_INTERFACE_H__ 35ed98bd31Smaya 367ec681f3Smrg// Includes should be before extern "C" 37ed98bd31Smaya#include "addrtypes.h" 38ed98bd31Smaya 39ed98bd31Smaya#if defined(__cplusplus) 40ed98bd31Smayaextern "C" 41ed98bd31Smaya{ 42ed98bd31Smaya#endif 43ed98bd31Smaya 44ed98bd31Smaya#define ADDRLIB_VERSION_MAJOR 6 45ed98bd31Smaya#define ADDRLIB_VERSION_MINOR 2 46ed98bd31Smaya#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR) 47ed98bd31Smaya 48ed98bd31Smaya/// Virtually all interface functions need ADDR_HANDLE as first parameter 49ed98bd31Smayatypedef VOID* ADDR_HANDLE; 50ed98bd31Smaya 51ed98bd31Smaya/// Client handle used in callbacks 52ed98bd31Smayatypedef VOID* ADDR_CLIENT_HANDLE; 53ed98bd31Smaya 54ed98bd31Smaya/** 55ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 56ed98bd31Smaya* // Callback functions 57ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 58ed98bd31Smaya* typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 59ed98bd31Smaya* const ADDR_ALLOCSYSMEM_INPUT* pInput); 60ed98bd31Smaya* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 61ed98bd31Smaya* VOID* pVirtAddr); 62ed98bd31Smaya* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 63ed98bd31Smaya* const ADDR_DEBUGPRINT_INPUT* pInput); 64ed98bd31Smaya* 65ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 66ed98bd31Smaya* // Create/Destroy/Config functions 67ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 68ed98bd31Smaya* AddrCreate() 69ed98bd31Smaya* AddrDestroy() 70ed98bd31Smaya* 71ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 72ed98bd31Smaya* // Surface functions 73ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 74ed98bd31Smaya* AddrComputeSurfaceInfo() 75ed98bd31Smaya* AddrComputeSurfaceAddrFromCoord() 76ed98bd31Smaya* AddrComputeSurfaceCoordFromAddr() 77ed98bd31Smaya* 78ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 79ed98bd31Smaya* // HTile functions 80ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 81ed98bd31Smaya* AddrComputeHtileInfo() 82ed98bd31Smaya* AddrComputeHtileAddrFromCoord() 83ed98bd31Smaya* AddrComputeHtileCoordFromAddr() 84ed98bd31Smaya* 85ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 86ed98bd31Smaya* // C-mask functions 87ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 88ed98bd31Smaya* AddrComputeCmaskInfo() 89ed98bd31Smaya* AddrComputeCmaskAddrFromCoord() 90ed98bd31Smaya* AddrComputeCmaskCoordFromAddr() 91ed98bd31Smaya* 92ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 93ed98bd31Smaya* // F-mask functions 94ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 95ed98bd31Smaya* AddrComputeFmaskInfo() 96ed98bd31Smaya* AddrComputeFmaskAddrFromCoord() 97ed98bd31Smaya* AddrComputeFmaskCoordFromAddr() 98ed98bd31Smaya* 99ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 100ed98bd31Smaya* // Element/Utility functions 101ed98bd31Smaya* ///////////////////////////////////////////////////////////////////////////////////////////////// 102ed98bd31Smaya* ElemFlt32ToDepthPixel() 103ed98bd31Smaya* ElemFlt32ToColorPixel() 104ed98bd31Smaya* AddrExtractBankPipeSwizzle() 105ed98bd31Smaya* AddrCombineBankPipeSwizzle() 106ed98bd31Smaya* AddrComputeSliceSwizzle() 107ed98bd31Smaya* AddrConvertTileInfoToHW() 108ed98bd31Smaya* AddrConvertTileIndex() 109ed98bd31Smaya* AddrConvertTileIndex1() 110ed98bd31Smaya* AddrGetTileIndex() 111ed98bd31Smaya* AddrComputeBaseSwizzle() 112ed98bd31Smaya* AddrUseTileIndex() 113ed98bd31Smaya* AddrUseCombinedSwizzle() 114ed98bd31Smaya* 115ed98bd31Smaya**/ 116ed98bd31Smaya 117ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 118ed98bd31Smaya// Callback functions 119ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 120ed98bd31Smaya 121ed98bd31Smaya/** 122ed98bd31Smaya**************************************************************************************************** 123ed98bd31Smaya* @brief channel setting structure 124ed98bd31Smaya**************************************************************************************************** 125ed98bd31Smaya*/ 126ed98bd31Smayatypedef union _ADDR_CHANNEL_SETTING 127ed98bd31Smaya{ 128ed98bd31Smaya struct 129ed98bd31Smaya { 130ed98bd31Smaya UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 131ed98bd31Smaya UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel 132ed98bd31Smaya UINT_8 index : 5; ///< Channel index 133ed98bd31Smaya }; 134ed98bd31Smaya UINT_8 value; ///< Value 135ed98bd31Smaya} ADDR_CHANNEL_SETTING; 136ed98bd31Smaya 137ed98bd31Smaya/** 138ed98bd31Smaya**************************************************************************************************** 139ed98bd31Smaya* @brief address equation key structure 140ed98bd31Smaya**************************************************************************************************** 141ed98bd31Smaya*/ 142ed98bd31Smayatypedef union _ADDR_EQUATION_KEY 143ed98bd31Smaya{ 144ed98bd31Smaya struct 145ed98bd31Smaya { 146ed98bd31Smaya UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 147ed98bd31Smaya UINT_32 tileMode : 5; ///< Tile mode 148ed98bd31Smaya UINT_32 microTileType : 3; ///< Micro tile type 149ed98bd31Smaya UINT_32 pipeConfig : 5; ///< pipe config 150ed98bd31Smaya UINT_32 numBanksLog2 : 3; ///< Number of banks log2 151ed98bd31Smaya UINT_32 bankWidth : 4; ///< Bank width 152ed98bd31Smaya UINT_32 bankHeight : 4; ///< Bank height 153ed98bd31Smaya UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 154ed98bd31Smaya UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 155ed98bd31Smaya UINT_32 reserved : 1; ///< Reserved bit 156ed98bd31Smaya } fields; 157ed98bd31Smaya UINT_32 value; 158ed98bd31Smaya} ADDR_EQUATION_KEY; 159ed98bd31Smaya 160ed98bd31Smaya/** 161ed98bd31Smaya**************************************************************************************************** 162ed98bd31Smaya* @brief address equation structure 163ed98bd31Smaya**************************************************************************************************** 164ed98bd31Smaya*/ 165ed98bd31Smaya#define ADDR_MAX_EQUATION_BIT 20u 166ed98bd31Smaya 167ed98bd31Smaya// Invalid equation index 168ed98bd31Smaya#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 169ed98bd31Smaya 170ed98bd31Smayatypedef struct _ADDR_EQUATION 171ed98bd31Smaya{ 172ed98bd31Smaya ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 173ed98bd31Smaya ///< each bit is result of addr ^ xor ^ xor2 174ed98bd31Smaya ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 175ed98bd31Smaya ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 176ed98bd31Smaya UINT_32 numBits; ///< The number of bits in equation 177ed98bd31Smaya BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 178ed98bd31Smaya ///< stacked vertically prior to swizzling 179ed98bd31Smaya} ADDR_EQUATION; 180ed98bd31Smaya 1817ec681f3Smrg 182ed98bd31Smaya/** 183ed98bd31Smaya**************************************************************************************************** 184ed98bd31Smaya* @brief Alloc system memory flags. 185ed98bd31Smaya* @note These flags are reserved for future use and if flags are added will minimize the impact 186ed98bd31Smaya* of the client. 187ed98bd31Smaya**************************************************************************************************** 188ed98bd31Smaya*/ 189ed98bd31Smayatypedef union _ADDR_ALLOCSYSMEM_FLAGS 190ed98bd31Smaya{ 191ed98bd31Smaya struct 192ed98bd31Smaya { 193ed98bd31Smaya UINT_32 reserved : 32; ///< Reserved for future use. 194ed98bd31Smaya } fields; 195ed98bd31Smaya UINT_32 value; 196ed98bd31Smaya 197ed98bd31Smaya} ADDR_ALLOCSYSMEM_FLAGS; 198ed98bd31Smaya 199ed98bd31Smaya/** 200ed98bd31Smaya**************************************************************************************************** 201ed98bd31Smaya* @brief Alloc system memory input structure 202ed98bd31Smaya**************************************************************************************************** 203ed98bd31Smaya*/ 204ed98bd31Smayatypedef struct _ADDR_ALLOCSYSMEM_INPUT 205ed98bd31Smaya{ 206ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 207ed98bd31Smaya 208ed98bd31Smaya ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 209ed98bd31Smaya UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 210ed98bd31Smaya ADDR_CLIENT_HANDLE hClient; ///< Client handle 211ed98bd31Smaya} ADDR_ALLOCSYSMEM_INPUT; 212ed98bd31Smaya 213ed98bd31Smaya/** 214ed98bd31Smaya**************************************************************************************************** 215ed98bd31Smaya* ADDR_ALLOCSYSMEM 216ed98bd31Smaya* @brief 217ed98bd31Smaya* Allocate system memory callback function. Returns valid pointer on success. 218ed98bd31Smaya**************************************************************************************************** 219ed98bd31Smaya*/ 220ed98bd31Smayatypedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 221ed98bd31Smaya const ADDR_ALLOCSYSMEM_INPUT* pInput); 222ed98bd31Smaya 223ed98bd31Smaya/** 224ed98bd31Smaya**************************************************************************************************** 225ed98bd31Smaya* @brief Free system memory input structure 226ed98bd31Smaya**************************************************************************************************** 227ed98bd31Smaya*/ 228ed98bd31Smayatypedef struct _ADDR_FREESYSMEM_INPUT 229ed98bd31Smaya{ 230ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 231ed98bd31Smaya 232ed98bd31Smaya VOID* pVirtAddr; ///< Virtual address 233ed98bd31Smaya ADDR_CLIENT_HANDLE hClient; ///< Client handle 234ed98bd31Smaya} ADDR_FREESYSMEM_INPUT; 235ed98bd31Smaya 236ed98bd31Smaya/** 237ed98bd31Smaya**************************************************************************************************** 238ed98bd31Smaya* ADDR_FREESYSMEM 239ed98bd31Smaya* @brief 240ed98bd31Smaya* Free system memory callback function. 241ed98bd31Smaya* Returns ADDR_OK on success. 242ed98bd31Smaya**************************************************************************************************** 243ed98bd31Smaya*/ 244ed98bd31Smayatypedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 245ed98bd31Smaya const ADDR_FREESYSMEM_INPUT* pInput); 246ed98bd31Smaya 247ed98bd31Smaya/** 248ed98bd31Smaya**************************************************************************************************** 249ed98bd31Smaya* @brief Print debug message input structure 250ed98bd31Smaya**************************************************************************************************** 251ed98bd31Smaya*/ 252ed98bd31Smayatypedef struct _ADDR_DEBUGPRINT_INPUT 253ed98bd31Smaya{ 254ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 255ed98bd31Smaya 256ed98bd31Smaya CHAR* pDebugString; ///< Debug print string 257ed98bd31Smaya va_list ap; ///< Variable argument list 258ed98bd31Smaya ADDR_CLIENT_HANDLE hClient; ///< Client handle 259ed98bd31Smaya} ADDR_DEBUGPRINT_INPUT; 260ed98bd31Smaya 261ed98bd31Smaya/** 262ed98bd31Smaya**************************************************************************************************** 263ed98bd31Smaya* ADDR_DEBUGPRINT 264ed98bd31Smaya* @brief 265ed98bd31Smaya* Print debug message callback function. 266ed98bd31Smaya* Returns ADDR_OK on success. 267ed98bd31Smaya**************************************************************************************************** 268ed98bd31Smaya*/ 269ed98bd31Smayatypedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 270ed98bd31Smaya const ADDR_DEBUGPRINT_INPUT* pInput); 271ed98bd31Smaya 272ed98bd31Smaya/** 273ed98bd31Smaya**************************************************************************************************** 274ed98bd31Smaya* ADDR_CALLBACKS 275ed98bd31Smaya* 276ed98bd31Smaya* @brief 277ed98bd31Smaya* Address Library needs client to provide system memory alloc/free routines. 278ed98bd31Smaya**************************************************************************************************** 279ed98bd31Smaya*/ 280ed98bd31Smayatypedef struct _ADDR_CALLBACKS 281ed98bd31Smaya{ 282ed98bd31Smaya ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 283ed98bd31Smaya ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 284ed98bd31Smaya ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 285ed98bd31Smaya} ADDR_CALLBACKS; 286ed98bd31Smaya 287ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 288ed98bd31Smaya// Create/Destroy functions 289ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 290ed98bd31Smaya 291ed98bd31Smaya/** 292ed98bd31Smaya**************************************************************************************************** 293ed98bd31Smaya* ADDR_CREATE_FLAGS 294ed98bd31Smaya* 295ed98bd31Smaya* @brief 296ed98bd31Smaya* This structure is used to pass some setup in creation of AddrLib 297ed98bd31Smaya* @note 298ed98bd31Smaya**************************************************************************************************** 299ed98bd31Smaya*/ 300ed98bd31Smayatypedef union _ADDR_CREATE_FLAGS 301ed98bd31Smaya{ 302ed98bd31Smaya struct 303ed98bd31Smaya { 304ed98bd31Smaya UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 305ed98bd31Smaya UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 306ed98bd31Smaya /// output structure 307ed98bd31Smaya UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 308ed98bd31Smaya UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 309ed98bd31Smaya UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 310ed98bd31Smaya UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 311ed98bd31Smaya UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 3127ec681f3Smrg UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 3137ec681f3Smrg UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2 3147ec681f3Smrg UINT_32 enableAltTiling : 1; ///< Enable alt tile mode 3157ec681f3Smrg UINT_32 reserved : 22; ///< Reserved bits for future use 316ed98bd31Smaya }; 317ed98bd31Smaya 318ed98bd31Smaya UINT_32 value; 319ed98bd31Smaya} ADDR_CREATE_FLAGS; 320ed98bd31Smaya 321ed98bd31Smaya/** 322ed98bd31Smaya**************************************************************************************************** 323ed98bd31Smaya* ADDR_REGISTER_VALUE 324ed98bd31Smaya* 325ed98bd31Smaya* @brief 326ed98bd31Smaya* Data from registers to setup AddrLib global data, used in AddrCreate 327ed98bd31Smaya**************************************************************************************************** 328ed98bd31Smaya*/ 329ed98bd31Smayatypedef struct _ADDR_REGISTER_VALUE 330ed98bd31Smaya{ 331ed98bd31Smaya UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 332ed98bd31Smaya /// For R6xx/R7xx, use GB_TILING_CONFIG. 333ed98bd31Smaya /// But they can be treated as the same. 334ed98bd31Smaya /// if this value is 0, use chip to set default value 335ed98bd31Smaya UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 336ed98bd31Smaya /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 337ed98bd31Smaya 338ed98bd31Smaya /// R800 registers----------------------------------------------- 339ed98bd31Smaya UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 340ed98bd31Smaya /// No enums for this value in h/w header files 341ed98bd31Smaya /// 0: 4 342ed98bd31Smaya /// 1: 8 343ed98bd31Smaya /// 2: 16 344ed98bd31Smaya UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 345ed98bd31Smaya /// 0: 1 346ed98bd31Smaya /// 1: 2 347ed98bd31Smaya /// SI (R1000) registers----------------------------------------- 348ed98bd31Smaya const UINT_32* pTileConfig; ///< Global tile setting tables 349ed98bd31Smaya UINT_32 noOfEntries; ///< Number of entries in pTileConfig 350ed98bd31Smaya 351ed98bd31Smaya ///< CI registers------------------------------------------------- 352ed98bd31Smaya const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 353ed98bd31Smaya UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 354ed98bd31Smaya} ADDR_REGISTER_VALUE; 355ed98bd31Smaya 356ed98bd31Smaya/** 357ed98bd31Smaya**************************************************************************************************** 358ed98bd31Smaya* ADDR_CREATE_INPUT 359ed98bd31Smaya* 360ed98bd31Smaya* @brief 361ed98bd31Smaya* Parameters use to create an AddrLib Object. Caller must provide all fields. 362ed98bd31Smaya* 363ed98bd31Smaya**************************************************************************************************** 364ed98bd31Smaya*/ 365ed98bd31Smayatypedef struct _ADDR_CREATE_INPUT 366ed98bd31Smaya{ 367ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 368ed98bd31Smaya 369ed98bd31Smaya UINT_32 chipEngine; ///< Chip Engine 370ed98bd31Smaya UINT_32 chipFamily; ///< Chip Family 371ed98bd31Smaya UINT_32 chipRevision; ///< Chip Revision 372ed98bd31Smaya ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 373ed98bd31Smaya ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 374ed98bd31Smaya ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 375ed98bd31Smaya ADDR_CLIENT_HANDLE hClient; ///< Client handle 376ed98bd31Smaya UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 377ed98bd31Smaya} ADDR_CREATE_INPUT; 378ed98bd31Smaya 379ed98bd31Smaya/** 380ed98bd31Smaya**************************************************************************************************** 381ed98bd31Smaya* ADDR_CREATEINFO_OUTPUT 382ed98bd31Smaya* 383ed98bd31Smaya* @brief 384ed98bd31Smaya* Return AddrLib handle to client driver 385ed98bd31Smaya* 386ed98bd31Smaya**************************************************************************************************** 387ed98bd31Smaya*/ 388ed98bd31Smayatypedef struct _ADDR_CREATE_OUTPUT 389ed98bd31Smaya{ 390ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 391ed98bd31Smaya 392ed98bd31Smaya ADDR_HANDLE hLib; ///< Address lib handle 393ed98bd31Smaya 394ed98bd31Smaya UINT_32 numEquations; ///< Number of equations in the table 395ed98bd31Smaya const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 396ed98bd31Smaya} ADDR_CREATE_OUTPUT; 397ed98bd31Smaya 398ed98bd31Smaya/** 399ed98bd31Smaya**************************************************************************************************** 400ed98bd31Smaya* AddrCreate 401ed98bd31Smaya* 402ed98bd31Smaya* @brief 403ed98bd31Smaya* Create AddrLib object, must be called before any interface calls 404ed98bd31Smaya* 405ed98bd31Smaya* @return 406ed98bd31Smaya* ADDR_OK if successful 407ed98bd31Smaya**************************************************************************************************** 408ed98bd31Smaya*/ 409ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrCreate( 410ed98bd31Smaya const ADDR_CREATE_INPUT* pAddrCreateIn, 411ed98bd31Smaya ADDR_CREATE_OUTPUT* pAddrCreateOut); 412ed98bd31Smaya 4137ec681f3Smrg 4147ec681f3Smrg 415ed98bd31Smaya/** 416ed98bd31Smaya**************************************************************************************************** 417ed98bd31Smaya* AddrDestroy 418ed98bd31Smaya* 419ed98bd31Smaya* @brief 420ed98bd31Smaya* Destroy AddrLib object, must be called to free internally allocated resources. 421ed98bd31Smaya* 422ed98bd31Smaya* @return 423ed98bd31Smaya* ADDR_OK if successful 424ed98bd31Smaya**************************************************************************************************** 425ed98bd31Smaya*/ 426ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrDestroy( 427ed98bd31Smaya ADDR_HANDLE hLib); 428ed98bd31Smaya 4297ec681f3Smrg 4307ec681f3Smrg 431ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 432ed98bd31Smaya// Surface functions 433ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 434ed98bd31Smaya 435ed98bd31Smaya/** 436ed98bd31Smaya**************************************************************************************************** 437ed98bd31Smaya* @brief 438ed98bd31Smaya* Bank/tiling parameters. On function input, these can be set as desired or 439ed98bd31Smaya* left 0 for AddrLib to calculate/default. On function output, these are the actual 440ed98bd31Smaya* parameters used. 441ed98bd31Smaya* @note 442ed98bd31Smaya* Valid bankWidth/bankHeight value: 443ed98bd31Smaya* 1,2,4,8. They are factors instead of pixels or bytes. 444ed98bd31Smaya* 445ed98bd31Smaya* The bank number remains constant across each row of the 446ed98bd31Smaya* macro tile as each pipe is selected, so the number of 447ed98bd31Smaya* tiles in the x direction with the same bank number will 448ed98bd31Smaya* be bank_width * num_pipes. 449ed98bd31Smaya**************************************************************************************************** 450ed98bd31Smaya*/ 451ed98bd31Smayatypedef struct _ADDR_TILEINFO 452ed98bd31Smaya{ 453ed98bd31Smaya /// Any of these parameters can be set to 0 to use the HW default. 454ed98bd31Smaya UINT_32 banks; ///< Number of banks, numerical value 455ed98bd31Smaya UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 456ed98bd31Smaya UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 457ed98bd31Smaya UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 458ed98bd31Smaya UINT_32 tileSplitBytes; ///< Tile split size, in bytes 459ed98bd31Smaya AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 460ed98bd31Smaya} ADDR_TILEINFO; 461ed98bd31Smaya 462ed98bd31Smaya// Create a define to avoid client change. The removal of R800 is because we plan to implement SI 463ed98bd31Smaya// within 800 HWL - An AddrPipeCfg is added in above data structure 464ed98bd31Smayatypedef ADDR_TILEINFO ADDR_R800_TILEINFO; 465ed98bd31Smaya 466ed98bd31Smaya/** 467ed98bd31Smaya**************************************************************************************************** 468ed98bd31Smaya* @brief 469ed98bd31Smaya* Information needed by quad buffer stereo support 470ed98bd31Smaya**************************************************************************************************** 471ed98bd31Smaya*/ 472ed98bd31Smayatypedef struct _ADDR_QBSTEREOINFO 473ed98bd31Smaya{ 474ed98bd31Smaya UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 475ed98bd31Smaya UINT_32 rightOffset; ///< Offset (in bytes) to right eye 476ed98bd31Smaya UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 477ed98bd31Smaya} ADDR_QBSTEREOINFO; 478ed98bd31Smaya 479ed98bd31Smaya/** 480ed98bd31Smaya**************************************************************************************************** 481ed98bd31Smaya* ADDR_SURFACE_FLAGS 482ed98bd31Smaya* 483ed98bd31Smaya* @brief 484ed98bd31Smaya* Surface flags 485ed98bd31Smaya**************************************************************************************************** 486ed98bd31Smaya*/ 487ed98bd31Smayatypedef union _ADDR_SURFACE_FLAGS 488ed98bd31Smaya{ 489ed98bd31Smaya struct 490ed98bd31Smaya { 491ed98bd31Smaya UINT_32 color : 1; ///< Flag indicates this is a color buffer 492ed98bd31Smaya UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 493ed98bd31Smaya UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 494ed98bd31Smaya UINT_32 texture : 1; ///< Flag indicates this is a texture 495ed98bd31Smaya UINT_32 cube : 1; ///< Flag indicates this is a cubemap 496ed98bd31Smaya UINT_32 volume : 1; ///< Flag indicates this is a volume texture 497ed98bd31Smaya UINT_32 fmask : 1; ///< Flag indicates this is an fmask 498ed98bd31Smaya UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 499ed98bd31Smaya UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 500ed98bd31Smaya UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 501ed98bd31Smaya UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 502ed98bd31Smaya UINT_32 display : 1; ///< Flag indicates this should match display controller req. 503ed98bd31Smaya UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 504ed98bd31Smaya /// i.e. save some memory but may lose performance 505ed98bd31Smaya UINT_32 prt : 1; ///< Flag for partially resident texture 506ed98bd31Smaya UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 507ed98bd31Smaya UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 508ed98bd31Smaya UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 509ed98bd31Smaya UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 510ed98bd31Smaya UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 511ed98bd31Smaya UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 512ed98bd31Smaya UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 513ed98bd31Smaya /// dcc can't be enabled if pipe config of tile mode 514ed98bd31Smaya /// is different from that of ASIC, this flag 515ed98bd31Smaya /// is address lib internal flag, client should ignore it 516ed98bd31Smaya UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 517ed98bd31Smaya /// This flag indicates we need to follow the 518ed98bd31Smaya /// alignment with CZ families or other ASICs under 519ed98bd31Smaya /// PX configuration + CZ. 520ed98bd31Smaya UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 521ed98bd31Smaya UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 522ed98bd31Smaya UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 523ed98bd31Smaya /// This flag indicates we need to override tile 524ed98bd31Smaya /// mode to PRT_* tile mode to disable slice rotation, 525ed98bd31Smaya /// which is needed by swizzle pattern equation. 526ed98bd31Smaya UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 527ed98bd31Smaya UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 528ed98bd31Smaya UINT_32 minimizeAlignment : 1; ///< Minimize alignment 529ed98bd31Smaya UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 530ed98bd31Smaya UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 531ed98bd31Smaya /// to make sure they share same tile config parameters 532ed98bd31Smaya UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 533ed98bd31Smaya UINT_32 reserved : 1; ///< Reserved bits 534ed98bd31Smaya }; 535ed98bd31Smaya 536ed98bd31Smaya UINT_32 value; 537ed98bd31Smaya} ADDR_SURFACE_FLAGS; 538ed98bd31Smaya 539ed98bd31Smaya/** 540ed98bd31Smaya**************************************************************************************************** 541ed98bd31Smaya* ADDR_COMPUTE_SURFACE_INFO_INPUT 542ed98bd31Smaya* 543ed98bd31Smaya* @brief 544ed98bd31Smaya* Input structure for AddrComputeSurfaceInfo 545ed98bd31Smaya**************************************************************************************************** 546ed98bd31Smaya*/ 547ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 548ed98bd31Smaya{ 549ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 550ed98bd31Smaya 551ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 552ed98bd31Smaya AddrFormat format; ///< If format is set to valid one, bpp/width/height 553ed98bd31Smaya /// might be overwritten 554ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 555ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 556ed98bd31Smaya UINT_32 width; ///< Width, in pixels 557ed98bd31Smaya UINT_32 height; ///< Height, in pixels 558ed98bd31Smaya UINT_32 numSlices; ///< Number of surface slices or depth 559ed98bd31Smaya UINT_32 slice; ///< Slice index 560ed98bd31Smaya UINT_32 mipLevel; ///< Current mipmap level 561ed98bd31Smaya UINT_32 numMipLevels; ///< Number of mips in mip chain 562ed98bd31Smaya ADDR_SURFACE_FLAGS flags; ///< Surface type flags 563ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 564ed98bd31Smaya /// number of samples for normal AA; Set it to the 565ed98bd31Smaya /// number of fragments for EQAA 566ed98bd31Smaya /// r800 and later HWL parameters 567ed98bd31Smaya // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 568ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 569ed98bd31Smaya AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 570ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 571ed98bd31Smaya /// while the global useTileIndex is set to 1 572ed98bd31Smaya UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 573ed98bd31Smaya /// must for mip levels from SI+. 574ed98bd31Smaya /// Don't use pitch in blocks for compressed formats! 575ed98bd31Smaya UINT_32 maxBaseAlign; ///< Max base alignment request from client 576ed98bd31Smaya UINT_32 pitchAlign; ///< Pitch alignment request from client 577ed98bd31Smaya UINT_32 heightAlign; ///< Height alignment request from client 578ed98bd31Smaya} ADDR_COMPUTE_SURFACE_INFO_INPUT; 579ed98bd31Smaya 580ed98bd31Smaya/** 581ed98bd31Smaya**************************************************************************************************** 582ed98bd31Smaya* ADDR_COMPUTE_SURFACE_INFO_OUTPUT 583ed98bd31Smaya* 584ed98bd31Smaya* @brief 585ed98bd31Smaya* Output structure for AddrComputeSurfInfo 586ed98bd31Smaya* @note 587ed98bd31Smaya Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 588ed98bd31Smaya Pixel: Original pixel 589ed98bd31Smaya**************************************************************************************************** 590ed98bd31Smaya*/ 591ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 592ed98bd31Smaya{ 593ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 594ed98bd31Smaya 595ed98bd31Smaya UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 596ed98bd31Smaya UINT_32 height; ///< Height in elements (in blocks for compressed formats) 597ed98bd31Smaya UINT_32 depth; ///< Number of slice/depth 598ed98bd31Smaya UINT_64 surfSize; ///< Surface size in bytes 599ed98bd31Smaya AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 600ed98bd31Smaya UINT_32 baseAlign; ///< Base address alignment 601ed98bd31Smaya UINT_32 pitchAlign; ///< Pitch alignment, in elements 602ed98bd31Smaya UINT_32 heightAlign; ///< Height alignment, in elements 603ed98bd31Smaya UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 604ed98bd31Smaya UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 605ed98bd31Smaya UINT_32 pixelPitch; ///< Pitch in original pixels 606ed98bd31Smaya UINT_32 pixelHeight; ///< Height in original pixels 607ed98bd31Smaya UINT_32 pixelBits; ///< Original bits per pixel, passed from input 608ed98bd31Smaya UINT_64 sliceSize; ///< Size of slice specified by input's slice 609ed98bd31Smaya /// The result is controlled by surface flags & createFlags 610ed98bd31Smaya /// By default this value equals to surfSize for volume 611ed98bd31Smaya UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 612ed98bd31Smaya UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 613ed98bd31Smaya UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 614ed98bd31Smaya 615ed98bd31Smaya UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 616ed98bd31Smaya 617ed98bd31Smaya /// r800 and later HWL parameters 618ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 619ed98bd31Smaya AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 620ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 621ed98bd31Smaya 622ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 623ed98bd31Smaya /// Output flags 624ed98bd31Smaya struct 625ed98bd31Smaya { 626ed98bd31Smaya /// Special information to work around SI mipmap swizzle bug UBTS #317508 627ed98bd31Smaya UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 628ed98bd31Smaya ///< Only meaningful when create flag checkLast2DLevel is set 629ed98bd31Smaya UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 630ed98bd31Smaya UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 631ed98bd31Smaya UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 632ed98bd31Smaya ///< If address lib return true for mip 0, client should set prt flag 633ed98bd31Smaya ///< for child mips in subsequent compute surface info calls 634ed98bd31Smaya UINT_32 reserved :28; ///< Reserved bits 635ed98bd31Smaya }; 636ed98bd31Smaya 637ed98bd31Smaya UINT_32 equationIndex; ///< Equation index in the equation table; 638ed98bd31Smaya 639ed98bd31Smaya UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 640ed98bd31Smaya UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 641ed98bd31Smaya UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 642ed98bd31Smaya 643ed98bd31Smaya /// Stereo info 644ed98bd31Smaya ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 645ed98bd31Smaya 646ed98bd31Smaya INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 647ed98bd31Smaya} ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 648ed98bd31Smaya 649ed98bd31Smaya/** 650ed98bd31Smaya**************************************************************************************************** 651ed98bd31Smaya* AddrComputeSurfaceInfo 652ed98bd31Smaya* 653ed98bd31Smaya* @brief 654ed98bd31Smaya* Compute surface width/height/depth/alignments and suitable tiling mode 655ed98bd31Smaya**************************************************************************************************** 656ed98bd31Smaya*/ 657ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 658ed98bd31Smaya ADDR_HANDLE hLib, 659ed98bd31Smaya const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 660ed98bd31Smaya ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 661ed98bd31Smaya 6627ec681f3Smrg 6637ec681f3Smrg 664ed98bd31Smaya/** 665ed98bd31Smaya**************************************************************************************************** 666ed98bd31Smaya* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 667ed98bd31Smaya* 668ed98bd31Smaya* @brief 669ed98bd31Smaya* Input structure for AddrComputeSurfaceAddrFromCoord 670ed98bd31Smaya**************************************************************************************************** 671ed98bd31Smaya*/ 672ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 673ed98bd31Smaya{ 674ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 675ed98bd31Smaya 676ed98bd31Smaya UINT_32 x; ///< X coordinate 677ed98bd31Smaya UINT_32 y; ///< Y coordinate 678ed98bd31Smaya UINT_32 slice; ///< Slice index 679ed98bd31Smaya UINT_32 sample; ///< Sample index, use fragment index for EQAA 680ed98bd31Smaya 681ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 682ed98bd31Smaya UINT_32 pitch; ///< Surface pitch, in pixels 683ed98bd31Smaya UINT_32 height; ///< Surface height, in pixels 684ed98bd31Smaya UINT_32 numSlices; ///< Surface depth 685ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 686ed98bd31Smaya 687ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 688ed98bd31Smaya BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 689ed98bd31Smaya /// micro tile. Textures can also choose depth sample order 690ed98bd31Smaya UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 691ed98bd31Smaya /// the case that components are stored separately 692ed98bd31Smaya UINT_32 compBits; ///< The component bits actually needed(for planar surface) 693ed98bd31Smaya 694ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 695ed98bd31Smaya /// number of samples for normal AA; Set it to the 696ed98bd31Smaya /// number of fragments for EQAA 697ed98bd31Smaya /// r800 and later HWL parameters 698ed98bd31Smaya // Used for 1D tiling above 699ed98bd31Smaya AddrTileType tileType; ///< See defintion of AddrTileType 700ed98bd31Smaya struct 701ed98bd31Smaya { 702ed98bd31Smaya UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 703ed98bd31Smaya /// only flag. Only non-RT texture can set this to TRUE 704ed98bd31Smaya UINT_32 reserved :31; ///< Reserved for future use. 705ed98bd31Smaya }; 706ed98bd31Smaya // 2D tiling needs following structure 707ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 708ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 709ed98bd31Smaya /// while the global useTileIndex is set to 1 710ed98bd31Smaya union 711ed98bd31Smaya { 712ed98bd31Smaya struct 713ed98bd31Smaya { 714ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 715ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 716ed98bd31Smaya }; 717ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 718ed98bd31Smaya }; 719ed98bd31Smaya} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 720ed98bd31Smaya 721ed98bd31Smaya/** 722ed98bd31Smaya**************************************************************************************************** 723ed98bd31Smaya* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 724ed98bd31Smaya* 725ed98bd31Smaya* @brief 726ed98bd31Smaya* Output structure for AddrComputeSurfaceAddrFromCoord 727ed98bd31Smaya**************************************************************************************************** 728ed98bd31Smaya*/ 729ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 730ed98bd31Smaya{ 731ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 732ed98bd31Smaya 733ed98bd31Smaya UINT_64 addr; ///< Byte address 734ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 735ed98bd31Smaya /// For surface bpp < 8, e.g. FMT_1. 736ed98bd31Smaya UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 737ed98bd31Smaya} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 738ed98bd31Smaya 739ed98bd31Smaya/** 740ed98bd31Smaya**************************************************************************************************** 741ed98bd31Smaya* AddrComputeSurfaceAddrFromCoord 742ed98bd31Smaya* 743ed98bd31Smaya* @brief 744ed98bd31Smaya* Compute surface address from a given coordinate. 745ed98bd31Smaya**************************************************************************************************** 746ed98bd31Smaya*/ 747ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 748ed98bd31Smaya ADDR_HANDLE hLib, 749ed98bd31Smaya const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 750ed98bd31Smaya ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 751ed98bd31Smaya 7527ec681f3Smrg 7537ec681f3Smrg 754ed98bd31Smaya/** 755ed98bd31Smaya**************************************************************************************************** 756ed98bd31Smaya* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 757ed98bd31Smaya* 758ed98bd31Smaya* @brief 759ed98bd31Smaya* Input structure for AddrComputeSurfaceCoordFromAddr 760ed98bd31Smaya**************************************************************************************************** 761ed98bd31Smaya*/ 762ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 763ed98bd31Smaya{ 764ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 765ed98bd31Smaya 766ed98bd31Smaya UINT_64 addr; ///< Address in bytes 767ed98bd31Smaya UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 768ed98bd31Smaya /// e.g. FMT_1; 769ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 770ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels 771ed98bd31Smaya UINT_32 height; ///< Height in pixels 772ed98bd31Smaya UINT_32 numSlices; ///< Surface depth 773ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 774ed98bd31Smaya 775ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 776ed98bd31Smaya BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 777ed98bd31Smaya /// Note: Textures can choose depth sample order as well. 778ed98bd31Smaya UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 779ed98bd31Smaya /// the case that components are stored separately 780ed98bd31Smaya UINT_32 compBits; ///< The component bits actually needed(for planar surface) 781ed98bd31Smaya 782ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 783ed98bd31Smaya /// number of samples for normal AA; Set it to the 784ed98bd31Smaya /// number of fragments for EQAA 785ed98bd31Smaya /// r800 and later HWL parameters 786ed98bd31Smaya // Used for 1D tiling above 787ed98bd31Smaya AddrTileType tileType; ///< See defintion of AddrTileType 788ed98bd31Smaya struct 789ed98bd31Smaya { 790ed98bd31Smaya UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 791ed98bd31Smaya /// only flag. Only non-RT texture can set this to TRUE 792ed98bd31Smaya UINT_32 reserved :31; ///< Reserved for future use. 793ed98bd31Smaya }; 794ed98bd31Smaya // 2D tiling needs following structure 795ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 796ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 797ed98bd31Smaya /// while the global useTileIndex is set to 1 798ed98bd31Smaya union 799ed98bd31Smaya { 800ed98bd31Smaya struct 801ed98bd31Smaya { 802ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 803ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 804ed98bd31Smaya }; 805ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 806ed98bd31Smaya }; 807ed98bd31Smaya} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 808ed98bd31Smaya 809ed98bd31Smaya/** 810ed98bd31Smaya**************************************************************************************************** 811ed98bd31Smaya* ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 812ed98bd31Smaya* 813ed98bd31Smaya* @brief 814ed98bd31Smaya* Output structure for AddrComputeSurfaceCoordFromAddr 815ed98bd31Smaya**************************************************************************************************** 816ed98bd31Smaya*/ 817ed98bd31Smayatypedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 818ed98bd31Smaya{ 819ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 820ed98bd31Smaya 821ed98bd31Smaya UINT_32 x; ///< X coordinate 822ed98bd31Smaya UINT_32 y; ///< Y coordinate 823ed98bd31Smaya UINT_32 slice; ///< Index of slices 824ed98bd31Smaya UINT_32 sample; ///< Index of samples, means fragment index for EQAA 825ed98bd31Smaya} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 826ed98bd31Smaya 827ed98bd31Smaya/** 828ed98bd31Smaya**************************************************************************************************** 829ed98bd31Smaya* AddrComputeSurfaceCoordFromAddr 830ed98bd31Smaya* 831ed98bd31Smaya* @brief 832ed98bd31Smaya* Compute coordinate from a given surface address 833ed98bd31Smaya**************************************************************************************************** 834ed98bd31Smaya*/ 835ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 836ed98bd31Smaya ADDR_HANDLE hLib, 837ed98bd31Smaya const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 838ed98bd31Smaya ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 839ed98bd31Smaya 840ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 841ed98bd31Smaya// HTile functions 842ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 843ed98bd31Smaya 844ed98bd31Smaya/** 845ed98bd31Smaya**************************************************************************************************** 846ed98bd31Smaya* ADDR_HTILE_FLAGS 847ed98bd31Smaya* 848ed98bd31Smaya* @brief 849ed98bd31Smaya* HTILE flags 850ed98bd31Smaya**************************************************************************************************** 851ed98bd31Smaya*/ 852ed98bd31Smayatypedef union _ADDR_HTILE_FLAGS 853ed98bd31Smaya{ 854ed98bd31Smaya struct 855ed98bd31Smaya { 856ed98bd31Smaya UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 857ed98bd31Smaya UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 858ed98bd31Smaya /// size to 256xBankxPipe when computing tc-compatible 859ed98bd31Smaya /// htile info. 860ed98bd31Smaya UINT_32 reserved : 30; ///< Reserved bits 861ed98bd31Smaya }; 862ed98bd31Smaya 863ed98bd31Smaya UINT_32 value; 864ed98bd31Smaya} ADDR_HTILE_FLAGS; 865ed98bd31Smaya 866ed98bd31Smaya/** 867ed98bd31Smaya**************************************************************************************************** 868ed98bd31Smaya* ADDR_COMPUTE_HTILE_INFO_INPUT 869ed98bd31Smaya* 870ed98bd31Smaya* @brief 871ed98bd31Smaya* Input structure of AddrComputeHtileInfo 872ed98bd31Smaya**************************************************************************************************** 873ed98bd31Smaya*/ 874ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 875ed98bd31Smaya{ 876ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 877ed98bd31Smaya 878ed98bd31Smaya ADDR_HTILE_FLAGS flags; ///< HTILE flags 879ed98bd31Smaya UINT_32 pitch; ///< Surface pitch, in pixels 880ed98bd31Smaya UINT_32 height; ///< Surface height, in pixels 881ed98bd31Smaya UINT_32 numSlices; ///< Number of slices 882ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled HTILE layout 883ed98bd31Smaya AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 884ed98bd31Smaya AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 885ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 886ed98bd31Smaya 887ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 888ed98bd31Smaya /// while the global useTileIndex is set to 1 889ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 890ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 891ed98bd31Smaya} ADDR_COMPUTE_HTILE_INFO_INPUT; 892ed98bd31Smaya 893ed98bd31Smaya/** 894ed98bd31Smaya**************************************************************************************************** 895ed98bd31Smaya* ADDR_COMPUTE_HTILE_INFO_OUTPUT 896ed98bd31Smaya* 897ed98bd31Smaya* @brief 898ed98bd31Smaya* Output structure of AddrComputeHtileInfo 899ed98bd31Smaya**************************************************************************************************** 900ed98bd31Smaya*/ 901ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 902ed98bd31Smaya{ 903ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 904ed98bd31Smaya 905ed98bd31Smaya UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 906ed98bd31Smaya /// HTile buffer. This might be larger than original depth 907ed98bd31Smaya /// buffer pitch when called with an unaligned pitch. 908ed98bd31Smaya UINT_32 height; ///< Height in pixels, as above 909ed98bd31Smaya UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 910ed98bd31Smaya UINT_32 baseAlign; ///< Base alignment 911ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 912ed98bd31Smaya UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 913ed98bd31Smaya UINT_32 macroHeight; ///< Macro height in pixels 914ed98bd31Smaya UINT_64 sliceSize; ///< Slice size, in bytes. 915ed98bd31Smaya BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 916ed98bd31Smaya /// Compute engine clear can't be used if htile is interleaved 917ed98bd31Smaya BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 918ed98bd31Smaya /// next mip level, it also indicates if memory set based 919ed98bd31Smaya /// fast clear can be used for current mip level. 920ed98bd31Smaya} ADDR_COMPUTE_HTILE_INFO_OUTPUT; 921ed98bd31Smaya 922ed98bd31Smaya/** 923ed98bd31Smaya**************************************************************************************************** 924ed98bd31Smaya* AddrComputeHtileInfo 925ed98bd31Smaya* 926ed98bd31Smaya* @brief 927ed98bd31Smaya* Compute Htile pitch, height, base alignment and size in bytes 928ed98bd31Smaya**************************************************************************************************** 929ed98bd31Smaya*/ 930ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 931ed98bd31Smaya ADDR_HANDLE hLib, 932ed98bd31Smaya const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 933ed98bd31Smaya ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 934ed98bd31Smaya 9357ec681f3Smrg 9367ec681f3Smrg 937ed98bd31Smaya/** 938ed98bd31Smaya**************************************************************************************************** 939ed98bd31Smaya* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 940ed98bd31Smaya* 941ed98bd31Smaya* @brief 942ed98bd31Smaya* Input structure for AddrComputeHtileAddrFromCoord 943ed98bd31Smaya**************************************************************************************************** 944ed98bd31Smaya*/ 945ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 946ed98bd31Smaya{ 947ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 948ed98bd31Smaya 949ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels 950ed98bd31Smaya UINT_32 height; ///< Height in pixels 951ed98bd31Smaya UINT_32 x; ///< X coordinate 952ed98bd31Smaya UINT_32 y; ///< Y coordinate 953ed98bd31Smaya UINT_32 slice; ///< Index of slice 954ed98bd31Smaya UINT_32 numSlices; ///< Number of slices 955ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled HTILE layout 956ed98bd31Smaya ADDR_HTILE_FLAGS flags; ///< htile flags 957ed98bd31Smaya AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 958ed98bd31Smaya AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 959ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 960ed98bd31Smaya 961ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 962ed98bd31Smaya /// while the global useTileIndex is set to 1 963ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 964ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 965ed98bd31Smaya UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 966ed98bd31Smaya UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 967ed98bd31Smaya} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 968ed98bd31Smaya 969ed98bd31Smaya/** 970ed98bd31Smaya**************************************************************************************************** 971ed98bd31Smaya* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 972ed98bd31Smaya* 973ed98bd31Smaya* @brief 974ed98bd31Smaya* Output structure for AddrComputeHtileAddrFromCoord 975ed98bd31Smaya**************************************************************************************************** 976ed98bd31Smaya*/ 977ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 978ed98bd31Smaya{ 979ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 980ed98bd31Smaya 981ed98bd31Smaya UINT_64 addr; ///< Address in bytes 982ed98bd31Smaya UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 983ed98bd31Smaya /// So we keep bitPosition for HTILE as well 984ed98bd31Smaya} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 985ed98bd31Smaya 986ed98bd31Smaya/** 987ed98bd31Smaya**************************************************************************************************** 988ed98bd31Smaya* AddrComputeHtileAddrFromCoord 989ed98bd31Smaya* 990ed98bd31Smaya* @brief 991ed98bd31Smaya* Compute Htile address according to coordinates (of depth buffer) 992ed98bd31Smaya**************************************************************************************************** 993ed98bd31Smaya*/ 994ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 995ed98bd31Smaya ADDR_HANDLE hLib, 996ed98bd31Smaya const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 997ed98bd31Smaya ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 998ed98bd31Smaya 9997ec681f3Smrg 10007ec681f3Smrg 1001ed98bd31Smaya/** 1002ed98bd31Smaya**************************************************************************************************** 1003ed98bd31Smaya* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1004ed98bd31Smaya* 1005ed98bd31Smaya* @brief 1006ed98bd31Smaya* Input structure for AddrComputeHtileCoordFromAddr 1007ed98bd31Smaya**************************************************************************************************** 1008ed98bd31Smaya*/ 1009ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1010ed98bd31Smaya{ 1011ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1012ed98bd31Smaya 1013ed98bd31Smaya UINT_64 addr; ///< Address 1014ed98bd31Smaya UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1015ed98bd31Smaya /// so we keep bitPosition for HTILE as well 1016ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels 1017ed98bd31Smaya UINT_32 height; ///< Height, in pixels 1018ed98bd31Smaya UINT_32 numSlices; ///< Number of slices 1019ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1020ed98bd31Smaya AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1021ed98bd31Smaya AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1022ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 1023ed98bd31Smaya 1024ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1025ed98bd31Smaya /// while the global useTileIndex is set to 1 1026ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1027ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1028ed98bd31Smaya} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1029ed98bd31Smaya 1030ed98bd31Smaya/** 1031ed98bd31Smaya**************************************************************************************************** 1032ed98bd31Smaya* ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1033ed98bd31Smaya* 1034ed98bd31Smaya* @brief 1035ed98bd31Smaya* Output structure for AddrComputeHtileCoordFromAddr 1036ed98bd31Smaya**************************************************************************************************** 1037ed98bd31Smaya*/ 1038ed98bd31Smayatypedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1039ed98bd31Smaya{ 1040ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1041ed98bd31Smaya 1042ed98bd31Smaya UINT_32 x; ///< X coordinate 1043ed98bd31Smaya UINT_32 y; ///< Y coordinate 1044ed98bd31Smaya UINT_32 slice; ///< Slice index 1045ed98bd31Smaya} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1046ed98bd31Smaya 1047ed98bd31Smaya/** 1048ed98bd31Smaya**************************************************************************************************** 1049ed98bd31Smaya* AddrComputeHtileCoordFromAddr 1050ed98bd31Smaya* 1051ed98bd31Smaya* @brief 1052ed98bd31Smaya* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1053ed98bd31Smaya* Htile address 1054ed98bd31Smaya**************************************************************************************************** 1055ed98bd31Smaya*/ 1056ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1057ed98bd31Smaya ADDR_HANDLE hLib, 1058ed98bd31Smaya const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1059ed98bd31Smaya ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1060ed98bd31Smaya 10617ec681f3Smrg 10627ec681f3Smrg 1063ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1064ed98bd31Smaya// C-mask functions 1065ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1066ed98bd31Smaya 1067ed98bd31Smaya/** 1068ed98bd31Smaya**************************************************************************************************** 1069ed98bd31Smaya* ADDR_CMASK_FLAGS 1070ed98bd31Smaya* 1071ed98bd31Smaya* @brief 1072ed98bd31Smaya* CMASK flags 1073ed98bd31Smaya**************************************************************************************************** 1074ed98bd31Smaya*/ 1075ed98bd31Smayatypedef union _ADDR_CMASK_FLAGS 1076ed98bd31Smaya{ 1077ed98bd31Smaya struct 1078ed98bd31Smaya { 1079ed98bd31Smaya UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1080ed98bd31Smaya UINT_32 reserved :31; ///< Reserved bits 1081ed98bd31Smaya }; 1082ed98bd31Smaya 1083ed98bd31Smaya UINT_32 value; 1084ed98bd31Smaya} ADDR_CMASK_FLAGS; 1085ed98bd31Smaya 1086ed98bd31Smaya/** 1087ed98bd31Smaya**************************************************************************************************** 1088ed98bd31Smaya* ADDR_COMPUTE_CMASK_INFO_INPUT 1089ed98bd31Smaya* 1090ed98bd31Smaya* @brief 1091ed98bd31Smaya* Input structure of AddrComputeCmaskInfo 1092ed98bd31Smaya**************************************************************************************************** 1093ed98bd31Smaya*/ 1094ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1095ed98bd31Smaya{ 1096ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1097ed98bd31Smaya 1098ed98bd31Smaya ADDR_CMASK_FLAGS flags; ///< CMASK flags 1099ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1100ed98bd31Smaya UINT_32 height; ///< Height, in pixels, of color buffer 1101ed98bd31Smaya UINT_32 numSlices; ///< Number of slices, of color buffer 1102ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1103ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 1104ed98bd31Smaya 1105ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1106ed98bd31Smaya /// while the global useTileIndex is set to 1 1107ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1108ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1109ed98bd31Smaya} ADDR_COMPUTE_CMASK_INFO_INPUT; 1110ed98bd31Smaya 1111ed98bd31Smaya/** 1112ed98bd31Smaya**************************************************************************************************** 1113ed98bd31Smaya* ADDR_COMPUTE_CMASK_INFO_OUTPUT 1114ed98bd31Smaya* 1115ed98bd31Smaya* @brief 1116ed98bd31Smaya* Output structure of AddrComputeCmaskInfo 1117ed98bd31Smaya**************************************************************************************************** 1118ed98bd31Smaya*/ 1119ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1120ed98bd31Smaya{ 1121ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1122ed98bd31Smaya 1123ed98bd31Smaya UINT_32 pitch; ///< Pitch in pixels of color buffer which 1124ed98bd31Smaya /// this Cmask matches. The size might be larger than 1125ed98bd31Smaya /// original color buffer pitch when called with 1126ed98bd31Smaya /// an unaligned pitch. 1127ed98bd31Smaya UINT_32 height; ///< Height in pixels, as above 1128ed98bd31Smaya UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1129ed98bd31Smaya UINT_32 baseAlign; ///< Base alignment 1130ed98bd31Smaya UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1131ed98bd31Smaya UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1132ed98bd31Smaya UINT_32 macroHeight; ///< Macro height in pixels 1133ed98bd31Smaya UINT_64 sliceSize; ///< Slice size, in bytes. 1134ed98bd31Smaya} ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1135ed98bd31Smaya 1136ed98bd31Smaya/** 1137ed98bd31Smaya**************************************************************************************************** 1138ed98bd31Smaya* AddrComputeCmaskInfo 1139ed98bd31Smaya* 1140ed98bd31Smaya* @brief 1141ed98bd31Smaya* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1142ed98bd31Smaya* info 1143ed98bd31Smaya**************************************************************************************************** 1144ed98bd31Smaya*/ 1145ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1146ed98bd31Smaya ADDR_HANDLE hLib, 1147ed98bd31Smaya const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1148ed98bd31Smaya ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1149ed98bd31Smaya 11507ec681f3Smrg 11517ec681f3Smrg 1152ed98bd31Smaya/** 1153ed98bd31Smaya**************************************************************************************************** 1154ed98bd31Smaya* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1155ed98bd31Smaya* 1156ed98bd31Smaya* @brief 1157ed98bd31Smaya* Input structure for AddrComputeCmaskAddrFromCoord 1158ed98bd31Smaya* 1159ed98bd31Smaya**************************************************************************************************** 1160ed98bd31Smaya*/ 1161ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1162ed98bd31Smaya{ 1163ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1164ed98bd31Smaya UINT_32 x; ///< X coordinate 1165ed98bd31Smaya UINT_32 y; ///< Y coordinate 1166ed98bd31Smaya UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1167ed98bd31Smaya UINT_32 slice; ///< Slice index 1168ed98bd31Smaya UINT_32 pitch; ///< Pitch in pixels, of color buffer 1169ed98bd31Smaya UINT_32 height; ///< Height in pixels, of color buffer 1170ed98bd31Smaya UINT_32 numSlices; ///< Number of slices 1171ed98bd31Smaya UINT_32 bpp; 1172ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1173ed98bd31Smaya ADDR_CMASK_FLAGS flags; ///< CMASK flags 1174ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 1175ed98bd31Smaya 1176ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1177ed98bd31Smaya ///< while the global useTileIndex is set to 1 1178ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1179ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1180ed98bd31Smaya} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1181ed98bd31Smaya 1182ed98bd31Smaya/** 1183ed98bd31Smaya**************************************************************************************************** 1184ed98bd31Smaya* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1185ed98bd31Smaya* 1186ed98bd31Smaya* @brief 1187ed98bd31Smaya* Output structure for AddrComputeCmaskAddrFromCoord 1188ed98bd31Smaya**************************************************************************************************** 1189ed98bd31Smaya*/ 1190ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1191ed98bd31Smaya{ 1192ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1193ed98bd31Smaya 1194ed98bd31Smaya UINT_64 addr; ///< CMASK address in bytes 1195ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1196ed98bd31Smaya /// so the address may be located in bit 0 (0) or 4 (4) 1197ed98bd31Smaya} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1198ed98bd31Smaya 1199ed98bd31Smaya/** 1200ed98bd31Smaya**************************************************************************************************** 1201ed98bd31Smaya* AddrComputeCmaskAddrFromCoord 1202ed98bd31Smaya* 1203ed98bd31Smaya* @brief 1204ed98bd31Smaya* Compute Cmask address according to coordinates (of MSAA color buffer) 1205ed98bd31Smaya**************************************************************************************************** 1206ed98bd31Smaya*/ 1207ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1208ed98bd31Smaya ADDR_HANDLE hLib, 1209ed98bd31Smaya const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1210ed98bd31Smaya ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1211ed98bd31Smaya 12127ec681f3Smrg 12137ec681f3Smrg 1214ed98bd31Smaya/** 1215ed98bd31Smaya**************************************************************************************************** 1216ed98bd31Smaya* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1217ed98bd31Smaya* 1218ed98bd31Smaya* @brief 1219ed98bd31Smaya* Input structure for AddrComputeCmaskCoordFromAddr 1220ed98bd31Smaya**************************************************************************************************** 1221ed98bd31Smaya*/ 1222ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1223ed98bd31Smaya{ 1224ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1225ed98bd31Smaya 1226ed98bd31Smaya UINT_64 addr; ///< CMASK address in bytes 1227ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1228ed98bd31Smaya /// so the address may be located in bit 0 (0) or 4 (4) 1229ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels 1230ed98bd31Smaya UINT_32 height; ///< Height in pixels 1231ed98bd31Smaya UINT_32 numSlices; ///< Number of slices 1232ed98bd31Smaya BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1233ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 1234ed98bd31Smaya 1235ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1236ed98bd31Smaya /// while the global useTileIndex is set to 1 1237ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1238ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1239ed98bd31Smaya} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1240ed98bd31Smaya 1241ed98bd31Smaya/** 1242ed98bd31Smaya**************************************************************************************************** 1243ed98bd31Smaya* ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1244ed98bd31Smaya* 1245ed98bd31Smaya* @brief 1246ed98bd31Smaya* Output structure for AddrComputeCmaskCoordFromAddr 1247ed98bd31Smaya**************************************************************************************************** 1248ed98bd31Smaya*/ 1249ed98bd31Smayatypedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1250ed98bd31Smaya{ 1251ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1252ed98bd31Smaya 1253ed98bd31Smaya UINT_32 x; ///< X coordinate 1254ed98bd31Smaya UINT_32 y; ///< Y coordinate 1255ed98bd31Smaya UINT_32 slice; ///< Slice index 1256ed98bd31Smaya} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1257ed98bd31Smaya 1258ed98bd31Smaya/** 1259ed98bd31Smaya**************************************************************************************************** 1260ed98bd31Smaya* AddrComputeCmaskCoordFromAddr 1261ed98bd31Smaya* 1262ed98bd31Smaya* @brief 1263ed98bd31Smaya* Compute coordinates within color buffer (1st pixel of a micro tile) according to 1264ed98bd31Smaya* Cmask address 1265ed98bd31Smaya**************************************************************************************************** 1266ed98bd31Smaya*/ 1267ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1268ed98bd31Smaya ADDR_HANDLE hLib, 1269ed98bd31Smaya const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1270ed98bd31Smaya ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1271ed98bd31Smaya 12727ec681f3Smrg 12737ec681f3Smrg 1274ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1275ed98bd31Smaya// F-mask functions 1276ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1277ed98bd31Smaya 1278ed98bd31Smaya/** 1279ed98bd31Smaya**************************************************************************************************** 1280ed98bd31Smaya* ADDR_COMPUTE_FMASK_INFO_INPUT 1281ed98bd31Smaya* 1282ed98bd31Smaya* @brief 1283ed98bd31Smaya* Input structure for AddrComputeFmaskInfo 1284ed98bd31Smaya**************************************************************************************************** 1285ed98bd31Smaya*/ 1286ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1287ed98bd31Smaya{ 1288ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1289ed98bd31Smaya 1290ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 1291ed98bd31Smaya UINT_32 pitch; ///< Surface pitch, in pixels 1292ed98bd31Smaya UINT_32 height; ///< Surface height, in pixels 1293ed98bd31Smaya UINT_32 numSlices; ///< Number of slice/depth 1294ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 1295ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1296ed98bd31Smaya /// number of samples for normal AA; Set it to the 1297ed98bd31Smaya /// number of fragments for EQAA 1298ed98bd31Smaya /// r800 and later HWL parameters 1299ed98bd31Smaya struct 1300ed98bd31Smaya { 1301ed98bd31Smaya UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1302ed98bd31Smaya /// by H/W clients. S/W should always set it to FALSE. 1303ed98bd31Smaya UINT_32 reserved: 31; ///< Reserved for future use. 1304ed98bd31Smaya }; 1305ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1306ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1307ed98bd31Smaya /// while the global useTileIndex is set to 1 1308ed98bd31Smaya} ADDR_COMPUTE_FMASK_INFO_INPUT; 1309ed98bd31Smaya 1310ed98bd31Smaya/** 1311ed98bd31Smaya**************************************************************************************************** 1312ed98bd31Smaya* ADDR_COMPUTE_FMASK_INFO_OUTPUT 1313ed98bd31Smaya* 1314ed98bd31Smaya* @brief 1315ed98bd31Smaya* Output structure for AddrComputeFmaskInfo 1316ed98bd31Smaya**************************************************************************************************** 1317ed98bd31Smaya*/ 1318ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1319ed98bd31Smaya{ 1320ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1321ed98bd31Smaya 1322ed98bd31Smaya UINT_32 pitch; ///< Pitch of fmask in pixels 1323ed98bd31Smaya UINT_32 height; ///< Height of fmask in pixels 1324ed98bd31Smaya UINT_32 numSlices; ///< Slices of fmask 1325ed98bd31Smaya UINT_64 fmaskBytes; ///< Size of fmask in bytes 1326ed98bd31Smaya UINT_32 baseAlign; ///< Base address alignment 1327ed98bd31Smaya UINT_32 pitchAlign; ///< Pitch alignment 1328ed98bd31Smaya UINT_32 heightAlign; ///< Height alignment 1329ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1330ed98bd31Smaya UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1331ed98bd31Smaya /// may be changed in 9xx and above 1332ed98bd31Smaya /// r800 and later HWL parameters 1333ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1334ed98bd31Smaya /// bank_height from color buffer 1335ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1336ed98bd31Smaya /// while the global useTileIndex is set to 1 1337ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1338ed98bd31Smaya UINT_64 sliceSize; ///< Size of slice in bytes 1339ed98bd31Smaya} ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1340ed98bd31Smaya 1341ed98bd31Smaya/** 1342ed98bd31Smaya**************************************************************************************************** 1343ed98bd31Smaya* AddrComputeFmaskInfo 1344ed98bd31Smaya* 1345ed98bd31Smaya* @brief 1346ed98bd31Smaya* Compute Fmask pitch/height/depth/alignments and size in bytes 1347ed98bd31Smaya**************************************************************************************************** 1348ed98bd31Smaya*/ 1349ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1350ed98bd31Smaya ADDR_HANDLE hLib, 1351ed98bd31Smaya const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1352ed98bd31Smaya ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1353ed98bd31Smaya 13547ec681f3Smrg 13557ec681f3Smrg 1356ed98bd31Smaya/** 1357ed98bd31Smaya**************************************************************************************************** 1358ed98bd31Smaya* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1359ed98bd31Smaya* 1360ed98bd31Smaya* @brief 1361ed98bd31Smaya* Input structure for AddrComputeFmaskAddrFromCoord 1362ed98bd31Smaya**************************************************************************************************** 1363ed98bd31Smaya*/ 1364ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1365ed98bd31Smaya{ 1366ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1367ed98bd31Smaya 1368ed98bd31Smaya UINT_32 x; ///< X coordinate 1369ed98bd31Smaya UINT_32 y; ///< Y coordinate 1370ed98bd31Smaya UINT_32 slice; ///< Slice index 1371ed98bd31Smaya UINT_32 plane; ///< Plane number 1372ed98bd31Smaya UINT_32 sample; ///< Sample index (fragment index for EQAA) 1373ed98bd31Smaya 1374ed98bd31Smaya UINT_32 pitch; ///< Surface pitch, in pixels 1375ed98bd31Smaya UINT_32 height; ///< Surface height, in pixels 1376ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 1377ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1378ed98bd31Smaya /// number of samples for normal AA; Set it to the 1379ed98bd31Smaya /// number of fragments for EQAA 1380ed98bd31Smaya 1381ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 1382ed98bd31Smaya union 1383ed98bd31Smaya { 1384ed98bd31Smaya struct 1385ed98bd31Smaya { 1386ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 1387ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 1388ed98bd31Smaya }; 1389ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1390ed98bd31Smaya }; 1391ed98bd31Smaya 1392ed98bd31Smaya /// r800 and later HWL parameters 1393ed98bd31Smaya struct 1394ed98bd31Smaya { 1395ed98bd31Smaya UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1396ed98bd31Smaya UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1397ed98bd31Smaya UINT_32 reserved: 30; ///< Reserved for future use. 1398ed98bd31Smaya }; 1399ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1400ed98bd31Smaya 1401ed98bd31Smaya} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1402ed98bd31Smaya 1403ed98bd31Smaya/** 1404ed98bd31Smaya**************************************************************************************************** 1405ed98bd31Smaya* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1406ed98bd31Smaya* 1407ed98bd31Smaya* @brief 1408ed98bd31Smaya* Output structure for AddrComputeFmaskAddrFromCoord 1409ed98bd31Smaya**************************************************************************************************** 1410ed98bd31Smaya*/ 1411ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1412ed98bd31Smaya{ 1413ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1414ed98bd31Smaya 1415ed98bd31Smaya UINT_64 addr; ///< Fmask address 1416ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1417ed98bd31Smaya} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1418ed98bd31Smaya 1419ed98bd31Smaya/** 1420ed98bd31Smaya**************************************************************************************************** 1421ed98bd31Smaya* AddrComputeFmaskAddrFromCoord 1422ed98bd31Smaya* 1423ed98bd31Smaya* @brief 1424ed98bd31Smaya* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1425ed98bd31Smaya**************************************************************************************************** 1426ed98bd31Smaya*/ 1427ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1428ed98bd31Smaya ADDR_HANDLE hLib, 1429ed98bd31Smaya const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1430ed98bd31Smaya ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1431ed98bd31Smaya 14327ec681f3Smrg 14337ec681f3Smrg 1434ed98bd31Smaya/** 1435ed98bd31Smaya**************************************************************************************************** 1436ed98bd31Smaya* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1437ed98bd31Smaya* 1438ed98bd31Smaya* @brief 1439ed98bd31Smaya* Input structure for AddrComputeFmaskCoordFromAddr 1440ed98bd31Smaya**************************************************************************************************** 1441ed98bd31Smaya*/ 1442ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1443ed98bd31Smaya{ 1444ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1445ed98bd31Smaya 1446ed98bd31Smaya UINT_64 addr; ///< Address 1447ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1448ed98bd31Smaya 1449ed98bd31Smaya UINT_32 pitch; ///< Pitch, in pixels 1450ed98bd31Smaya UINT_32 height; ///< Height in pixels 1451ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 1452ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments 1453ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 1454ed98bd31Smaya union 1455ed98bd31Smaya { 1456ed98bd31Smaya struct 1457ed98bd31Smaya { 1458ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 1459ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 1460ed98bd31Smaya }; 1461ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1462ed98bd31Smaya }; 1463ed98bd31Smaya 1464ed98bd31Smaya /// r800 and later HWL parameters 1465ed98bd31Smaya struct 1466ed98bd31Smaya { 1467ed98bd31Smaya UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1468ed98bd31Smaya UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1469ed98bd31Smaya UINT_32 reserved: 30; ///< Reserved for future use. 1470ed98bd31Smaya }; 1471ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1472ed98bd31Smaya 1473ed98bd31Smaya} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1474ed98bd31Smaya 1475ed98bd31Smaya/** 1476ed98bd31Smaya**************************************************************************************************** 1477ed98bd31Smaya* ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1478ed98bd31Smaya* 1479ed98bd31Smaya* @brief 1480ed98bd31Smaya* Output structure for AddrComputeFmaskCoordFromAddr 1481ed98bd31Smaya**************************************************************************************************** 1482ed98bd31Smaya*/ 1483ed98bd31Smayatypedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1484ed98bd31Smaya{ 1485ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1486ed98bd31Smaya 1487ed98bd31Smaya UINT_32 x; ///< X coordinate 1488ed98bd31Smaya UINT_32 y; ///< Y coordinate 1489ed98bd31Smaya UINT_32 slice; ///< Slice index 1490ed98bd31Smaya UINT_32 plane; ///< Plane number 1491ed98bd31Smaya UINT_32 sample; ///< Sample index (fragment index for EQAA) 1492ed98bd31Smaya} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1493ed98bd31Smaya 1494ed98bd31Smaya/** 1495ed98bd31Smaya**************************************************************************************************** 1496ed98bd31Smaya* AddrComputeFmaskCoordFromAddr 1497ed98bd31Smaya* 1498ed98bd31Smaya* @brief 1499ed98bd31Smaya* Compute FMASK coordinate from an given address 1500ed98bd31Smaya**************************************************************************************************** 1501ed98bd31Smaya*/ 1502ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1503ed98bd31Smaya ADDR_HANDLE hLib, 1504ed98bd31Smaya const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1505ed98bd31Smaya ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1506ed98bd31Smaya 15077ec681f3Smrg 15087ec681f3Smrg 1509ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1510ed98bd31Smaya// Element/utility functions 1511ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 1512ed98bd31Smaya 1513ed98bd31Smaya/** 1514ed98bd31Smaya**************************************************************************************************** 1515ed98bd31Smaya* AddrGetVersion 1516ed98bd31Smaya* 1517ed98bd31Smaya* @brief 1518ed98bd31Smaya* Get AddrLib version number 1519ed98bd31Smaya**************************************************************************************************** 1520ed98bd31Smaya*/ 1521ed98bd31SmayaUINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1522ed98bd31Smaya 1523ed98bd31Smaya/** 1524ed98bd31Smaya**************************************************************************************************** 1525ed98bd31Smaya* AddrUseTileIndex 1526ed98bd31Smaya* 1527ed98bd31Smaya* @brief 1528ed98bd31Smaya* Return TRUE if tileIndex is enabled in this address library 1529ed98bd31Smaya**************************************************************************************************** 1530ed98bd31Smaya*/ 1531ed98bd31SmayaBOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1532ed98bd31Smaya 1533ed98bd31Smaya/** 1534ed98bd31Smaya**************************************************************************************************** 1535ed98bd31Smaya* AddrUseCombinedSwizzle 1536ed98bd31Smaya* 1537ed98bd31Smaya* @brief 1538ed98bd31Smaya* Return TRUE if combined swizzle is enabled in this address library 1539ed98bd31Smaya**************************************************************************************************** 1540ed98bd31Smaya*/ 1541ed98bd31SmayaBOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1542ed98bd31Smaya 1543ed98bd31Smaya/** 1544ed98bd31Smaya**************************************************************************************************** 1545ed98bd31Smaya* ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1546ed98bd31Smaya* 1547ed98bd31Smaya* @brief 1548ed98bd31Smaya* Input structure of AddrExtractBankPipeSwizzle 1549ed98bd31Smaya**************************************************************************************************** 1550ed98bd31Smaya*/ 1551ed98bd31Smayatypedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1552ed98bd31Smaya{ 1553ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1554ed98bd31Smaya 1555ed98bd31Smaya UINT_32 base256b; ///< Base256b value 1556ed98bd31Smaya 1557ed98bd31Smaya /// r800 and later HWL parameters 1558ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1559ed98bd31Smaya 1560ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1561ed98bd31Smaya /// while the global useTileIndex is set to 1 1562ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1563ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1564ed98bd31Smaya} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1565ed98bd31Smaya 1566ed98bd31Smaya/** 1567ed98bd31Smaya**************************************************************************************************** 1568ed98bd31Smaya* ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1569ed98bd31Smaya* 1570ed98bd31Smaya* @brief 1571ed98bd31Smaya* Output structure of AddrExtractBankPipeSwizzle 1572ed98bd31Smaya**************************************************************************************************** 1573ed98bd31Smaya*/ 1574ed98bd31Smayatypedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1575ed98bd31Smaya{ 1576ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1577ed98bd31Smaya 1578ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 1579ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 1580ed98bd31Smaya} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1581ed98bd31Smaya 1582ed98bd31Smaya/** 1583ed98bd31Smaya**************************************************************************************************** 1584ed98bd31Smaya* AddrExtractBankPipeSwizzle 1585ed98bd31Smaya* 1586ed98bd31Smaya* @brief 1587ed98bd31Smaya* Extract Bank and Pipe swizzle from base256b 1588ed98bd31Smaya* @return 1589ed98bd31Smaya* ADDR_OK if no error 1590ed98bd31Smaya**************************************************************************************************** 1591ed98bd31Smaya*/ 1592ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1593ed98bd31Smaya ADDR_HANDLE hLib, 1594ed98bd31Smaya const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1595ed98bd31Smaya ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1596ed98bd31Smaya 15977ec681f3Smrg 1598ed98bd31Smaya/** 1599ed98bd31Smaya**************************************************************************************************** 1600ed98bd31Smaya* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1601ed98bd31Smaya* 1602ed98bd31Smaya* @brief 1603ed98bd31Smaya* Input structure of AddrCombineBankPipeSwizzle 1604ed98bd31Smaya**************************************************************************************************** 1605ed98bd31Smaya*/ 1606ed98bd31Smayatypedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1607ed98bd31Smaya{ 1608ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1609ed98bd31Smaya 1610ed98bd31Smaya UINT_32 bankSwizzle; ///< Bank swizzle 1611ed98bd31Smaya UINT_32 pipeSwizzle; ///< Pipe swizzle 1612ed98bd31Smaya UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1613ed98bd31Smaya 1614ed98bd31Smaya /// r800 and later HWL parameters 1615ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1616ed98bd31Smaya 1617ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1618ed98bd31Smaya /// while the global useTileIndex is set to 1 1619ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1620ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1621ed98bd31Smaya} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1622ed98bd31Smaya 1623ed98bd31Smaya/** 1624ed98bd31Smaya**************************************************************************************************** 1625ed98bd31Smaya* ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1626ed98bd31Smaya* 1627ed98bd31Smaya* @brief 1628ed98bd31Smaya* Output structure of AddrCombineBankPipeSwizzle 1629ed98bd31Smaya**************************************************************************************************** 1630ed98bd31Smaya*/ 1631ed98bd31Smayatypedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1632ed98bd31Smaya{ 1633ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1634ed98bd31Smaya 1635ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle 1636ed98bd31Smaya} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1637ed98bd31Smaya 1638ed98bd31Smaya/** 1639ed98bd31Smaya**************************************************************************************************** 1640ed98bd31Smaya* AddrCombineBankPipeSwizzle 1641ed98bd31Smaya* 1642ed98bd31Smaya* @brief 1643ed98bd31Smaya* Combine Bank and Pipe swizzle 1644ed98bd31Smaya* @return 1645ed98bd31Smaya* ADDR_OK if no error 1646ed98bd31Smaya* @note 1647ed98bd31Smaya* baseAddr here is full MCAddress instead of base256b 1648ed98bd31Smaya**************************************************************************************************** 1649ed98bd31Smaya*/ 1650ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1651ed98bd31Smaya ADDR_HANDLE hLib, 1652ed98bd31Smaya const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1653ed98bd31Smaya ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1654ed98bd31Smaya 16557ec681f3Smrg 16567ec681f3Smrg 1657ed98bd31Smaya/** 1658ed98bd31Smaya**************************************************************************************************** 1659ed98bd31Smaya* ADDR_COMPUTE_SLICESWIZZLE_INPUT 1660ed98bd31Smaya* 1661ed98bd31Smaya* @brief 1662ed98bd31Smaya* Input structure of AddrComputeSliceSwizzle 1663ed98bd31Smaya**************************************************************************************************** 1664ed98bd31Smaya*/ 1665ed98bd31Smayatypedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1666ed98bd31Smaya{ 1667ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1668ed98bd31Smaya 1669ed98bd31Smaya AddrTileMode tileMode; ///< Tile Mode 1670ed98bd31Smaya UINT_32 baseSwizzle; ///< Base tile swizzle 1671ed98bd31Smaya UINT_32 slice; ///< Slice index 1672ed98bd31Smaya UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1673ed98bd31Smaya 1674ed98bd31Smaya /// r800 and later HWL parameters 1675ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1676ed98bd31Smaya 1677ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1678ed98bd31Smaya /// while the global useTileIndex is set to 1 1679ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1680ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1681ed98bd31Smaya} ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1682ed98bd31Smaya 16837ec681f3Smrg 16847ec681f3Smrg 1685ed98bd31Smaya/** 1686ed98bd31Smaya**************************************************************************************************** 1687ed98bd31Smaya* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1688ed98bd31Smaya* 1689ed98bd31Smaya* @brief 1690ed98bd31Smaya* Output structure of AddrComputeSliceSwizzle 1691ed98bd31Smaya**************************************************************************************************** 1692ed98bd31Smaya*/ 1693ed98bd31Smayatypedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1694ed98bd31Smaya{ 1695ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1696ed98bd31Smaya 1697ed98bd31Smaya UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1698ed98bd31Smaya} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1699ed98bd31Smaya 1700ed98bd31Smaya/** 1701ed98bd31Smaya**************************************************************************************************** 1702ed98bd31Smaya* AddrComputeSliceSwizzle 1703ed98bd31Smaya* 1704ed98bd31Smaya* @brief 1705ed98bd31Smaya* Extract Bank and Pipe swizzle from base256b 1706ed98bd31Smaya* @return 1707ed98bd31Smaya* ADDR_OK if no error 1708ed98bd31Smaya**************************************************************************************************** 1709ed98bd31Smaya*/ 1710ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1711ed98bd31Smaya ADDR_HANDLE hLib, 1712ed98bd31Smaya const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1713ed98bd31Smaya ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1714ed98bd31Smaya 17157ec681f3Smrg 1716ed98bd31Smaya/** 1717ed98bd31Smaya**************************************************************************************************** 1718ed98bd31Smaya* AddrSwizzleGenOption 1719ed98bd31Smaya* 1720ed98bd31Smaya* @brief 1721ed98bd31Smaya* Which swizzle generating options: legacy or linear 1722ed98bd31Smaya**************************************************************************************************** 1723ed98bd31Smaya*/ 1724ed98bd31Smayatypedef enum _AddrSwizzleGenOption 1725ed98bd31Smaya{ 1726ed98bd31Smaya ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1727ed98bd31Smaya ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1728ed98bd31Smaya} AddrSwizzleGenOption; 1729ed98bd31Smaya 1730ed98bd31Smaya/** 1731ed98bd31Smaya**************************************************************************************************** 1732ed98bd31Smaya* AddrSwizzleOption 1733ed98bd31Smaya* 1734ed98bd31Smaya* @brief 1735ed98bd31Smaya* Controls how swizzle is generated 1736ed98bd31Smaya**************************************************************************************************** 1737ed98bd31Smaya*/ 1738ed98bd31Smayatypedef union _ADDR_SWIZZLE_OPTION 1739ed98bd31Smaya{ 1740ed98bd31Smaya struct 1741ed98bd31Smaya { 1742ed98bd31Smaya UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1743ed98bd31Smaya UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1744ed98bd31Smaya UINT_32 reserved :30; ///< Reserved bits 1745ed98bd31Smaya }; 1746ed98bd31Smaya 1747ed98bd31Smaya UINT_32 value; 1748ed98bd31Smaya 1749ed98bd31Smaya} ADDR_SWIZZLE_OPTION; 1750ed98bd31Smaya 1751ed98bd31Smaya/** 1752ed98bd31Smaya**************************************************************************************************** 1753ed98bd31Smaya* ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1754ed98bd31Smaya* 1755ed98bd31Smaya* @brief 1756ed98bd31Smaya* Input structure of AddrComputeBaseSwizzle 1757ed98bd31Smaya**************************************************************************************************** 1758ed98bd31Smaya*/ 1759ed98bd31Smayatypedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1760ed98bd31Smaya{ 1761ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1762ed98bd31Smaya 1763ed98bd31Smaya ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1764ed98bd31Smaya UINT_32 surfIndex; ///< Index of this surface type 1765ed98bd31Smaya AddrTileMode tileMode; ///< Tile Mode 1766ed98bd31Smaya 1767ed98bd31Smaya /// r800 and later HWL parameters 1768ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1769ed98bd31Smaya 1770ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1771ed98bd31Smaya /// while the global useTileIndex is set to 1 1772ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1773ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 1774ed98bd31Smaya} ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1775ed98bd31Smaya 1776ed98bd31Smaya/** 1777ed98bd31Smaya**************************************************************************************************** 1778ed98bd31Smaya* ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1779ed98bd31Smaya* 1780ed98bd31Smaya* @brief 1781ed98bd31Smaya* Output structure of AddrComputeBaseSwizzle 1782ed98bd31Smaya**************************************************************************************************** 1783ed98bd31Smaya*/ 1784ed98bd31Smayatypedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1785ed98bd31Smaya{ 1786ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1787ed98bd31Smaya 1788ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle 1789ed98bd31Smaya} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1790ed98bd31Smaya 1791ed98bd31Smaya/** 1792ed98bd31Smaya**************************************************************************************************** 1793ed98bd31Smaya* AddrComputeBaseSwizzle 1794ed98bd31Smaya* 1795ed98bd31Smaya* @brief 1796ed98bd31Smaya* Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1797ed98bd31Smaya* @return 1798ed98bd31Smaya* ADDR_OK if no error 1799ed98bd31Smaya**************************************************************************************************** 1800ed98bd31Smaya*/ 1801ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1802ed98bd31Smaya ADDR_HANDLE hLib, 1803ed98bd31Smaya const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1804ed98bd31Smaya ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1805ed98bd31Smaya 18067ec681f3Smrg 18077ec681f3Smrg 1808ed98bd31Smaya/** 1809ed98bd31Smaya**************************************************************************************************** 1810ed98bd31Smaya* ELEM_GETEXPORTNORM_INPUT 1811ed98bd31Smaya* 1812ed98bd31Smaya* @brief 1813ed98bd31Smaya* Input structure for ElemGetExportNorm 1814ed98bd31Smaya* 1815ed98bd31Smaya**************************************************************************************************** 1816ed98bd31Smaya*/ 1817ed98bd31Smayatypedef struct _ELEM_GETEXPORTNORM_INPUT 1818ed98bd31Smaya{ 1819ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1820ed98bd31Smaya 1821ed98bd31Smaya AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1822ed98bd31Smaya AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1823ed98bd31Smaya AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1824ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 1825ed98bd31Smaya} ELEM_GETEXPORTNORM_INPUT; 1826ed98bd31Smaya 1827ed98bd31Smaya/** 1828ed98bd31Smaya**************************************************************************************************** 1829ed98bd31Smaya* ElemGetExportNorm 1830ed98bd31Smaya* 1831ed98bd31Smaya* @brief 1832ed98bd31Smaya* Helper function to check one format can be EXPORT_NUM, which is a register 1833ed98bd31Smaya* CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1834ed98bd31Smaya* family 1835ed98bd31Smaya* @note 1836ed98bd31Smaya* The implementation is only for r600. 1837ed98bd31Smaya* 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1838ed98bd31Smaya* clocks per export) 1839ed98bd31Smaya* 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1840ed98bd31Smaya* clock per export) 1841ed98bd31Smaya* 1842ed98bd31Smaya**************************************************************************************************** 1843ed98bd31Smaya*/ 1844ed98bd31SmayaBOOL_32 ADDR_API ElemGetExportNorm( 1845ed98bd31Smaya ADDR_HANDLE hLib, 1846ed98bd31Smaya const ELEM_GETEXPORTNORM_INPUT* pIn); 1847ed98bd31Smaya 18487ec681f3Smrg 18497ec681f3Smrg 1850ed98bd31Smaya/** 1851ed98bd31Smaya**************************************************************************************************** 1852ed98bd31Smaya* ELEM_FLT32TODEPTHPIXEL_INPUT 1853ed98bd31Smaya* 1854ed98bd31Smaya* @brief 1855ed98bd31Smaya* Input structure for addrFlt32ToDepthPixel 1856ed98bd31Smaya* 1857ed98bd31Smaya**************************************************************************************************** 1858ed98bd31Smaya*/ 1859ed98bd31Smayatypedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1860ed98bd31Smaya{ 1861ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1862ed98bd31Smaya 1863ed98bd31Smaya AddrDepthFormat format; ///< Depth buffer format 1864ed98bd31Smaya ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1865ed98bd31Smaya} ELEM_FLT32TODEPTHPIXEL_INPUT; 1866ed98bd31Smaya 1867ed98bd31Smaya/** 1868ed98bd31Smaya**************************************************************************************************** 1869ed98bd31Smaya* ELEM_FLT32TODEPTHPIXEL_INPUT 1870ed98bd31Smaya* 1871ed98bd31Smaya* @brief 1872ed98bd31Smaya* Output structure for ElemFlt32ToDepthPixel 1873ed98bd31Smaya* 1874ed98bd31Smaya**************************************************************************************************** 1875ed98bd31Smaya*/ 1876ed98bd31Smayatypedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1877ed98bd31Smaya{ 1878ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1879ed98bd31Smaya 1880ed98bd31Smaya UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1881ed98bd31Smaya /// Client must provide enough storage for this type. 1882ed98bd31Smaya UINT_32 depthBase; ///< Tile base in bits for depth bits 1883ed98bd31Smaya UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1884ed98bd31Smaya UINT_32 depthBits; ///< Bits for depth 1885ed98bd31Smaya UINT_32 stencilBits; ///< Bits for stencil 1886ed98bd31Smaya} ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1887ed98bd31Smaya 1888ed98bd31Smaya/** 1889ed98bd31Smaya**************************************************************************************************** 1890ed98bd31Smaya* ElemFlt32ToDepthPixel 1891ed98bd31Smaya* 1892ed98bd31Smaya* @brief 1893ed98bd31Smaya* Convert a FLT_32 value to a depth/stencil pixel value 1894ed98bd31Smaya* 1895ed98bd31Smaya* @return 1896ed98bd31Smaya* Return code 1897ed98bd31Smaya* 1898ed98bd31Smaya**************************************************************************************************** 1899ed98bd31Smaya*/ 1900ed98bd31SmayaADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1901ed98bd31Smaya ADDR_HANDLE hLib, 1902ed98bd31Smaya const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1903ed98bd31Smaya ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1904ed98bd31Smaya 19057ec681f3Smrg 19067ec681f3Smrg 1907ed98bd31Smaya/** 1908ed98bd31Smaya**************************************************************************************************** 1909ed98bd31Smaya* ELEM_FLT32TOCOLORPIXEL_INPUT 1910ed98bd31Smaya* 1911ed98bd31Smaya* @brief 1912ed98bd31Smaya* Input structure for addrFlt32ToColorPixel 1913ed98bd31Smaya* 1914ed98bd31Smaya**************************************************************************************************** 1915ed98bd31Smaya*/ 1916ed98bd31Smayatypedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1917ed98bd31Smaya{ 1918ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1919ed98bd31Smaya 1920ed98bd31Smaya AddrColorFormat format; ///< Color buffer format 1921ed98bd31Smaya AddrSurfaceNumber surfNum; ///< Surface number 1922ed98bd31Smaya AddrSurfaceSwap surfSwap; ///< Surface swap 1923ed98bd31Smaya ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1924ed98bd31Smaya} ELEM_FLT32TOCOLORPIXEL_INPUT; 1925ed98bd31Smaya 1926ed98bd31Smaya/** 1927ed98bd31Smaya**************************************************************************************************** 1928ed98bd31Smaya* ELEM_FLT32TOCOLORPIXEL_INPUT 1929ed98bd31Smaya* 1930ed98bd31Smaya* @brief 1931ed98bd31Smaya* Output structure for ElemFlt32ToColorPixel 1932ed98bd31Smaya* 1933ed98bd31Smaya**************************************************************************************************** 1934ed98bd31Smaya*/ 1935ed98bd31Smayatypedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1936ed98bd31Smaya{ 1937ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1938ed98bd31Smaya 1939ed98bd31Smaya UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1940ed98bd31Smaya /// Client must provide enough storage for this type. 1941ed98bd31Smaya} ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1942ed98bd31Smaya 1943ed98bd31Smaya/** 1944ed98bd31Smaya**************************************************************************************************** 1945ed98bd31Smaya* ElemFlt32ToColorPixel 1946ed98bd31Smaya* 1947ed98bd31Smaya* @brief 1948ed98bd31Smaya* Convert a FLT_32 value to a red/green/blue/alpha pixel value 1949ed98bd31Smaya* 1950ed98bd31Smaya* @return 1951ed98bd31Smaya* Return code 1952ed98bd31Smaya* 1953ed98bd31Smaya**************************************************************************************************** 1954ed98bd31Smaya*/ 1955ed98bd31SmayaADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1956ed98bd31Smaya ADDR_HANDLE hLib, 1957ed98bd31Smaya const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1958ed98bd31Smaya ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1959ed98bd31Smaya 1960ed98bd31Smaya/** 1961ed98bd31Smaya**************************************************************************************************** 1962ed98bd31Smaya* ElemSize 1963ed98bd31Smaya* 1964ed98bd31Smaya* @brief 1965ed98bd31Smaya* Get bits-per-element for specified format 1966ed98bd31Smaya* 1967ed98bd31Smaya* @return 1968ed98bd31Smaya* Bits-per-element of specified format 1969ed98bd31Smaya* 1970ed98bd31Smaya**************************************************************************************************** 1971ed98bd31Smaya*/ 1972ed98bd31SmayaUINT_32 ADDR_API ElemSize( 1973ed98bd31Smaya ADDR_HANDLE hLib, 1974ed98bd31Smaya AddrFormat format); 1975ed98bd31Smaya 1976ed98bd31Smaya/** 1977ed98bd31Smaya**************************************************************************************************** 1978ed98bd31Smaya* ADDR_CONVERT_TILEINFOTOHW_INPUT 1979ed98bd31Smaya* 1980ed98bd31Smaya* @brief 1981ed98bd31Smaya* Input structure for AddrConvertTileInfoToHW 1982ed98bd31Smaya* @note 1983ed98bd31Smaya* When reverse is TRUE, indices are igonred 1984ed98bd31Smaya**************************************************************************************************** 1985ed98bd31Smaya*/ 1986ed98bd31Smayatypedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 1987ed98bd31Smaya{ 1988ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 1989ed98bd31Smaya BOOL_32 reverse; ///< Convert control flag. 1990ed98bd31Smaya /// FALSE: convert from real value to HW value; 1991ed98bd31Smaya /// TRUE: convert from HW value to real value. 1992ed98bd31Smaya 1993ed98bd31Smaya /// r800 and later HWL parameters 1994ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 1995ed98bd31Smaya 1996ed98bd31Smaya INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1997ed98bd31Smaya /// while the global useTileIndex is set to 1 1998ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1999ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 2000ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2001ed98bd31Smaya} ADDR_CONVERT_TILEINFOTOHW_INPUT; 2002ed98bd31Smaya 2003ed98bd31Smaya/** 2004ed98bd31Smaya**************************************************************************************************** 2005ed98bd31Smaya* ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2006ed98bd31Smaya* 2007ed98bd31Smaya* @brief 2008ed98bd31Smaya* Output structure for AddrConvertTileInfoToHW 2009ed98bd31Smaya**************************************************************************************************** 2010ed98bd31Smaya*/ 2011ed98bd31Smayatypedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2012ed98bd31Smaya{ 2013ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2014ed98bd31Smaya 2015ed98bd31Smaya /// r800 and later HWL parameters 2016ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 2017ed98bd31Smaya 2018ed98bd31Smaya} ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 2019ed98bd31Smaya 2020ed98bd31Smaya/** 2021ed98bd31Smaya**************************************************************************************************** 2022ed98bd31Smaya* AddrConvertTileInfoToHW 2023ed98bd31Smaya* 2024ed98bd31Smaya* @brief 2025ed98bd31Smaya* Convert tile info from real value to hardware register value 2026ed98bd31Smaya**************************************************************************************************** 2027ed98bd31Smaya*/ 2028ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 2029ed98bd31Smaya ADDR_HANDLE hLib, 2030ed98bd31Smaya const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 2031ed98bd31Smaya ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 2032ed98bd31Smaya 20337ec681f3Smrg 20347ec681f3Smrg 2035ed98bd31Smaya/** 2036ed98bd31Smaya**************************************************************************************************** 2037ed98bd31Smaya* ADDR_CONVERT_TILEINDEX_INPUT 2038ed98bd31Smaya* 2039ed98bd31Smaya* @brief 2040ed98bd31Smaya* Input structure for AddrConvertTileIndex 2041ed98bd31Smaya**************************************************************************************************** 2042ed98bd31Smaya*/ 2043ed98bd31Smayatypedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2044ed98bd31Smaya{ 2045ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2046ed98bd31Smaya 2047ed98bd31Smaya INT_32 tileIndex; ///< Tile index 2048ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2049ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2050ed98bd31Smaya BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2051ed98bd31Smaya} ADDR_CONVERT_TILEINDEX_INPUT; 2052ed98bd31Smaya 2053ed98bd31Smaya/** 2054ed98bd31Smaya**************************************************************************************************** 2055ed98bd31Smaya* ADDR_CONVERT_TILEINDEX_OUTPUT 2056ed98bd31Smaya* 2057ed98bd31Smaya* @brief 2058ed98bd31Smaya* Output structure for AddrConvertTileIndex 2059ed98bd31Smaya**************************************************************************************************** 2060ed98bd31Smaya*/ 2061ed98bd31Smayatypedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2062ed98bd31Smaya{ 2063ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2064ed98bd31Smaya 2065ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 2066ed98bd31Smaya AddrTileType tileType; ///< Tile type 2067ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Tile info 2068ed98bd31Smaya 2069ed98bd31Smaya} ADDR_CONVERT_TILEINDEX_OUTPUT; 2070ed98bd31Smaya 2071ed98bd31Smaya/** 2072ed98bd31Smaya**************************************************************************************************** 2073ed98bd31Smaya* AddrConvertTileIndex 2074ed98bd31Smaya* 2075ed98bd31Smaya* @brief 2076ed98bd31Smaya* Convert tile index to tile mode/type/info 2077ed98bd31Smaya**************************************************************************************************** 2078ed98bd31Smaya*/ 2079ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2080ed98bd31Smaya ADDR_HANDLE hLib, 2081ed98bd31Smaya const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2082ed98bd31Smaya ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2083ed98bd31Smaya 2084ed98bd31Smaya/** 2085ed98bd31Smaya**************************************************************************************************** 2086ed98bd31Smaya* ADDR_GET_MACROMODEINDEX_INPUT 2087ed98bd31Smaya* 2088ed98bd31Smaya* @brief 2089ed98bd31Smaya* Input structure for AddrGetMacroModeIndex 2090ed98bd31Smaya**************************************************************************************************** 2091ed98bd31Smaya*/ 2092ed98bd31Smayatypedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2093ed98bd31Smaya{ 2094ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2095ed98bd31Smaya ADDR_SURFACE_FLAGS flags; ///< Surface flag 2096ed98bd31Smaya INT_32 tileIndex; ///< Tile index 2097ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2098ed98bd31Smaya UINT_32 numFrags; ///< Number of color fragments 2099ed98bd31Smaya} ADDR_GET_MACROMODEINDEX_INPUT; 2100ed98bd31Smaya 2101ed98bd31Smaya/** 2102ed98bd31Smaya**************************************************************************************************** 2103ed98bd31Smaya* ADDR_GET_MACROMODEINDEX_OUTPUT 2104ed98bd31Smaya* 2105ed98bd31Smaya* @brief 2106ed98bd31Smaya* Output structure for AddrGetMacroModeIndex 2107ed98bd31Smaya**************************************************************************************************** 2108ed98bd31Smaya*/ 2109ed98bd31Smayatypedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2110ed98bd31Smaya{ 2111ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2112ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2113ed98bd31Smaya} ADDR_GET_MACROMODEINDEX_OUTPUT; 2114ed98bd31Smaya 2115ed98bd31Smaya/** 2116ed98bd31Smaya**************************************************************************************************** 2117ed98bd31Smaya* AddrGetMacroModeIndex 2118ed98bd31Smaya* 2119ed98bd31Smaya* @brief 2120ed98bd31Smaya* Get macro mode index based on input parameters 2121ed98bd31Smaya**************************************************************************************************** 2122ed98bd31Smaya*/ 2123ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2124ed98bd31Smaya ADDR_HANDLE hLib, 2125ed98bd31Smaya const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2126ed98bd31Smaya ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2127ed98bd31Smaya 2128ed98bd31Smaya/** 2129ed98bd31Smaya**************************************************************************************************** 2130ed98bd31Smaya* ADDR_CONVERT_TILEINDEX1_INPUT 2131ed98bd31Smaya* 2132ed98bd31Smaya* @brief 2133ed98bd31Smaya* Input structure for AddrConvertTileIndex1 (without macro mode index) 2134ed98bd31Smaya**************************************************************************************************** 2135ed98bd31Smaya*/ 2136ed98bd31Smayatypedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2137ed98bd31Smaya{ 2138ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2139ed98bd31Smaya 2140ed98bd31Smaya INT_32 tileIndex; ///< Tile index 2141ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2142ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 2143ed98bd31Smaya BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2144ed98bd31Smaya} ADDR_CONVERT_TILEINDEX1_INPUT; 2145ed98bd31Smaya 2146ed98bd31Smaya/** 2147ed98bd31Smaya**************************************************************************************************** 2148ed98bd31Smaya* AddrConvertTileIndex1 2149ed98bd31Smaya* 2150ed98bd31Smaya* @brief 2151ed98bd31Smaya* Convert tile index to tile mode/type/info 2152ed98bd31Smaya**************************************************************************************************** 2153ed98bd31Smaya*/ 2154ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2155ed98bd31Smaya ADDR_HANDLE hLib, 2156ed98bd31Smaya const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2157ed98bd31Smaya ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2158ed98bd31Smaya 21597ec681f3Smrg 21607ec681f3Smrg 2161ed98bd31Smaya/** 2162ed98bd31Smaya**************************************************************************************************** 2163ed98bd31Smaya* ADDR_GET_TILEINDEX_INPUT 2164ed98bd31Smaya* 2165ed98bd31Smaya* @brief 2166ed98bd31Smaya* Input structure for AddrGetTileIndex 2167ed98bd31Smaya**************************************************************************************************** 2168ed98bd31Smaya*/ 2169ed98bd31Smayatypedef struct _ADDR_GET_TILEINDEX_INPUT 2170ed98bd31Smaya{ 2171ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2172ed98bd31Smaya 2173ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode 2174ed98bd31Smaya AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2175ed98bd31Smaya ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2176ed98bd31Smaya} ADDR_GET_TILEINDEX_INPUT; 2177ed98bd31Smaya 2178ed98bd31Smaya/** 2179ed98bd31Smaya**************************************************************************************************** 2180ed98bd31Smaya* ADDR_GET_TILEINDEX_OUTPUT 2181ed98bd31Smaya* 2182ed98bd31Smaya* @brief 2183ed98bd31Smaya* Output structure for AddrGetTileIndex 2184ed98bd31Smaya**************************************************************************************************** 2185ed98bd31Smaya*/ 2186ed98bd31Smayatypedef struct _ADDR_GET_TILEINDEX_OUTPUT 2187ed98bd31Smaya{ 2188ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2189ed98bd31Smaya 2190ed98bd31Smaya INT_32 index; ///< index in table 2191ed98bd31Smaya} ADDR_GET_TILEINDEX_OUTPUT; 2192ed98bd31Smaya 2193ed98bd31Smaya/** 2194ed98bd31Smaya**************************************************************************************************** 2195ed98bd31Smaya* AddrGetTileIndex 2196ed98bd31Smaya* 2197ed98bd31Smaya* @brief 2198ed98bd31Smaya* Get the tiling mode index in table 2199ed98bd31Smaya**************************************************************************************************** 2200ed98bd31Smaya*/ 2201ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2202ed98bd31Smaya ADDR_HANDLE hLib, 2203ed98bd31Smaya const ADDR_GET_TILEINDEX_INPUT* pIn, 2204ed98bd31Smaya ADDR_GET_TILEINDEX_OUTPUT* pOut); 2205ed98bd31Smaya 22067ec681f3Smrg 22077ec681f3Smrg 2208ed98bd31Smaya/** 2209ed98bd31Smaya**************************************************************************************************** 2210ed98bd31Smaya* ADDR_PRT_INFO_INPUT 2211ed98bd31Smaya* 2212ed98bd31Smaya* @brief 2213ed98bd31Smaya* Input structure for AddrComputePrtInfo 2214ed98bd31Smaya**************************************************************************************************** 2215ed98bd31Smaya*/ 2216ed98bd31Smayatypedef struct _ADDR_PRT_INFO_INPUT 2217ed98bd31Smaya{ 2218ed98bd31Smaya AddrFormat format; ///< Surface format 2219ed98bd31Smaya UINT_32 baseMipWidth; ///< Base mipmap width 2220ed98bd31Smaya UINT_32 baseMipHeight; ///< Base mipmap height 2221ed98bd31Smaya UINT_32 baseMipDepth; ///< Base mipmap depth 2222ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, 2223ed98bd31Smaya} ADDR_PRT_INFO_INPUT; 2224ed98bd31Smaya 2225ed98bd31Smaya/** 2226ed98bd31Smaya**************************************************************************************************** 2227ed98bd31Smaya* ADDR_PRT_INFO_OUTPUT 2228ed98bd31Smaya* 2229ed98bd31Smaya* @brief 2230ed98bd31Smaya* Input structure for AddrComputePrtInfo 2231ed98bd31Smaya**************************************************************************************************** 2232ed98bd31Smaya*/ 2233ed98bd31Smayatypedef struct _ADDR_PRT_INFO_OUTPUT 2234ed98bd31Smaya{ 2235ed98bd31Smaya UINT_32 prtTileWidth; 2236ed98bd31Smaya UINT_32 prtTileHeight; 2237ed98bd31Smaya} ADDR_PRT_INFO_OUTPUT; 2238ed98bd31Smaya 2239ed98bd31Smaya/** 2240ed98bd31Smaya**************************************************************************************************** 2241ed98bd31Smaya* AddrComputePrtInfo 2242ed98bd31Smaya* 2243ed98bd31Smaya* @brief 2244ed98bd31Smaya* Compute prt surface related information 2245ed98bd31Smaya**************************************************************************************************** 2246ed98bd31Smaya*/ 2247ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2248ed98bd31Smaya ADDR_HANDLE hLib, 2249ed98bd31Smaya const ADDR_PRT_INFO_INPUT* pIn, 2250ed98bd31Smaya ADDR_PRT_INFO_OUTPUT* pOut); 2251ed98bd31Smaya 22527ec681f3Smrg 22537ec681f3Smrg 2254ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2255ed98bd31Smaya// DCC key functions 2256ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2257ed98bd31Smaya 2258ed98bd31Smaya/** 2259ed98bd31Smaya**************************************************************************************************** 2260ed98bd31Smaya* _ADDR_COMPUTE_DCCINFO_INPUT 2261ed98bd31Smaya* 2262ed98bd31Smaya* @brief 2263ed98bd31Smaya* Input structure of AddrComputeDccInfo 2264ed98bd31Smaya**************************************************************************************************** 2265ed98bd31Smaya*/ 2266ed98bd31Smayatypedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2267ed98bd31Smaya{ 2268ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2269ed98bd31Smaya UINT_32 bpp; ///< BitPP of color surface 2270ed98bd31Smaya UINT_32 numSamples; ///< Sample number of color surface 2271ed98bd31Smaya UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2272ed98bd31Smaya AddrTileMode tileMode; ///< Tile mode of color surface 2273ed98bd31Smaya ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2274ed98bd31Smaya UINT_32 tileSwizzle; ///< Tile swizzle 2275ed98bd31Smaya INT_32 tileIndex; ///< Tile index of color surface, 2276ed98bd31Smaya ///< MUST be -1 if you don't want to use it 2277ed98bd31Smaya ///< while the global useTileIndex is set to 1 2278ed98bd31Smaya INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2279ed98bd31Smaya ///< README: When tileIndex is not -1, this must be valid 2280ed98bd31Smaya} ADDR_COMPUTE_DCCINFO_INPUT; 2281ed98bd31Smaya 2282ed98bd31Smaya/** 2283ed98bd31Smaya**************************************************************************************************** 2284ed98bd31Smaya* ADDR_COMPUTE_DCCINFO_OUTPUT 2285ed98bd31Smaya* 2286ed98bd31Smaya* @brief 2287ed98bd31Smaya* Output structure of AddrComputeDccInfo 2288ed98bd31Smaya**************************************************************************************************** 2289ed98bd31Smaya*/ 2290ed98bd31Smayatypedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2291ed98bd31Smaya{ 2292ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2293ed98bd31Smaya UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2294ed98bd31Smaya UINT_64 dccRamSize; ///< Size of dcc key 2295ed98bd31Smaya UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2296ed98bd31Smaya BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2297ed98bd31Smaya BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2298ed98bd31Smaya} ADDR_COMPUTE_DCCINFO_OUTPUT; 2299ed98bd31Smaya 2300ed98bd31Smaya/** 2301ed98bd31Smaya**************************************************************************************************** 2302ed98bd31Smaya* AddrComputeDccInfo 2303ed98bd31Smaya* 2304ed98bd31Smaya* @brief 2305ed98bd31Smaya* Compute DCC key size, base alignment 2306ed98bd31Smaya* info 2307ed98bd31Smaya**************************************************************************************************** 2308ed98bd31Smaya*/ 2309ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2310ed98bd31Smaya ADDR_HANDLE hLib, 2311ed98bd31Smaya const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2312ed98bd31Smaya ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2313ed98bd31Smaya 23147ec681f3Smrg 23157ec681f3Smrg 2316ed98bd31Smaya/** 2317ed98bd31Smaya**************************************************************************************************** 23187ec681f3Smrg* ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2319ed98bd31Smaya* 2320ed98bd31Smaya* @brief 2321ed98bd31Smaya* Output structure of AddrGetMaxAlignments 2322ed98bd31Smaya**************************************************************************************************** 2323ed98bd31Smaya*/ 23247ec681f3Smrgtypedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT 2325ed98bd31Smaya{ 2326ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2327ed98bd31Smaya UINT_32 baseAlign; ///< Maximum base alignment in bytes 23287ec681f3Smrg} ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2329ed98bd31Smaya 2330ed98bd31Smaya/** 2331ed98bd31Smaya**************************************************************************************************** 2332ed98bd31Smaya* AddrGetMaxAlignments 2333ed98bd31Smaya* 2334ed98bd31Smaya* @brief 2335ed98bd31Smaya* Gets maximnum alignments 2336ed98bd31Smaya**************************************************************************************************** 2337ed98bd31Smaya*/ 2338ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2339ed98bd31Smaya ADDR_HANDLE hLib, 23407ec681f3Smrg ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2341ed98bd31Smaya 2342ed98bd31Smaya/** 2343ed98bd31Smaya**************************************************************************************************** 2344ed98bd31Smaya* AddrGetMaxMetaAlignments 2345ed98bd31Smaya* 2346ed98bd31Smaya* @brief 2347ed98bd31Smaya* Gets maximnum alignments for metadata 2348ed98bd31Smaya**************************************************************************************************** 2349ed98bd31Smaya*/ 2350ed98bd31SmayaADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2351ed98bd31Smaya ADDR_HANDLE hLib, 23527ec681f3Smrg ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2353ed98bd31Smaya 2354ed98bd31Smaya/** 2355ed98bd31Smaya**************************************************************************************************** 2356ed98bd31Smaya* Address library interface version 2 2357ed98bd31Smaya* available from Gfx9 hardware 2358ed98bd31Smaya**************************************************************************************************** 2359ed98bd31Smaya* Addr2ComputeSurfaceInfo() 2360ed98bd31Smaya* Addr2ComputeSurfaceAddrFromCoord() 2361ed98bd31Smaya* Addr2ComputeSurfaceCoordFromAddr() 2362ed98bd31Smaya 2363ed98bd31Smaya* Addr2ComputeHtileInfo() 2364ed98bd31Smaya* Addr2ComputeHtileAddrFromCoord() 2365ed98bd31Smaya* Addr2ComputeHtileCoordFromAddr() 2366ed98bd31Smaya* 2367ed98bd31Smaya* Addr2ComputeCmaskInfo() 2368ed98bd31Smaya* Addr2ComputeCmaskAddrFromCoord() 2369ed98bd31Smaya* Addr2ComputeCmaskCoordFromAddr() 2370ed98bd31Smaya* 2371ed98bd31Smaya* Addr2ComputeFmaskInfo() 2372ed98bd31Smaya* Addr2ComputeFmaskAddrFromCoord() 2373ed98bd31Smaya* Addr2ComputeFmaskCoordFromAddr() 2374ed98bd31Smaya* 2375ed98bd31Smaya* Addr2ComputeDccInfo() 2376ed98bd31Smaya* 2377ed98bd31Smaya**/ 2378ed98bd31Smaya 23797ec681f3Smrg 2380ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2381ed98bd31Smaya// Surface functions for Gfx9 2382ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2383ed98bd31Smaya 2384ed98bd31Smaya/** 2385ed98bd31Smaya**************************************************************************************************** 2386ed98bd31Smaya* ADDR2_SURFACE_FLAGS 2387ed98bd31Smaya* 2388ed98bd31Smaya* @brief 2389ed98bd31Smaya* Surface flags 2390ed98bd31Smaya**************************************************************************************************** 2391ed98bd31Smaya*/ 2392ed98bd31Smayatypedef union _ADDR2_SURFACE_FLAGS 2393ed98bd31Smaya{ 2394ed98bd31Smaya struct 2395ed98bd31Smaya { 2396ed98bd31Smaya UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2397ed98bd31Smaya UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2398ed98bd31Smaya UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2399ed98bd31Smaya UINT_32 fmask : 1; ///< This is an fmask surface 2400ed98bd31Smaya UINT_32 overlay : 1; ///< This is an overlay surface 2401ed98bd31Smaya UINT_32 display : 1; ///< This resource is displable, can be used with DRV 2402ed98bd31Smaya UINT_32 prt : 1; ///< This is a partially resident texture 2403ed98bd31Smaya UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2404ed98bd31Smaya UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2405ed98bd31Smaya UINT_32 texture : 1; ///< This resource can be used with SRV 2406ed98bd31Smaya UINT_32 unordered : 1; ///< This resource can be used with UAV 2407ed98bd31Smaya UINT_32 rotated : 1; ///< This resource is rotated and displable 2408ed98bd31Smaya UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2409ed98bd31Smaya UINT_32 opt4space : 1; ///< This resource should be optimized for space 2410ed98bd31Smaya UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2411ed98bd31Smaya UINT_32 noMetadata : 1; ///< This resource has no metadata 2412ed98bd31Smaya UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2413ed98bd31Smaya UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2414ed98bd31Smaya UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2415ed98bd31Smaya UINT_32 reserved : 13; ///< Reserved bits 2416ed98bd31Smaya }; 2417ed98bd31Smaya 2418ed98bd31Smaya UINT_32 value; 2419ed98bd31Smaya} ADDR2_SURFACE_FLAGS; 2420ed98bd31Smaya 2421ed98bd31Smaya/** 2422ed98bd31Smaya**************************************************************************************************** 2423ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_INFO_INPUT 2424ed98bd31Smaya* 2425ed98bd31Smaya* @brief 2426ed98bd31Smaya* Input structure for Addr2ComputeSurfaceInfo 2427ed98bd31Smaya**************************************************************************************************** 2428ed98bd31Smaya*/ 2429ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2430ed98bd31Smaya{ 2431ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2432ed98bd31Smaya 2433ed98bd31Smaya ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2434ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 2435ed98bd31Smaya AddrResourceType resourceType; ///< Surface type 2436ed98bd31Smaya AddrFormat format; ///< Surface format 2437ed98bd31Smaya UINT_32 bpp; ///< bits per pixel 2438ed98bd31Smaya UINT_32 width; ///< Width (of mip0), in pixels 2439ed98bd31Smaya UINT_32 height; ///< Height (of mip0), in pixels 2440ed98bd31Smaya UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2441ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels. 2442ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 2443ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2444ed98bd31Smaya /// number of samples for normal AA; Set it to the 2445ed98bd31Smaya /// number of fragments for EQAA 2446ed98bd31Smaya UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2447ed98bd31Smaya UINT_32 sliceAlign; ///< Required slice size in bytes 2448ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2449ed98bd31Smaya 2450ed98bd31Smaya/** 2451ed98bd31Smaya**************************************************************************************************** 2452ed98bd31Smaya* ADDR2_MIP_INFO 2453ed98bd31Smaya* 2454ed98bd31Smaya* @brief 2455ed98bd31Smaya* Structure that contains information for mip level 2456ed98bd31Smaya* 2457ed98bd31Smaya**************************************************************************************************** 2458ed98bd31Smaya*/ 2459ed98bd31Smayatypedef struct _ADDR2_MIP_INFO 2460ed98bd31Smaya{ 2461ed98bd31Smaya UINT_32 pitch; ///< Pitch in elements 2462ed98bd31Smaya UINT_32 height; ///< Padded height in elements 2463ed98bd31Smaya UINT_32 depth; ///< Padded depth 2464ed98bd31Smaya UINT_32 pixelPitch; ///< Pitch in pixels 2465ed98bd31Smaya UINT_32 pixelHeight; ///< Padded height in pixels 2466ed98bd31Smaya UINT_32 equationIndex; ///< Equation index in the equation table 2467ed98bd31Smaya UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2468ed98bd31Smaya ///< to setup vam surface descriptor, can't be used 2469ed98bd31Smaya ///< to setup swizzle pattern 2470ed98bd31Smaya UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2471ed98bd31Smaya UINT_32 mipTailOffset; ///< mip tail offset in bytes 2472ed98bd31Smaya UINT_32 mipTailCoordX; ///< mip tail coord x 2473ed98bd31Smaya UINT_32 mipTailCoordY; ///< mip tail coord y 2474ed98bd31Smaya UINT_32 mipTailCoordZ; ///< mip tail coord z 2475ed98bd31Smaya} ADDR2_MIP_INFO; 2476ed98bd31Smaya 2477ed98bd31Smaya/** 2478ed98bd31Smaya**************************************************************************************************** 2479ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2480ed98bd31Smaya* 2481ed98bd31Smaya* @brief 2482ed98bd31Smaya* Output structure for Addr2ComputeSurfInfo 2483ed98bd31Smaya* @note 2484ed98bd31Smaya Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2485ed98bd31Smaya Pixel: Original pixel 2486ed98bd31Smaya**************************************************************************************************** 2487ed98bd31Smaya*/ 2488ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2489ed98bd31Smaya{ 2490ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2491ed98bd31Smaya 2492ed98bd31Smaya UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2493ed98bd31Smaya UINT_32 height; ///< Padded height (of mip0) in elements 2494ed98bd31Smaya UINT_32 numSlices; ///< Padded depth for 3d resource 2495ed98bd31Smaya ///< or padded number of slices for 2d array resource 2496ed98bd31Smaya UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2497ed98bd31Smaya UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2498ed98bd31Smaya UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2499ed98bd31Smaya UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2500ed98bd31Smaya UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2501ed98bd31Smaya UINT_32 baseAlign; ///< Base address alignment 2502ed98bd31Smaya UINT_32 bpp; ///< Bits per elements 2503ed98bd31Smaya /// (e.g. blocks for BCn, 1/3 for 96bit) 2504ed98bd31Smaya UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2505ed98bd31Smaya UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2506ed98bd31Smaya UINT_32 pixelPitch; ///< Pitch in original pixels 2507ed98bd31Smaya UINT_32 pixelHeight; ///< Height in original pixels 2508ed98bd31Smaya UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2509ed98bd31Smaya 2510ed98bd31Smaya UINT_32 blockWidth; ///< Width in element inside one block 2511ed98bd31Smaya UINT_32 blockHeight; ///< Height in element inside one block 2512ed98bd31Smaya UINT_32 blockSlices; ///< Slice number inside one block 2513ed98bd31Smaya ///< Prt tile is one block, its width/height/slice 2514ed98bd31Smaya ///< equals to blcok width/height/slice 2515ed98bd31Smaya 2516ed98bd31Smaya BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2517ed98bd31Smaya /// Stereo info 2518ed98bd31Smaya ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2519ed98bd31Smaya /// Mip info 2520ed98bd31Smaya ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2521ed98bd31Smaya /// if it is not NULL, the array is assumed to 2522ed98bd31Smaya /// contain numMipLevels entries 2523ed98bd31Smaya 2524ed98bd31Smaya UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2525ed98bd31Smaya BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2526ed98bd31Smaya UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2527ed98bd31Smaya /// in tail, it will be set to number of mip levels 2528ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2529ed98bd31Smaya 2530ed98bd31Smaya/** 2531ed98bd31Smaya**************************************************************************************************** 2532ed98bd31Smaya* Addr2ComputeSurfaceInfo 2533ed98bd31Smaya* 2534ed98bd31Smaya* @brief 2535ed98bd31Smaya* Compute surface width/height/slices/alignments and suitable tiling mode 2536ed98bd31Smaya**************************************************************************************************** 2537ed98bd31Smaya*/ 2538ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2539ed98bd31Smaya ADDR_HANDLE hLib, 2540ed98bd31Smaya const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2541ed98bd31Smaya ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2542ed98bd31Smaya 25437ec681f3Smrg 25447ec681f3Smrg 2545ed98bd31Smaya/** 2546ed98bd31Smaya**************************************************************************************************** 2547ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2548ed98bd31Smaya* 2549ed98bd31Smaya* @brief 2550ed98bd31Smaya* Input structure for Addr2ComputeSurfaceAddrFromCoord 2551ed98bd31Smaya**************************************************************************************************** 2552ed98bd31Smaya*/ 2553ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2554ed98bd31Smaya{ 2555ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2556ed98bd31Smaya 2557ed98bd31Smaya UINT_32 x; ///< X coordinate 2558ed98bd31Smaya UINT_32 y; ///< Y coordinate 2559ed98bd31Smaya UINT_32 slice; ///< Slice index 2560ed98bd31Smaya UINT_32 sample; ///< Sample index, use fragment index for EQAA 2561ed98bd31Smaya UINT_32 mipId; ///< the mip ID in mip chain 2562ed98bd31Smaya 2563ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2564ed98bd31Smaya ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2565ed98bd31Smaya AddrResourceType resourceType; ///< Surface type 2566ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2567ed98bd31Smaya UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2568ed98bd31Smaya UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2569ed98bd31Smaya UINT_32 numSlices; ///< Surface original slices (of mip0) 2570ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels 2571ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 2572ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2573ed98bd31Smaya /// number of samples for normal AA; Set it to the 2574ed98bd31Smaya /// number of fragments for EQAA 2575ed98bd31Smaya 2576ed98bd31Smaya UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2577ed98bd31Smaya UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2578ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2579ed98bd31Smaya 2580ed98bd31Smaya/** 2581ed98bd31Smaya**************************************************************************************************** 2582ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2583ed98bd31Smaya* 2584ed98bd31Smaya* @brief 2585ed98bd31Smaya* Output structure for Addr2ComputeSurfaceAddrFromCoord 2586ed98bd31Smaya**************************************************************************************************** 2587ed98bd31Smaya*/ 2588ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2589ed98bd31Smaya{ 2590ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2591ed98bd31Smaya 2592ed98bd31Smaya UINT_64 addr; ///< Byte address 2593ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2594ed98bd31Smaya /// For surface bpp < 8, e.g. FMT_1. 2595ed98bd31Smaya UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2596ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2597ed98bd31Smaya 2598ed98bd31Smaya/** 2599ed98bd31Smaya**************************************************************************************************** 2600ed98bd31Smaya* Addr2ComputeSurfaceAddrFromCoord 2601ed98bd31Smaya* 2602ed98bd31Smaya* @brief 2603ed98bd31Smaya* Compute surface address from a given coordinate. 2604ed98bd31Smaya**************************************************************************************************** 2605ed98bd31Smaya*/ 2606ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2607ed98bd31Smaya ADDR_HANDLE hLib, 2608ed98bd31Smaya const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2609ed98bd31Smaya ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2610ed98bd31Smaya 26117ec681f3Smrg 26127ec681f3Smrg 2613ed98bd31Smaya/** 2614ed98bd31Smaya**************************************************************************************************** 2615ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2616ed98bd31Smaya* 2617ed98bd31Smaya* @brief 2618ed98bd31Smaya* Input structure for Addr2ComputeSurfaceCoordFromAddr 2619ed98bd31Smaya**************************************************************************************************** 2620ed98bd31Smaya*/ 2621ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2622ed98bd31Smaya{ 2623ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2624ed98bd31Smaya 2625ed98bd31Smaya UINT_64 addr; ///< Address in bytes 2626ed98bd31Smaya UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2627ed98bd31Smaya /// e.g. FMT_1; 2628ed98bd31Smaya 2629ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2630ed98bd31Smaya ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2631ed98bd31Smaya AddrResourceType resourceType; ///< Surface type 2632ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel 2633ed98bd31Smaya UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2634ed98bd31Smaya UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2635ed98bd31Smaya UINT_32 numSlices; ///< Surface original slices (of mip0) 2636ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels. 2637ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 2638ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2639ed98bd31Smaya /// number of samples for normal AA; Set it to the 2640ed98bd31Smaya /// number of fragments for EQAA 2641ed98bd31Smaya 2642ed98bd31Smaya UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2643ed98bd31Smaya UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2644ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2645ed98bd31Smaya 2646ed98bd31Smaya/** 2647ed98bd31Smaya**************************************************************************************************** 2648ed98bd31Smaya* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2649ed98bd31Smaya* 2650ed98bd31Smaya* @brief 2651ed98bd31Smaya* Output structure for Addr2ComputeSurfaceCoordFromAddr 2652ed98bd31Smaya**************************************************************************************************** 2653ed98bd31Smaya*/ 2654ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2655ed98bd31Smaya{ 2656ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2657ed98bd31Smaya 2658ed98bd31Smaya UINT_32 x; ///< X coordinate 2659ed98bd31Smaya UINT_32 y; ///< Y coordinate 2660ed98bd31Smaya UINT_32 slice; ///< Index of slices 2661ed98bd31Smaya UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2662ed98bd31Smaya UINT_32 mipId; ///< mipmap level id 2663ed98bd31Smaya} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2664ed98bd31Smaya 2665ed98bd31Smaya/** 2666ed98bd31Smaya**************************************************************************************************** 2667ed98bd31Smaya* Addr2ComputeSurfaceCoordFromAddr 2668ed98bd31Smaya* 2669ed98bd31Smaya* @brief 2670ed98bd31Smaya* Compute coordinate from a given surface address 2671ed98bd31Smaya**************************************************************************************************** 2672ed98bd31Smaya*/ 2673ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2674ed98bd31Smaya ADDR_HANDLE hLib, 2675ed98bd31Smaya const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2676ed98bd31Smaya ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2677ed98bd31Smaya 26787ec681f3Smrg 26797ec681f3Smrg 2680ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2681ed98bd31Smaya// HTile functions for Gfx9 2682ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2683ed98bd31Smaya 2684ed98bd31Smaya/** 2685ed98bd31Smaya**************************************************************************************************** 2686ed98bd31Smaya* ADDR2_META_FLAGS 2687ed98bd31Smaya* 2688ed98bd31Smaya* @brief 2689ed98bd31Smaya* Metadata flags 2690ed98bd31Smaya**************************************************************************************************** 2691ed98bd31Smaya*/ 2692ed98bd31Smayatypedef union _ADDR2_META_FLAGS 2693ed98bd31Smaya{ 2694ed98bd31Smaya struct 2695ed98bd31Smaya { 2696ed98bd31Smaya UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2697ed98bd31Smaya UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2698ed98bd31Smaya UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2699ed98bd31Smaya UINT_32 reserved : 29; ///< Reserved bits 2700ed98bd31Smaya }; 2701ed98bd31Smaya 2702ed98bd31Smaya UINT_32 value; 2703ed98bd31Smaya} ADDR2_META_FLAGS; 2704ed98bd31Smaya 2705ed98bd31Smaya/** 2706ed98bd31Smaya**************************************************************************************************** 2707ed98bd31Smaya* ADDR2_META_MIP_INFO 2708ed98bd31Smaya* 2709ed98bd31Smaya* @brief 2710ed98bd31Smaya* Structure to store per mip metadata information 2711ed98bd31Smaya**************************************************************************************************** 2712ed98bd31Smaya*/ 2713ed98bd31Smayatypedef struct _ADDR2_META_MIP_INFO 2714ed98bd31Smaya{ 2715ed98bd31Smaya BOOL_32 inMiptail; 2716ed98bd31Smaya union 2717ed98bd31Smaya { 2718ed98bd31Smaya struct 2719ed98bd31Smaya { 2720ed98bd31Smaya UINT_32 startX; 2721ed98bd31Smaya UINT_32 startY; 2722ed98bd31Smaya UINT_32 startZ; 2723ed98bd31Smaya UINT_32 width; 2724ed98bd31Smaya UINT_32 height; 2725ed98bd31Smaya UINT_32 depth; 2726ed98bd31Smaya }; 2727ed98bd31Smaya 27287ec681f3Smrg // GFX10 2729ed98bd31Smaya struct 2730ed98bd31Smaya { 2731ed98bd31Smaya UINT_32 offset; ///< Metadata offset within one slice, 2732ed98bd31Smaya /// the thickness of a slice is meta block depth. 2733ed98bd31Smaya UINT_32 sliceSize; ///< Metadata size within one slice, 2734ed98bd31Smaya /// the thickness of a slice is meta block depth. 2735ed98bd31Smaya }; 2736ed98bd31Smaya }; 2737ed98bd31Smaya} ADDR2_META_MIP_INFO; 2738ed98bd31Smaya 2739ed98bd31Smaya/** 2740ed98bd31Smaya**************************************************************************************************** 2741ed98bd31Smaya* ADDR2_COMPUTE_HTILE_INFO_INPUT 2742ed98bd31Smaya* 2743ed98bd31Smaya* @brief 2744ed98bd31Smaya* Input structure of Addr2ComputeHtileInfo 2745ed98bd31Smaya**************************************************************************************************** 2746ed98bd31Smaya*/ 2747ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2748ed98bd31Smaya{ 2749ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2750ed98bd31Smaya 2751ed98bd31Smaya ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2752ed98bd31Smaya ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2753ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2754ed98bd31Smaya UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2755ed98bd31Smaya UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2756ed98bd31Smaya UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2757ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2758ed98bd31Smaya UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2759ed98bd31Smaya /// if no mip is in tail, it should be set to 2760ed98bd31Smaya /// number of mip levels 27617ec681f3Smrg /// Only for GFX10 2762ed98bd31Smaya} ADDR2_COMPUTE_HTILE_INFO_INPUT; 2763ed98bd31Smaya 2764ed98bd31Smaya/** 2765ed98bd31Smaya**************************************************************************************************** 2766ed98bd31Smaya* ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2767ed98bd31Smaya* 2768ed98bd31Smaya* @brief 2769ed98bd31Smaya* Output structure of Addr2ComputeHtileInfo 2770ed98bd31Smaya**************************************************************************************************** 2771ed98bd31Smaya*/ 2772ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2773ed98bd31Smaya{ 2774ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2775ed98bd31Smaya 2776ed98bd31Smaya UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2777ed98bd31Smaya /// HTile buffer. This might be larger than original depth 2778ed98bd31Smaya /// buffer pitch when called with an unaligned pitch. 2779ed98bd31Smaya UINT_32 height; ///< Height in pixels, as above 2780ed98bd31Smaya UINT_32 baseAlign; ///< Base alignment 2781ed98bd31Smaya UINT_32 sliceSize; ///< Slice size, in bytes. 2782ed98bd31Smaya UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2783ed98bd31Smaya UINT_32 metaBlkWidth; ///< Meta block width 2784ed98bd31Smaya UINT_32 metaBlkHeight; ///< Meta block height 2785ed98bd31Smaya UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2786ed98bd31Smaya 2787ed98bd31Smaya ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 27887ec681f3Smrg 27897ec681f3Smrg struct { 27907ec681f3Smrg UINT_16* gfx10_bits; /* 72 2-byte elements */ 27917ec681f3Smrg } equation; 2792ed98bd31Smaya} ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2793ed98bd31Smaya 2794ed98bd31Smaya/** 2795ed98bd31Smaya**************************************************************************************************** 2796ed98bd31Smaya* Addr2ComputeHtileInfo 2797ed98bd31Smaya* 2798ed98bd31Smaya* @brief 2799ed98bd31Smaya* Compute Htile pitch, height, base alignment and size in bytes 2800ed98bd31Smaya**************************************************************************************************** 2801ed98bd31Smaya*/ 2802ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2803ed98bd31Smaya ADDR_HANDLE hLib, 2804ed98bd31Smaya const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2805ed98bd31Smaya ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2806ed98bd31Smaya 28077ec681f3Smrg 28087ec681f3Smrg 2809ed98bd31Smaya/** 2810ed98bd31Smaya**************************************************************************************************** 2811ed98bd31Smaya* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2812ed98bd31Smaya* 2813ed98bd31Smaya* @brief 2814ed98bd31Smaya* Input structure for Addr2ComputeHtileAddrFromCoord 2815ed98bd31Smaya**************************************************************************************************** 2816ed98bd31Smaya*/ 2817ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2818ed98bd31Smaya{ 2819ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2820ed98bd31Smaya 2821ed98bd31Smaya UINT_32 x; ///< X coordinate 2822ed98bd31Smaya UINT_32 y; ///< Y coordinate 2823ed98bd31Smaya UINT_32 slice; ///< Index of slices 2824ed98bd31Smaya UINT_32 mipId; ///< mipmap level id 2825ed98bd31Smaya 2826ed98bd31Smaya ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2827ed98bd31Smaya ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2828ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2829ed98bd31Smaya UINT_32 bpp; ///< Depth surface bits per pixel 2830ed98bd31Smaya UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2831ed98bd31Smaya UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2832ed98bd31Smaya UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2833ed98bd31Smaya UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2834ed98bd31Smaya UINT_32 numSamples; ///< Depth surface number of samples 2835ed98bd31Smaya UINT_32 pipeXor; ///< Pipe xor setting 2836ed98bd31Smaya} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2837ed98bd31Smaya 2838ed98bd31Smaya/** 2839ed98bd31Smaya**************************************************************************************************** 2840ed98bd31Smaya* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2841ed98bd31Smaya* 2842ed98bd31Smaya* @brief 2843ed98bd31Smaya* Output structure for Addr2ComputeHtileAddrFromCoord 2844ed98bd31Smaya**************************************************************************************************** 2845ed98bd31Smaya*/ 2846ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2847ed98bd31Smaya{ 2848ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2849ed98bd31Smaya 2850ed98bd31Smaya UINT_64 addr; ///< Address in bytes 2851ed98bd31Smaya} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2852ed98bd31Smaya 2853ed98bd31Smaya/** 2854ed98bd31Smaya**************************************************************************************************** 2855ed98bd31Smaya* Addr2ComputeHtileAddrFromCoord 2856ed98bd31Smaya* 2857ed98bd31Smaya* @brief 2858ed98bd31Smaya* Compute Htile address according to coordinates (of depth buffer) 2859ed98bd31Smaya**************************************************************************************************** 2860ed98bd31Smaya*/ 2861ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2862ed98bd31Smaya ADDR_HANDLE hLib, 2863ed98bd31Smaya const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2864ed98bd31Smaya ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2865ed98bd31Smaya 28667ec681f3Smrg 28677ec681f3Smrg 2868ed98bd31Smaya/** 2869ed98bd31Smaya**************************************************************************************************** 2870ed98bd31Smaya* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2871ed98bd31Smaya* 2872ed98bd31Smaya* @brief 2873ed98bd31Smaya* Input structure for Addr2ComputeHtileCoordFromAddr 2874ed98bd31Smaya**************************************************************************************************** 2875ed98bd31Smaya*/ 2876ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2877ed98bd31Smaya{ 2878ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2879ed98bd31Smaya 2880ed98bd31Smaya UINT_64 addr; ///< Address 2881ed98bd31Smaya 2882ed98bd31Smaya ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2883ed98bd31Smaya ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2884ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2885ed98bd31Smaya UINT_32 bpp; ///< Depth surface bits per pixel 2886ed98bd31Smaya UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2887ed98bd31Smaya UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2888ed98bd31Smaya UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2889ed98bd31Smaya UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2890ed98bd31Smaya UINT_32 numSamples; ///< Depth surface number of samples 2891ed98bd31Smaya UINT_32 pipeXor; ///< Pipe xor setting 2892ed98bd31Smaya} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2893ed98bd31Smaya 2894ed98bd31Smaya/** 2895ed98bd31Smaya**************************************************************************************************** 2896ed98bd31Smaya* ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2897ed98bd31Smaya* 2898ed98bd31Smaya* @brief 2899ed98bd31Smaya* Output structure for Addr2ComputeHtileCoordFromAddr 2900ed98bd31Smaya**************************************************************************************************** 2901ed98bd31Smaya*/ 2902ed98bd31Smayatypedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2903ed98bd31Smaya{ 2904ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2905ed98bd31Smaya 2906ed98bd31Smaya UINT_32 x; ///< X coordinate 2907ed98bd31Smaya UINT_32 y; ///< Y coordinate 2908ed98bd31Smaya UINT_32 slice; ///< Index of slices 2909ed98bd31Smaya UINT_32 mipId; ///< mipmap level id 2910ed98bd31Smaya} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2911ed98bd31Smaya 2912ed98bd31Smaya/** 2913ed98bd31Smaya**************************************************************************************************** 2914ed98bd31Smaya* Addr2ComputeHtileCoordFromAddr 2915ed98bd31Smaya* 2916ed98bd31Smaya* @brief 2917ed98bd31Smaya* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2918ed98bd31Smaya* Htile address 2919ed98bd31Smaya**************************************************************************************************** 2920ed98bd31Smaya*/ 2921ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2922ed98bd31Smaya ADDR_HANDLE hLib, 2923ed98bd31Smaya const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2924ed98bd31Smaya ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2925ed98bd31Smaya 29267ec681f3Smrg 29277ec681f3Smrg 2928ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2929ed98bd31Smaya// C-mask functions for Gfx9 2930ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 2931ed98bd31Smaya 2932ed98bd31Smaya/** 2933ed98bd31Smaya**************************************************************************************************** 2934ed98bd31Smaya* ADDR2_COMPUTE_CMASK_INFO_INPUT 2935ed98bd31Smaya* 2936ed98bd31Smaya* @brief 2937ed98bd31Smaya* Input structure of Addr2ComputeCmaskInfo 2938ed98bd31Smaya**************************************************************************************************** 2939ed98bd31Smaya*/ 2940ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2941ed98bd31Smaya{ 2942ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2943ed98bd31Smaya 2944ed98bd31Smaya ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2945ed98bd31Smaya ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2946ed98bd31Smaya AddrResourceType resourceType; ///< Color surface type 2947ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2948ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width 2949ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height 2950ed98bd31Smaya UINT_32 numSlices; ///< Number of slices of color buffer 29517ec681f3Smrg UINT_32 numMipLevels; ///< Number of mip levels 29527ec681f3Smrg UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 29537ec681f3Smrg /// it should be number of mip levels 29547ec681f3Smrg /// Only for GFX10 2955ed98bd31Smaya} ADDR2_COMPUTE_CMASK_INFO_INPUT; 2956ed98bd31Smaya 29577ec681f3Smrg/* DCC addr meta equation for GFX9. */ 29587ec681f3Smrgstruct gfx9_addr_meta_equation { 29597ec681f3Smrg UINT_8 num_bits; 29607ec681f3Smrg 29617ec681f3Smrg struct { 29627ec681f3Smrg struct { 29637ec681f3Smrg UINT_8 dim; /* 0..4 as index, 5 means invalid */ 29647ec681f3Smrg UINT_8 ord; /* 0..31 */ 29657ec681f3Smrg } coord[8]; /* 0..num_coords */ 29667ec681f3Smrg } bit[32]; /* 0..num_bits */ 29677ec681f3Smrg 29687ec681f3Smrg UINT_8 numPipeBits; 29697ec681f3Smrg}; 29707ec681f3Smrg 2971ed98bd31Smaya/** 2972ed98bd31Smaya**************************************************************************************************** 2973ed98bd31Smaya* ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2974ed98bd31Smaya* 2975ed98bd31Smaya* @brief 2976ed98bd31Smaya* Output structure of Addr2ComputeCmaskInfo 2977ed98bd31Smaya**************************************************************************************************** 2978ed98bd31Smaya*/ 2979ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2980ed98bd31Smaya{ 2981ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 2982ed98bd31Smaya 2983ed98bd31Smaya UINT_32 pitch; ///< Pitch in pixels of color buffer which 2984ed98bd31Smaya /// this Cmask matches. The size might be larger than 2985ed98bd31Smaya /// original color buffer pitch when called with 2986ed98bd31Smaya /// an unaligned pitch. 2987ed98bd31Smaya UINT_32 height; ///< Height in pixels, as above 2988ed98bd31Smaya UINT_32 baseAlign; ///< Base alignment 2989ed98bd31Smaya UINT_32 sliceSize; ///< Slice size, in bytes. 2990ed98bd31Smaya UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 2991ed98bd31Smaya UINT_32 metaBlkWidth; ///< Meta block width 2992ed98bd31Smaya UINT_32 metaBlkHeight; ///< Meta block height 2993ed98bd31Smaya 29947ec681f3Smrg UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 29957ec681f3Smrg 29967ec681f3Smrg ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 29977ec681f3Smrg 29987ec681f3Smrg /* The equation for doing CMASK address computations in shaders. */ 29997ec681f3Smrg union { 30007ec681f3Smrg /* This is chip-specific, and it varies with: 30017ec681f3Smrg * - resource type 30027ec681f3Smrg * - swizzle_mode 30037ec681f3Smrg * - bpp 30047ec681f3Smrg * - pipe_aligned 30057ec681f3Smrg * - rb_aligned 30067ec681f3Smrg */ 30077ec681f3Smrg struct gfx9_addr_meta_equation gfx9; 30087ec681f3Smrg 30097ec681f3Smrg /* This is chip-specific, it requires 64KB_Z_X. */ 30107ec681f3Smrg UINT_16 *gfx10_bits; /* 68 2-byte elements */ 30117ec681f3Smrg } equation; 3012ed98bd31Smaya} ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 3013ed98bd31Smaya 3014ed98bd31Smaya/** 3015ed98bd31Smaya**************************************************************************************************** 3016ed98bd31Smaya* Addr2ComputeCmaskInfo 3017ed98bd31Smaya* 3018ed98bd31Smaya* @brief 3019ed98bd31Smaya* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 3020ed98bd31Smaya* info 3021ed98bd31Smaya**************************************************************************************************** 3022ed98bd31Smaya*/ 3023ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 3024ed98bd31Smaya ADDR_HANDLE hLib, 3025ed98bd31Smaya const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 3026ed98bd31Smaya ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 3027ed98bd31Smaya 30287ec681f3Smrg 30297ec681f3Smrg 3030ed98bd31Smaya/** 3031ed98bd31Smaya**************************************************************************************************** 3032ed98bd31Smaya* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3033ed98bd31Smaya* 3034ed98bd31Smaya* @brief 3035ed98bd31Smaya* Input structure for Addr2ComputeCmaskAddrFromCoord 3036ed98bd31Smaya* 3037ed98bd31Smaya**************************************************************************************************** 3038ed98bd31Smaya*/ 3039ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3040ed98bd31Smaya{ 3041ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3042ed98bd31Smaya 3043ed98bd31Smaya UINT_32 x; ///< X coordinate 3044ed98bd31Smaya UINT_32 y; ///< Y coordinate 3045ed98bd31Smaya UINT_32 slice; ///< Index of slices 3046ed98bd31Smaya 3047ed98bd31Smaya ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3048ed98bd31Smaya ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3049ed98bd31Smaya AddrResourceType resourceType; ///< Color surface type 3050ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3051ed98bd31Smaya 3052ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3053ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3054ed98bd31Smaya UINT_32 numSlices; ///< Color surface original slices (of mip0) 3055ed98bd31Smaya 3056ed98bd31Smaya UINT_32 numSamples; ///< Color surfae sample number 3057ed98bd31Smaya UINT_32 numFrags; ///< Color surface fragment number 3058ed98bd31Smaya 3059ed98bd31Smaya UINT_32 pipeXor; ///< pipe Xor setting 3060ed98bd31Smaya} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 3061ed98bd31Smaya 3062ed98bd31Smaya/** 3063ed98bd31Smaya**************************************************************************************************** 3064ed98bd31Smaya* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3065ed98bd31Smaya* 3066ed98bd31Smaya* @brief 3067ed98bd31Smaya* Output structure for Addr2ComputeCmaskAddrFromCoord 3068ed98bd31Smaya**************************************************************************************************** 3069ed98bd31Smaya*/ 3070ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3071ed98bd31Smaya{ 3072ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3073ed98bd31Smaya 3074ed98bd31Smaya UINT_64 addr; ///< CMASK address in bytes 3075ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3076ed98bd31Smaya} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 3077ed98bd31Smaya 3078ed98bd31Smaya/** 3079ed98bd31Smaya**************************************************************************************************** 3080ed98bd31Smaya* Addr2ComputeCmaskAddrFromCoord 3081ed98bd31Smaya* 3082ed98bd31Smaya* @brief 3083ed98bd31Smaya* Compute Cmask address according to coordinates (of MSAA color buffer) 3084ed98bd31Smaya**************************************************************************************************** 3085ed98bd31Smaya*/ 3086ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 3087ed98bd31Smaya ADDR_HANDLE hLib, 3088ed98bd31Smaya const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 3089ed98bd31Smaya ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 3090ed98bd31Smaya 30917ec681f3Smrg 30927ec681f3Smrg 3093ed98bd31Smaya/** 3094ed98bd31Smaya**************************************************************************************************** 3095ed98bd31Smaya* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3096ed98bd31Smaya* 3097ed98bd31Smaya* @brief 3098ed98bd31Smaya* Input structure for Addr2ComputeCmaskCoordFromAddr 3099ed98bd31Smaya**************************************************************************************************** 3100ed98bd31Smaya*/ 3101ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3102ed98bd31Smaya{ 3103ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3104ed98bd31Smaya 3105ed98bd31Smaya UINT_64 addr; ///< CMASK address in bytes 3106ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3107ed98bd31Smaya 3108ed98bd31Smaya ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3109ed98bd31Smaya ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3110ed98bd31Smaya AddrResourceType resourceType; ///< Color surface type 3111ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3112ed98bd31Smaya 3113ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3114ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3115ed98bd31Smaya UINT_32 numSlices; ///< Color surface original slices (of mip0) 3116ed98bd31Smaya UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3117ed98bd31Smaya} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3118ed98bd31Smaya 3119ed98bd31Smaya/** 3120ed98bd31Smaya**************************************************************************************************** 3121ed98bd31Smaya* ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3122ed98bd31Smaya* 3123ed98bd31Smaya* @brief 3124ed98bd31Smaya* Output structure for Addr2ComputeCmaskCoordFromAddr 3125ed98bd31Smaya**************************************************************************************************** 3126ed98bd31Smaya*/ 3127ed98bd31Smayatypedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3128ed98bd31Smaya{ 3129ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3130ed98bd31Smaya 3131ed98bd31Smaya UINT_32 x; ///< X coordinate 3132ed98bd31Smaya UINT_32 y; ///< Y coordinate 3133ed98bd31Smaya UINT_32 slice; ///< Index of slices 3134ed98bd31Smaya UINT_32 mipId; ///< mipmap level id 3135ed98bd31Smaya} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3136ed98bd31Smaya 3137ed98bd31Smaya/** 3138ed98bd31Smaya**************************************************************************************************** 3139ed98bd31Smaya* Addr2ComputeCmaskCoordFromAddr 3140ed98bd31Smaya* 3141ed98bd31Smaya* @brief 3142ed98bd31Smaya* Compute coordinates within color buffer (1st pixel of a micro tile) according to 3143ed98bd31Smaya* Cmask address 3144ed98bd31Smaya**************************************************************************************************** 3145ed98bd31Smaya*/ 3146ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3147ed98bd31Smaya ADDR_HANDLE hLib, 3148ed98bd31Smaya const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3149ed98bd31Smaya ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3150ed98bd31Smaya 31517ec681f3Smrg 31527ec681f3Smrg 3153ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3154ed98bd31Smaya// F-mask functions for Gfx9 3155ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3156ed98bd31Smaya 3157ed98bd31Smaya/** 3158ed98bd31Smaya**************************************************************************************************** 3159ed98bd31Smaya* ADDR2_FMASK_FLAGS 3160ed98bd31Smaya* 3161ed98bd31Smaya* @brief 3162ed98bd31Smaya* FMASK flags 3163ed98bd31Smaya**************************************************************************************************** 3164ed98bd31Smaya*/ 3165ed98bd31Smayatypedef union _ADDR2_FMASK_FLAGS 3166ed98bd31Smaya{ 3167ed98bd31Smaya struct 3168ed98bd31Smaya { 3169ed98bd31Smaya UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3170ed98bd31Smaya /// by H/W clients. S/W should always set it to FALSE. 3171ed98bd31Smaya UINT_32 reserved : 31; ///< Reserved for future use. 3172ed98bd31Smaya }; 3173ed98bd31Smaya 3174ed98bd31Smaya UINT_32 value; 3175ed98bd31Smaya} ADDR2_FMASK_FLAGS; 3176ed98bd31Smaya 3177ed98bd31Smaya/** 3178ed98bd31Smaya**************************************************************************************************** 3179ed98bd31Smaya* ADDR2_COMPUTE_FMASK_INFO_INPUT 3180ed98bd31Smaya* 3181ed98bd31Smaya* @brief 3182ed98bd31Smaya* Input structure for Addr2ComputeFmaskInfo 3183ed98bd31Smaya**************************************************************************************************** 3184ed98bd31Smaya*/ 3185ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3186ed98bd31Smaya{ 3187ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3188ed98bd31Smaya 3189ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3190ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width 3191ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height 3192ed98bd31Smaya UINT_32 numSlices; ///< Number of slices/depth 3193ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3194ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3195ed98bd31Smaya /// number of samples for normal AA; Set it to the 3196ed98bd31Smaya /// number of fragments for EQAA 3197ed98bd31Smaya ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3198ed98bd31Smaya} ADDR2_COMPUTE_FMASK_INFO_INPUT; 3199ed98bd31Smaya 3200ed98bd31Smaya/** 3201ed98bd31Smaya**************************************************************************************************** 3202ed98bd31Smaya* ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3203ed98bd31Smaya* 3204ed98bd31Smaya* @brief 3205ed98bd31Smaya* Output structure for Addr2ComputeFmaskInfo 3206ed98bd31Smaya**************************************************************************************************** 3207ed98bd31Smaya*/ 3208ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3209ed98bd31Smaya{ 3210ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3211ed98bd31Smaya 3212ed98bd31Smaya UINT_32 pitch; ///< Pitch of fmask in pixels 3213ed98bd31Smaya UINT_32 height; ///< Height of fmask in pixels 3214ed98bd31Smaya UINT_32 baseAlign; ///< Base alignment 3215ed98bd31Smaya UINT_32 numSlices; ///< Slices of fmask 3216ed98bd31Smaya UINT_32 fmaskBytes; ///< Size of fmask in bytes 3217ed98bd31Smaya UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3218ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3219ed98bd31Smaya UINT_32 sliceSize; ///< Size of slice in bytes 3220ed98bd31Smaya} ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3221ed98bd31Smaya 3222ed98bd31Smaya/** 3223ed98bd31Smaya**************************************************************************************************** 3224ed98bd31Smaya* Addr2ComputeFmaskInfo 3225ed98bd31Smaya* 3226ed98bd31Smaya* @brief 3227ed98bd31Smaya* Compute Fmask pitch/height/slices/alignments and size in bytes 3228ed98bd31Smaya**************************************************************************************************** 3229ed98bd31Smaya*/ 3230ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3231ed98bd31Smaya ADDR_HANDLE hLib, 3232ed98bd31Smaya const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3233ed98bd31Smaya ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3234ed98bd31Smaya 32357ec681f3Smrg 32367ec681f3Smrg 3237ed98bd31Smaya/** 3238ed98bd31Smaya**************************************************************************************************** 3239ed98bd31Smaya* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3240ed98bd31Smaya* 3241ed98bd31Smaya* @brief 3242ed98bd31Smaya* Input structure for Addr2ComputeFmaskAddrFromCoord 3243ed98bd31Smaya**************************************************************************************************** 3244ed98bd31Smaya*/ 3245ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3246ed98bd31Smaya{ 3247ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3248ed98bd31Smaya 3249ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3250ed98bd31Smaya UINT_32 x; ///< X coordinate 3251ed98bd31Smaya UINT_32 y; ///< Y coordinate 3252ed98bd31Smaya UINT_32 slice; ///< Slice index 3253ed98bd31Smaya UINT_32 sample; ///< Sample index (fragment index for EQAA) 3254ed98bd31Smaya UINT_32 plane; ///< Plane number 3255ed98bd31Smaya 3256ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width 3257ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height 3258ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3259ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3260ed98bd31Smaya /// number of samples for normal AA; Set it to the 3261ed98bd31Smaya /// number of fragments for EQAA 3262ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3263ed98bd31Smaya 3264ed98bd31Smaya ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3265ed98bd31Smaya} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3266ed98bd31Smaya 3267ed98bd31Smaya/** 3268ed98bd31Smaya**************************************************************************************************** 3269ed98bd31Smaya* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3270ed98bd31Smaya* 3271ed98bd31Smaya* @brief 3272ed98bd31Smaya* Output structure for Addr2ComputeFmaskAddrFromCoord 3273ed98bd31Smaya**************************************************************************************************** 3274ed98bd31Smaya*/ 3275ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3276ed98bd31Smaya{ 3277ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3278ed98bd31Smaya 3279ed98bd31Smaya UINT_64 addr; ///< Fmask address 3280ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3281ed98bd31Smaya} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3282ed98bd31Smaya 3283ed98bd31Smaya/** 3284ed98bd31Smaya**************************************************************************************************** 3285ed98bd31Smaya* Addr2ComputeFmaskAddrFromCoord 3286ed98bd31Smaya* 3287ed98bd31Smaya* @brief 3288ed98bd31Smaya* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3289ed98bd31Smaya**************************************************************************************************** 3290ed98bd31Smaya*/ 3291ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3292ed98bd31Smaya ADDR_HANDLE hLib, 3293ed98bd31Smaya const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3294ed98bd31Smaya ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3295ed98bd31Smaya 32967ec681f3Smrg 32977ec681f3Smrg 3298ed98bd31Smaya/** 3299ed98bd31Smaya**************************************************************************************************** 3300ed98bd31Smaya* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3301ed98bd31Smaya* 3302ed98bd31Smaya* @brief 3303ed98bd31Smaya* Input structure for Addr2ComputeFmaskCoordFromAddr 3304ed98bd31Smaya**************************************************************************************************** 3305ed98bd31Smaya*/ 3306ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3307ed98bd31Smaya{ 3308ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3309ed98bd31Smaya 3310ed98bd31Smaya UINT_64 addr; ///< Address 3311ed98bd31Smaya UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3312ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3313ed98bd31Smaya 3314ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width 3315ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height 3316ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3317ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments 3318ed98bd31Smaya 3319ed98bd31Smaya UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3320ed98bd31Smaya 3321ed98bd31Smaya ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3322ed98bd31Smaya} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3323ed98bd31Smaya 3324ed98bd31Smaya/** 3325ed98bd31Smaya**************************************************************************************************** 3326ed98bd31Smaya* ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3327ed98bd31Smaya* 3328ed98bd31Smaya* @brief 3329ed98bd31Smaya* Output structure for Addr2ComputeFmaskCoordFromAddr 3330ed98bd31Smaya**************************************************************************************************** 3331ed98bd31Smaya*/ 3332ed98bd31Smayatypedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3333ed98bd31Smaya{ 3334ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3335ed98bd31Smaya 3336ed98bd31Smaya UINT_32 x; ///< X coordinate 3337ed98bd31Smaya UINT_32 y; ///< Y coordinate 3338ed98bd31Smaya UINT_32 slice; ///< Slice index 3339ed98bd31Smaya UINT_32 sample; ///< Sample index (fragment index for EQAA) 3340ed98bd31Smaya UINT_32 plane; ///< Plane number 3341ed98bd31Smaya} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3342ed98bd31Smaya 3343ed98bd31Smaya/** 3344ed98bd31Smaya**************************************************************************************************** 3345ed98bd31Smaya* Addr2ComputeFmaskCoordFromAddr 3346ed98bd31Smaya* 3347ed98bd31Smaya* @brief 3348ed98bd31Smaya* Compute FMASK coordinate from an given address 3349ed98bd31Smaya**************************************************************************************************** 3350ed98bd31Smaya*/ 3351ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3352ed98bd31Smaya ADDR_HANDLE hLib, 3353ed98bd31Smaya const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3354ed98bd31Smaya ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3355ed98bd31Smaya 33567ec681f3Smrg 33577ec681f3Smrg 3358ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3359ed98bd31Smaya// DCC key functions for Gfx9 3360ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3361ed98bd31Smaya 3362ed98bd31Smaya/** 3363ed98bd31Smaya**************************************************************************************************** 3364ed98bd31Smaya* _ADDR2_COMPUTE_DCCINFO_INPUT 3365ed98bd31Smaya* 3366ed98bd31Smaya* @brief 3367ed98bd31Smaya* Input structure of Addr2ComputeDccInfo 3368ed98bd31Smaya**************************************************************************************************** 3369ed98bd31Smaya*/ 3370ed98bd31Smayatypedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3371ed98bd31Smaya{ 3372ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3373ed98bd31Smaya 3374ed98bd31Smaya ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3375ed98bd31Smaya ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3376ed98bd31Smaya AddrResourceType resourceType; ///< Color surface type 3377ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3378ed98bd31Smaya UINT_32 bpp; ///< bits per pixel 3379ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3380ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3381ed98bd31Smaya UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3382ed98bd31Smaya UINT_32 numFrags; ///< Fragment number of color surface 3383ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3384ed98bd31Smaya UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3385ed98bd31Smaya ///< useful in meta linear case 3386ed98bd31Smaya UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3387ed98bd31Smaya /// it should be number of mip levels 33887ec681f3Smrg /// Only for GFX10 3389ed98bd31Smaya} ADDR2_COMPUTE_DCCINFO_INPUT; 3390ed98bd31Smaya 3391ed98bd31Smaya/** 3392ed98bd31Smaya**************************************************************************************************** 3393ed98bd31Smaya* ADDR2_COMPUTE_DCCINFO_OUTPUT 3394ed98bd31Smaya* 3395ed98bd31Smaya* @brief 3396ed98bd31Smaya* Output structure of Addr2ComputeDccInfo 3397ed98bd31Smaya**************************************************************************************************** 3398ed98bd31Smaya*/ 3399ed98bd31Smayatypedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3400ed98bd31Smaya{ 3401ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3402ed98bd31Smaya 3403ed98bd31Smaya UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3404ed98bd31Smaya UINT_32 dccRamSize; ///< Size of dcc key 3405ed98bd31Smaya 3406ed98bd31Smaya UINT_32 pitch; ///< DCC surface mip chain pitch 3407ed98bd31Smaya UINT_32 height; ///< DCC surface mip chain height 3408ed98bd31Smaya UINT_32 depth; ///< DCC surface mip chain depth 3409ed98bd31Smaya 3410ed98bd31Smaya UINT_32 compressBlkWidth; ///< DCC compress block width 3411ed98bd31Smaya UINT_32 compressBlkHeight; ///< DCC compress block height 3412ed98bd31Smaya UINT_32 compressBlkDepth; ///< DCC compress block depth 3413ed98bd31Smaya 3414ed98bd31Smaya UINT_32 metaBlkWidth; ///< DCC meta block width 3415ed98bd31Smaya UINT_32 metaBlkHeight; ///< DCC meta block height 3416ed98bd31Smaya UINT_32 metaBlkDepth; ///< DCC meta block depth 34177ec681f3Smrg UINT_32 metaBlkSize; ///< DCC meta block size in bytes 3418ed98bd31Smaya UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3419ed98bd31Smaya 3420ed98bd31Smaya union 3421ed98bd31Smaya { 3422ed98bd31Smaya UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3423ed98bd31Smaya UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3424ed98bd31Smaya /// the slize size of a mip chain, the thickness of a 3425ed98bd31Smaya /// a slice is meta block depth 34267ec681f3Smrg /// Only for GFX10 3427ed98bd31Smaya }; 3428ed98bd31Smaya 3429ed98bd31Smaya ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 34307ec681f3Smrg 34317ec681f3Smrg /* The equation for doing DCC address computations in shaders. */ 34327ec681f3Smrg union { 34337ec681f3Smrg /* This is chip-specific, and it varies with: 34347ec681f3Smrg * - resource type 34357ec681f3Smrg * - swizzle_mode 34367ec681f3Smrg * - bpp 34377ec681f3Smrg * - number of fragments 34387ec681f3Smrg * - pipe_aligned 34397ec681f3Smrg * - rb_aligned 34407ec681f3Smrg */ 34417ec681f3Smrg struct gfx9_addr_meta_equation gfx9; 34427ec681f3Smrg 34437ec681f3Smrg /* This is chip-specific, it requires 64KB_R_X, and it varies with: 34447ec681f3Smrg * - bpp 34457ec681f3Smrg * - pipe_aligned 34467ec681f3Smrg */ 34477ec681f3Smrg UINT_16 *gfx10_bits; /* 68 2-byte elements */ 34487ec681f3Smrg } equation; 3449ed98bd31Smaya} ADDR2_COMPUTE_DCCINFO_OUTPUT; 3450ed98bd31Smaya 3451ed98bd31Smaya/** 3452ed98bd31Smaya**************************************************************************************************** 3453ed98bd31Smaya* Addr2ComputeDccInfo 3454ed98bd31Smaya* 3455ed98bd31Smaya* @brief 3456ed98bd31Smaya* Compute DCC key size, base alignment 3457ed98bd31Smaya* info 3458ed98bd31Smaya**************************************************************************************************** 3459ed98bd31Smaya*/ 3460ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3461ed98bd31Smaya ADDR_HANDLE hLib, 3462ed98bd31Smaya const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3463ed98bd31Smaya ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3464ed98bd31Smaya 34657ec681f3Smrg 3466ed98bd31Smaya/** 3467ed98bd31Smaya**************************************************************************************************** 3468ed98bd31Smaya* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3469ed98bd31Smaya* 3470ed98bd31Smaya* @brief 3471ed98bd31Smaya* Input structure for Addr2ComputeDccAddrFromCoord 3472ed98bd31Smaya* 3473ed98bd31Smaya**************************************************************************************************** 3474ed98bd31Smaya*/ 3475ed98bd31Smayatypedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3476ed98bd31Smaya{ 3477ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3478ed98bd31Smaya 3479ed98bd31Smaya UINT_32 x; ///< X coordinate 3480ed98bd31Smaya UINT_32 y; ///< Y coordinate 3481ed98bd31Smaya UINT_32 slice; ///< Index of slices 3482ed98bd31Smaya UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3483ed98bd31Smaya UINT_32 mipId; ///< mipmap level id 3484ed98bd31Smaya 3485ed98bd31Smaya ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3486ed98bd31Smaya ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3487ed98bd31Smaya AddrResourceType resourceType; ///< Color surface type 3488ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3489ed98bd31Smaya UINT_32 bpp; ///< Color surface bits per pixel 3490ed98bd31Smaya UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3491ed98bd31Smaya UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3492ed98bd31Smaya UINT_32 numSlices; ///< Color surface original slices (of mip0) 3493ed98bd31Smaya UINT_32 numMipLevels; ///< Color surface mipmap levels 3494ed98bd31Smaya UINT_32 numFrags; ///< Color surface fragment number 3495ed98bd31Smaya 3496ed98bd31Smaya UINT_32 pipeXor; ///< pipe Xor setting 34977ec681f3Smrg UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 34987ec681f3Smrg UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 34997ec681f3Smrg UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 35007ec681f3Smrg UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 35017ec681f3Smrg UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 35027ec681f3Smrg UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 35037ec681f3Smrg UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 35047ec681f3Smrg UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 35057ec681f3Smrg UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3506ed98bd31Smaya} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3507ed98bd31Smaya 3508ed98bd31Smaya/** 3509ed98bd31Smaya**************************************************************************************************** 3510ed98bd31Smaya* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3511ed98bd31Smaya* 3512ed98bd31Smaya* @brief 3513ed98bd31Smaya* Output structure for Addr2ComputeDccAddrFromCoord 3514ed98bd31Smaya**************************************************************************************************** 3515ed98bd31Smaya*/ 3516ed98bd31Smayatypedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3517ed98bd31Smaya{ 3518ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3519ed98bd31Smaya 3520ed98bd31Smaya UINT_64 addr; ///< DCC address in bytes 3521ed98bd31Smaya} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3522ed98bd31Smaya 3523ed98bd31Smaya/** 3524ed98bd31Smaya**************************************************************************************************** 3525ed98bd31Smaya* Addr2ComputeDccAddrFromCoord 3526ed98bd31Smaya* 3527ed98bd31Smaya* @brief 3528ed98bd31Smaya* Compute DCC address according to coordinates (of MSAA color buffer) 3529ed98bd31Smaya**************************************************************************************************** 3530ed98bd31Smaya*/ 3531ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3532ed98bd31Smaya ADDR_HANDLE hLib, 3533ed98bd31Smaya const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3534ed98bd31Smaya ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3535ed98bd31Smaya 3536ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3537ed98bd31Smaya// Misc functions for Gfx9 3538ed98bd31Smaya//////////////////////////////////////////////////////////////////////////////////////////////////// 3539ed98bd31Smaya 3540ed98bd31Smaya/** 3541ed98bd31Smaya**************************************************************************************************** 3542ed98bd31Smaya* ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3543ed98bd31Smaya* 3544ed98bd31Smaya* @brief 3545ed98bd31Smaya* Input structure of Addr2ComputePipebankXor 3546ed98bd31Smaya**************************************************************************************************** 3547ed98bd31Smaya*/ 3548ed98bd31Smayatypedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3549ed98bd31Smaya{ 3550ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3551ed98bd31Smaya UINT_32 surfIndex; ///< Input surface index 3552ed98bd31Smaya ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3553ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3554ed98bd31Smaya AddrResourceType resourceType; ///< Surface resource type 3555ed98bd31Smaya AddrFormat format; ///< Surface format 3556ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3557ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3558ed98bd31Smaya /// number of samples for normal AA; Set it to the 3559ed98bd31Smaya /// number of fragments for EQAA 3560ed98bd31Smaya} ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3561ed98bd31Smaya 3562ed98bd31Smaya/** 3563ed98bd31Smaya**************************************************************************************************** 3564ed98bd31Smaya* ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3565ed98bd31Smaya* 3566ed98bd31Smaya* @brief 3567ed98bd31Smaya* Output structure of Addr2ComputePipebankXor 3568ed98bd31Smaya**************************************************************************************************** 3569ed98bd31Smaya*/ 3570ed98bd31Smayatypedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3571ed98bd31Smaya{ 3572ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3573ed98bd31Smaya UINT_32 pipeBankXor; ///< Pipe bank xor 3574ed98bd31Smaya} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3575ed98bd31Smaya 3576ed98bd31Smaya/** 3577ed98bd31Smaya**************************************************************************************************** 3578ed98bd31Smaya* Addr2ComputePipeBankXor 3579ed98bd31Smaya* 3580ed98bd31Smaya* @brief 3581ed98bd31Smaya* Calculate a valid bank pipe xor value for client to use. 3582ed98bd31Smaya**************************************************************************************************** 3583ed98bd31Smaya*/ 3584ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3585ed98bd31Smaya ADDR_HANDLE hLib, 3586ed98bd31Smaya const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3587ed98bd31Smaya ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3588ed98bd31Smaya 3589ed98bd31Smaya/** 3590ed98bd31Smaya**************************************************************************************************** 3591ed98bd31Smaya* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3592ed98bd31Smaya* 3593ed98bd31Smaya* @brief 3594ed98bd31Smaya* Input structure of Addr2ComputeSlicePipeBankXor 3595ed98bd31Smaya**************************************************************************************************** 3596ed98bd31Smaya*/ 3597ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3598ed98bd31Smaya{ 3599ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3600ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3601ed98bd31Smaya AddrResourceType resourceType; ///< Surface resource type 36027ec681f3Smrg UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 3603ed98bd31Smaya UINT_32 basePipeBankXor; ///< Base pipe bank xor 3604ed98bd31Smaya UINT_32 slice; ///< Slice id 3605ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3606ed98bd31Smaya} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3607ed98bd31Smaya 3608ed98bd31Smaya/** 3609ed98bd31Smaya**************************************************************************************************** 3610ed98bd31Smaya* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3611ed98bd31Smaya* 3612ed98bd31Smaya* @brief 3613ed98bd31Smaya* Output structure of Addr2ComputeSlicePipeBankXor 3614ed98bd31Smaya**************************************************************************************************** 3615ed98bd31Smaya*/ 3616ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3617ed98bd31Smaya{ 3618ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3619ed98bd31Smaya UINT_32 pipeBankXor; ///< Pipe bank xor 3620ed98bd31Smaya} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3621ed98bd31Smaya 3622ed98bd31Smaya/** 3623ed98bd31Smaya**************************************************************************************************** 3624ed98bd31Smaya* Addr2ComputeSlicePipeBankXor 3625ed98bd31Smaya* 3626ed98bd31Smaya* @brief 3627ed98bd31Smaya* Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3628ed98bd31Smaya**************************************************************************************************** 3629ed98bd31Smaya*/ 3630ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3631ed98bd31Smaya ADDR_HANDLE hLib, 3632ed98bd31Smaya const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3633ed98bd31Smaya ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3634ed98bd31Smaya 3635ed98bd31Smaya/** 3636ed98bd31Smaya**************************************************************************************************** 3637ed98bd31Smaya* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3638ed98bd31Smaya* 3639ed98bd31Smaya* @brief 3640ed98bd31Smaya* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3641ed98bd31Smaya**************************************************************************************************** 3642ed98bd31Smaya*/ 3643ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3644ed98bd31Smaya{ 3645ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3646ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3647ed98bd31Smaya AddrResourceType resourceType; ///< Surface resource type 3648ed98bd31Smaya UINT_32 pipeBankXor; ///< Per resource xor 3649ed98bd31Smaya UINT_32 slice; ///< Slice id 3650ed98bd31Smaya UINT_64 sliceSize; ///< Slice size of a mip chain 3651ed98bd31Smaya UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3652ed98bd31Smaya UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3653ed98bd31Smaya} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3654ed98bd31Smaya 3655ed98bd31Smaya/** 3656ed98bd31Smaya**************************************************************************************************** 3657ed98bd31Smaya* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3658ed98bd31Smaya* 3659ed98bd31Smaya* @brief 3660ed98bd31Smaya* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3661ed98bd31Smaya**************************************************************************************************** 3662ed98bd31Smaya*/ 3663ed98bd31Smayatypedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3664ed98bd31Smaya{ 3665ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3666ed98bd31Smaya UINT_64 offset; ///< offset 3667ed98bd31Smaya} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3668ed98bd31Smaya 3669ed98bd31Smaya/** 3670ed98bd31Smaya**************************************************************************************************** 3671ed98bd31Smaya* Addr2ComputeSubResourceOffsetForSwizzlePattern 3672ed98bd31Smaya* 3673ed98bd31Smaya* @brief 3674ed98bd31Smaya* Calculate sub resource offset to support swizzle pattern. 3675ed98bd31Smaya**************************************************************************************************** 3676ed98bd31Smaya*/ 3677ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3678ed98bd31Smaya ADDR_HANDLE hLib, 3679ed98bd31Smaya const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3680ed98bd31Smaya ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3681ed98bd31Smaya 36827ec681f3Smrg/** 36837ec681f3Smrg**************************************************************************************************** 36847ec681f3Smrg* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 36857ec681f3Smrg* 36867ec681f3Smrg* @brief 36877ec681f3Smrg* Input structure of Addr2ComputeNonBlockCompressedView 36887ec681f3Smrg**************************************************************************************************** 36897ec681f3Smrg*/ 36907ec681f3Smrgtypedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 36917ec681f3Smrg{ 36927ec681f3Smrg UINT_32 size; ///< Size of this structure in bytes 36937ec681f3Smrg ADDR2_SURFACE_FLAGS flags; ///< Surface flags 36947ec681f3Smrg AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 36957ec681f3Smrg AddrResourceType resourceType; ///< Surface type 36967ec681f3Smrg AddrFormat format; ///< Surface format 36977ec681f3Smrg UINT_32 width; ///< Width of mip0 in texels (not in compressed block) 36987ec681f3Smrg UINT_32 height; ///< Height of mip0 in texels (not in compressed block) 36997ec681f3Smrg UINT_32 numSlices; ///< Number surface slice/depth of mip0 37007ec681f3Smrg UINT_32 numMipLevels; ///< Total mipmap levels. 37017ec681f3Smrg UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 37027ec681f3Smrg UINT_32 slice; ///< Index of slice to view 37037ec681f3Smrg UINT_32 mipId; ///< Id of mip to view 37047ec681f3Smrg} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 37057ec681f3Smrg 37067ec681f3Smrg/** 37077ec681f3Smrg**************************************************************************************************** 37087ec681f3Smrg* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 37097ec681f3Smrg* 37107ec681f3Smrg* @brief 37117ec681f3Smrg* Output structure of Addr2ComputeNonBlockCompressedView 37127ec681f3Smrg**************************************************************************************************** 37137ec681f3Smrg*/ 37147ec681f3Smrgtypedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 37157ec681f3Smrg{ 37167ec681f3Smrg UINT_32 size; ///< Size of this structure in bytes 37177ec681f3Smrg UINT_64 offset; ///< Offset shifted from resource base for the view 37187ec681f3Smrg UINT_32 pipeBankXor; ///< Pipe bank xor for the view 37197ec681f3Smrg UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view 37207ec681f3Smrg UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view 37217ec681f3Smrg UINT_32 numMipLevels; ///< Total mipmap levels for the view 37227ec681f3Smrg UINT_32 mipId; ///< Mip ID for the view 37237ec681f3Smrg} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 37247ec681f3Smrg 37257ec681f3Smrg/** 37267ec681f3Smrg**************************************************************************************************** 37277ec681f3Smrg* Addr2ComputeNonBlockCompressedView 37287ec681f3Smrg* 37297ec681f3Smrg* @brief 37307ec681f3Smrg* Compute non-block-compressed view for a given mipmap level/slice 37317ec681f3Smrg**************************************************************************************************** 37327ec681f3Smrg*/ 37337ec681f3SmrgADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView( 37347ec681f3Smrg ADDR_HANDLE hLib, 37357ec681f3Smrg const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 37367ec681f3Smrg ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 37377ec681f3Smrg 3738ed98bd31Smaya/** 3739ed98bd31Smaya**************************************************************************************************** 3740ed98bd31Smaya* ADDR2_BLOCK_SET 3741ed98bd31Smaya* 3742ed98bd31Smaya* @brief 3743ed98bd31Smaya* Bit field that defines block type 3744ed98bd31Smaya**************************************************************************************************** 3745ed98bd31Smaya*/ 3746ed98bd31Smayatypedef union _ADDR2_BLOCK_SET 3747ed98bd31Smaya{ 3748ed98bd31Smaya struct 3749ed98bd31Smaya { 37507ec681f3Smrg UINT_32 micro : 1; // 256B block for 2D resource 37517ec681f3Smrg UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 37527ec681f3Smrg UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 37537ec681f3Smrg UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 37547ec681f3Smrg UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 37557ec681f3Smrg UINT_32 var : 1; // VAR block 37567ec681f3Smrg UINT_32 : 1; 37577ec681f3Smrg UINT_32 linear : 1; // Linear block 37587ec681f3Smrg UINT_32 reserved : 24; 3759ed98bd31Smaya }; 3760ed98bd31Smaya 3761ed98bd31Smaya UINT_32 value; 3762ed98bd31Smaya} ADDR2_BLOCK_SET; 3763ed98bd31Smaya 3764ed98bd31Smaya/** 3765ed98bd31Smaya**************************************************************************************************** 3766ed98bd31Smaya* ADDR2_SWTYPE_SET 3767ed98bd31Smaya* 3768ed98bd31Smaya* @brief 3769ed98bd31Smaya* Bit field that defines swizzle type 3770ed98bd31Smaya**************************************************************************************************** 3771ed98bd31Smaya*/ 3772ed98bd31Smayatypedef union _ADDR2_SWTYPE_SET 3773ed98bd31Smaya{ 3774ed98bd31Smaya struct 3775ed98bd31Smaya { 3776ed98bd31Smaya UINT_32 sw_Z : 1; // SW_*_Z_* 3777ed98bd31Smaya UINT_32 sw_S : 1; // SW_*_S_* 3778ed98bd31Smaya UINT_32 sw_D : 1; // SW_*_D_* 3779ed98bd31Smaya UINT_32 sw_R : 1; // SW_*_R_* 3780ed98bd31Smaya UINT_32 reserved : 28; 3781ed98bd31Smaya }; 3782ed98bd31Smaya 3783ed98bd31Smaya UINT_32 value; 3784ed98bd31Smaya} ADDR2_SWTYPE_SET; 3785ed98bd31Smaya 3786ed98bd31Smaya/** 3787ed98bd31Smaya**************************************************************************************************** 3788ed98bd31Smaya* ADDR2_SWMODE_SET 3789ed98bd31Smaya* 3790ed98bd31Smaya* @brief 3791ed98bd31Smaya* Bit field that defines swizzle type 3792ed98bd31Smaya**************************************************************************************************** 3793ed98bd31Smaya*/ 3794ed98bd31Smayatypedef union _ADDR2_SWMODE_SET 3795ed98bd31Smaya{ 3796ed98bd31Smaya struct 3797ed98bd31Smaya { 37987ec681f3Smrg UINT_32 swLinear : 1; 37997ec681f3Smrg UINT_32 sw256B_S : 1; 38007ec681f3Smrg UINT_32 sw256B_D : 1; 38017ec681f3Smrg UINT_32 sw256B_R : 1; 38027ec681f3Smrg UINT_32 sw4KB_Z : 1; 38037ec681f3Smrg UINT_32 sw4KB_S : 1; 38047ec681f3Smrg UINT_32 sw4KB_D : 1; 38057ec681f3Smrg UINT_32 sw4KB_R : 1; 38067ec681f3Smrg UINT_32 sw64KB_Z : 1; 38077ec681f3Smrg UINT_32 sw64KB_S : 1; 38087ec681f3Smrg UINT_32 sw64KB_D : 1; 38097ec681f3Smrg UINT_32 sw64KB_R : 1; 38107ec681f3Smrg UINT_32 swMiscDef12 : 1; 38117ec681f3Smrg UINT_32 swMiscDef13 : 1; 38127ec681f3Smrg UINT_32 swMiscDef14 : 1; 38137ec681f3Smrg UINT_32 swMiscDef15 : 1; 38147ec681f3Smrg UINT_32 sw64KB_Z_T : 1; 38157ec681f3Smrg UINT_32 sw64KB_S_T : 1; 38167ec681f3Smrg UINT_32 sw64KB_D_T : 1; 38177ec681f3Smrg UINT_32 sw64KB_R_T : 1; 38187ec681f3Smrg UINT_32 sw4KB_Z_X : 1; 38197ec681f3Smrg UINT_32 sw4KB_S_X : 1; 38207ec681f3Smrg UINT_32 sw4KB_D_X : 1; 38217ec681f3Smrg UINT_32 sw4KB_R_X : 1; 38227ec681f3Smrg UINT_32 sw64KB_Z_X : 1; 38237ec681f3Smrg UINT_32 sw64KB_S_X : 1; 38247ec681f3Smrg UINT_32 sw64KB_D_X : 1; 38257ec681f3Smrg UINT_32 sw64KB_R_X : 1; 38267ec681f3Smrg UINT_32 swMiscDef28 : 1; 38277ec681f3Smrg UINT_32 swMiscDef29 : 1; 38287ec681f3Smrg UINT_32 swMiscDef30 : 1; 38297ec681f3Smrg UINT_32 swMiscDef31 : 1; 3830ed98bd31Smaya }; 3831ed98bd31Smaya 38327ec681f3Smrg struct 38337ec681f3Smrg { 38347ec681f3Smrg UINT_32 : 28; 38357ec681f3Smrg UINT_32 swVar_Z_X : 1; 38367ec681f3Smrg UINT_32 : 2; 38377ec681f3Smrg UINT_32 swVar_R_X : 1; 38387ec681f3Smrg } gfx10; 38397ec681f3Smrg 3840ed98bd31Smaya UINT_32 value; 3841ed98bd31Smaya} ADDR2_SWMODE_SET; 3842ed98bd31Smaya 3843ed98bd31Smaya/** 3844ed98bd31Smaya**************************************************************************************************** 3845ed98bd31Smaya* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3846ed98bd31Smaya* 3847ed98bd31Smaya* @brief 3848ed98bd31Smaya* Input structure of Addr2GetPreferredSurfaceSetting 3849ed98bd31Smaya**************************************************************************************************** 3850ed98bd31Smaya*/ 3851ed98bd31Smayatypedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3852ed98bd31Smaya{ 3853ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3854ed98bd31Smaya 3855ed98bd31Smaya ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3856ed98bd31Smaya AddrResourceType resourceType; ///< Surface type 3857ed98bd31Smaya AddrFormat format; ///< Surface format 3858ed98bd31Smaya AddrResrouceLocation resourceLoction; ///< Surface heap choice 3859ed98bd31Smaya ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3860ed98bd31Smaya ///< such as linear for DXTn, tiled for YUV 3861ed98bd31Smaya ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3862ed98bd31Smaya BOOL_32 noXor; ///< Do not use xor mode for this resource 3863ed98bd31Smaya UINT_32 bpp; ///< bits per pixel 3864ed98bd31Smaya UINT_32 width; ///< Width (of mip0), in pixels 3865ed98bd31Smaya UINT_32 height; ///< Height (of mip0), in pixels 3866ed98bd31Smaya UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3867ed98bd31Smaya UINT_32 numMipLevels; ///< Total mipmap levels. 3868ed98bd31Smaya UINT_32 numSamples; ///< Number of samples 3869ed98bd31Smaya UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3870ed98bd31Smaya /// number of samples for normal AA; Set it to the 3871ed98bd31Smaya /// number of fragments for EQAA 3872ed98bd31Smaya UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3873ed98bd31Smaya UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3874ed98bd31Smaya /// be padded to multiple of this value (in bytes) 38757ec681f3Smrg DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible 38767ec681f3Smrg /// size. 3877ed98bd31Smaya} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3878ed98bd31Smaya 3879ed98bd31Smaya/** 3880ed98bd31Smaya**************************************************************************************************** 3881ed98bd31Smaya* ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3882ed98bd31Smaya* 3883ed98bd31Smaya* @brief 3884ed98bd31Smaya* Output structure of Addr2GetPreferredSurfaceSetting 3885ed98bd31Smaya**************************************************************************************************** 3886ed98bd31Smaya*/ 3887ed98bd31Smayatypedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3888ed98bd31Smaya{ 3889ed98bd31Smaya UINT_32 size; ///< Size of this structure in bytes 3890ed98bd31Smaya 3891ed98bd31Smaya AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3892ed98bd31Smaya AddrResourceType resourceType; ///< Suggested resource type to program HW 3893ed98bd31Smaya ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3894ed98bd31Smaya BOOL_32 canXor; ///< If client can use xor on a valid macro block 3895ed98bd31Smaya /// type 3896ed98bd31Smaya ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3897ed98bd31Smaya ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3898ed98bd31Smaya ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3899ed98bd31Smaya} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3900ed98bd31Smaya 3901ed98bd31Smaya/** 3902ed98bd31Smaya**************************************************************************************************** 3903ed98bd31Smaya* Addr2GetPreferredSurfaceSetting 3904ed98bd31Smaya* 3905ed98bd31Smaya* @brief 3906ed98bd31Smaya* Suggest a preferred setting for client driver to program HW register 3907ed98bd31Smaya**************************************************************************************************** 3908ed98bd31Smaya*/ 3909ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3910ed98bd31Smaya ADDR_HANDLE hLib, 3911ed98bd31Smaya const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3912ed98bd31Smaya ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3913ed98bd31Smaya 3914ed98bd31Smaya/** 3915ed98bd31Smaya**************************************************************************************************** 3916ed98bd31Smaya* Addr2IsValidDisplaySwizzleMode 3917ed98bd31Smaya* 3918ed98bd31Smaya* @brief 39197ec681f3Smrg* Return whether the swizzle mode is supported by display engine 3920ed98bd31Smaya**************************************************************************************************** 3921ed98bd31Smaya*/ 3922ed98bd31SmayaADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3923ed98bd31Smaya ADDR_HANDLE hLib, 3924ed98bd31Smaya AddrSwizzleMode swizzleMode, 3925ed98bd31Smaya UINT_32 bpp, 39267ec681f3Smrg BOOL_32 *pResult); 3927ed98bd31Smaya 3928ed98bd31Smaya#if defined(__cplusplus) 3929ed98bd31Smaya} 3930ed98bd31Smaya#endif 3931ed98bd31Smaya 3932ed98bd31Smaya#endif // __ADDR_INTERFACE_H__ 3933