1/* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27/** 28************************************************************************************************************************ 29* @file gfx9addrlib.h 30* @brief Contgfx9ns the Gfx9Lib class definition. 31************************************************************************************************************************ 32*/ 33 34#ifndef __GFX9_ADDR_LIB_H__ 35#define __GFX9_ADDR_LIB_H__ 36 37#include "addrlib2.h" 38#include "coord.h" 39 40namespace Addr 41{ 42namespace V2 43{ 44 45/** 46************************************************************************************************************************ 47* @brief GFX9 specific settings structure. 48************************************************************************************************************************ 49*/ 50struct Gfx9ChipSettings 51{ 52 struct 53 { 54 // Asic/Generation name 55 UINT_32 isArcticIsland : 1; 56 UINT_32 isVega10 : 1; 57 UINT_32 isRaven : 1; 58 UINT_32 isVega12 : 1; 59 UINT_32 isVega20 : 1; 60 UINT_32 reserved0 : 27; 61 62 // Display engine IP version name 63 UINT_32 isDce12 : 1; 64 UINT_32 isDcn1 : 1; 65 UINT_32 isDcn2 : 1; 66 UINT_32 reserved1 : 29; 67 68 // Misc configuration bits 69 UINT_32 metaBaseAlignFix : 1; 70 UINT_32 depthPipeXorDisable : 1; 71 UINT_32 htileAlignFix : 1; 72 UINT_32 applyAliasFix : 1; 73 UINT_32 htileCacheRbConflict: 1; 74 UINT_32 reserved2 : 27; 75 }; 76}; 77 78/** 79************************************************************************************************************************ 80* @brief GFX9 data surface type. 81************************************************************************************************************************ 82*/ 83enum Gfx9DataType 84{ 85 Gfx9DataColor, 86 Gfx9DataDepthStencil, 87 Gfx9DataFmask 88}; 89 90const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR); 91 92const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 93 (1u << ADDR_SW_256B_D) | 94 (1u << ADDR_SW_256B_R); 95 96const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) | 97 (1u << ADDR_SW_4KB_S) | 98 (1u << ADDR_SW_4KB_D) | 99 (1u << ADDR_SW_4KB_R) | 100 (1u << ADDR_SW_4KB_Z_X) | 101 (1u << ADDR_SW_4KB_S_X) | 102 (1u << ADDR_SW_4KB_D_X) | 103 (1u << ADDR_SW_4KB_R_X); 104 105const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) | 106 (1u << ADDR_SW_64KB_S) | 107 (1u << ADDR_SW_64KB_D) | 108 (1u << ADDR_SW_64KB_R) | 109 (1u << ADDR_SW_64KB_Z_T) | 110 (1u << ADDR_SW_64KB_S_T) | 111 (1u << ADDR_SW_64KB_D_T) | 112 (1u << ADDR_SW_64KB_R_T) | 113 (1u << ADDR_SW_64KB_Z_X) | 114 (1u << ADDR_SW_64KB_S_X) | 115 (1u << ADDR_SW_64KB_D_X) | 116 (1u << ADDR_SW_64KB_R_X); 117 118const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) | 119 (1u << ADDR_SW_64KB_Z) | 120 (1u << ADDR_SW_64KB_Z_T) | 121 (1u << ADDR_SW_4KB_Z_X) | 122 (1u << ADDR_SW_64KB_Z_X); 123 124const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) | 125 (1u << ADDR_SW_4KB_S) | 126 (1u << ADDR_SW_64KB_S) | 127 (1u << ADDR_SW_64KB_S_T) | 128 (1u << ADDR_SW_4KB_S_X) | 129 (1u << ADDR_SW_64KB_S_X); 130 131const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 132 (1u << ADDR_SW_4KB_D) | 133 (1u << ADDR_SW_64KB_D) | 134 (1u << ADDR_SW_64KB_D_T) | 135 (1u << ADDR_SW_4KB_D_X) | 136 (1u << ADDR_SW_64KB_D_X); 137 138const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) | 139 (1u << ADDR_SW_4KB_R) | 140 (1u << ADDR_SW_64KB_R) | 141 (1u << ADDR_SW_64KB_R_T) | 142 (1u << ADDR_SW_4KB_R_X) | 143 (1u << ADDR_SW_64KB_R_X); 144 145const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) | 146 (1u << ADDR_SW_4KB_S_X) | 147 (1u << ADDR_SW_4KB_D_X) | 148 (1u << ADDR_SW_4KB_R_X) | 149 (1u << ADDR_SW_64KB_Z_X) | 150 (1u << ADDR_SW_64KB_S_X) | 151 (1u << ADDR_SW_64KB_D_X) | 152 (1u << ADDR_SW_64KB_R_X); 153 154const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) | 155 (1u << ADDR_SW_64KB_S_T) | 156 (1u << ADDR_SW_64KB_D_T) | 157 (1u << ADDR_SW_64KB_R_T); 158 159const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask | 160 Gfx9TSwModeMask; 161 162const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask | 163 Gfx9ZSwModeMask | 164 Gfx9StandardSwModeMask | 165 Gfx9DisplaySwModeMask | 166 Gfx9RotateSwModeMask; 167 168const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask; 169 170const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask; 171 172const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask; 173 174const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask; 175 176const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask; 177 178const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask; 179 180const UINT_32 Gfx9Rsrc3dThin4KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk4KBSwModeMask; 181 182const UINT_32 Gfx9Rsrc3dThin64KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk64KBSwModeMask; 183 184const UINT_32 Gfx9Rsrc3dThickSwModeMask = Gfx9Rsrc3dSwModeMask & ~(Gfx9Rsrc3dThinSwModeMask | Gfx9LinearSwModeMask); 185 186const UINT_32 Gfx9Rsrc3dThick4KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk4KBSwModeMask; 187 188const UINT_32 Gfx9Rsrc3dThick64KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk64KBSwModeMask; 189 190const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask; 191 192const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) | 193 (1u << ADDR_SW_4KB_D) | 194 (1u << ADDR_SW_4KB_R) | 195 (1u << ADDR_SW_64KB_D) | 196 (1u << ADDR_SW_64KB_R) | 197 (1u << ADDR_SW_4KB_D_X) | 198 (1u << ADDR_SW_4KB_R_X) | 199 (1u << ADDR_SW_64KB_D_X) | 200 (1u << ADDR_SW_64KB_R_X); 201 202const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) | 203 (1u << ADDR_SW_256B_R) | 204 Dce12NonBpp32SwModeMask; 205 206const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 207 (1u << ADDR_SW_4KB_S) | 208 (1u << ADDR_SW_64KB_S) | 209 (1u << ADDR_SW_64KB_S_T) | 210 (1u << ADDR_SW_4KB_S_X) | 211 (1u << ADDR_SW_64KB_S_X); 212const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 213 (1u << ADDR_SW_64KB_D) | 214 (1u << ADDR_SW_64KB_D_T) | 215 (1u << ADDR_SW_4KB_D_X) | 216 (1u << ADDR_SW_64KB_D_X) | 217 Dcn1NonBpp64SwModeMask; 218 219const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 220 (1u << ADDR_SW_64KB_S) | 221 (1u << ADDR_SW_64KB_S_T) | 222 (1u << ADDR_SW_64KB_S_X); 223 224const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 225 (1u << ADDR_SW_64KB_D_T) | 226 (1u << ADDR_SW_64KB_D_X) | 227 Dcn2NonBpp64SwModeMask; 228 229/** 230************************************************************************************************************************ 231* @brief GFX9 meta equation parameters 232************************************************************************************************************************ 233*/ 234struct MetaEqParams 235{ 236 UINT_32 maxMip; 237 UINT_32 elementBytesLog2; 238 UINT_32 numSamplesLog2; 239 ADDR2_META_FLAGS metaFlag; 240 Gfx9DataType dataSurfaceType; 241 AddrSwizzleMode swizzleMode; 242 AddrResourceType resourceType; 243 UINT_32 metaBlkWidthLog2; 244 UINT_32 metaBlkHeightLog2; 245 UINT_32 metaBlkDepthLog2; 246 UINT_32 compBlkWidthLog2; 247 UINT_32 compBlkHeightLog2; 248 UINT_32 compBlkDepthLog2; 249}; 250 251/** 252************************************************************************************************************************ 253* @brief This class is the GFX9 specific address library 254* function set. 255************************************************************************************************************************ 256*/ 257class Gfx9Lib : public Lib 258{ 259public: 260 /// Creates Gfx9Lib object 261 static Addr::Lib* CreateObj(const Client* pClient) 262 { 263 VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient); 264 return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL; 265 } 266 267protected: 268 Gfx9Lib(const Client* pClient); 269 virtual ~Gfx9Lib(); 270 271 virtual BOOL_32 HwlIsStandardSwizzle( 272 AddrResourceType resourceType, 273 AddrSwizzleMode swizzleMode) const 274 { 275 return m_swizzleModeTable[swizzleMode].isStd || 276 (IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp); 277 } 278 279 virtual BOOL_32 HwlIsDisplaySwizzle( 280 AddrResourceType resourceType, 281 AddrSwizzleMode swizzleMode) const 282 { 283 return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp; 284 } 285 286 virtual BOOL_32 HwlIsThin( 287 AddrResourceType resourceType, 288 AddrSwizzleMode swizzleMode) const 289 { 290 return ((IsTex2d(resourceType) == TRUE) || 291 ((IsTex3d(resourceType) == TRUE) && 292 (m_swizzleModeTable[swizzleMode].isZ == FALSE) && 293 (m_swizzleModeTable[swizzleMode].isStd == FALSE))); 294 } 295 296 virtual BOOL_32 HwlIsThick( 297 AddrResourceType resourceType, 298 AddrSwizzleMode swizzleMode) const 299 { 300 return (IsTex3d(resourceType) && 301 (m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd)); 302 } 303 304 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 305 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 306 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 307 308 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 309 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 310 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 311 312 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 313 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 314 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 315 316 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 317 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 318 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 319 320 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 321 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 322 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 323 324 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 325 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 326 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 327 328 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 329 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 330 331 virtual VOID HwlComputeDccAddrFromCoord( 332 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 333 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 334 335 virtual UINT_32 HwlGetEquationIndex( 336 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 337 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 338 339 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 340 AddrResourceType rsrcType, 341 AddrSwizzleMode swMode, 342 UINT_32 elementBytesLog2, 343 ADDR_EQUATION* pEquation) const; 344 345 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 346 AddrResourceType rsrcType, 347 AddrSwizzleMode swMode, 348 UINT_32 elementBytesLog2, 349 ADDR_EQUATION* pEquation) const; 350 351 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 352 AddrResourceType rsrcType, 353 AddrSwizzleMode swMode, 354 UINT_32 elementBytesLog2, 355 ADDR_EQUATION* pEquation) const; 356 357 // Get equation table pointer and number of equations 358 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 359 { 360 *ppEquationTable = m_equationTable; 361 362 return m_numEquations; 363 } 364 365 virtual BOOL_32 IsEquationSupported( 366 AddrResourceType rsrcType, 367 AddrSwizzleMode swMode, 368 UINT_32 elementBytesLog2) const; 369 370 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 371 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 372 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 373 374 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 375 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 376 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 377 378 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 379 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 380 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 381 382 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 383 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 384 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 385 386 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 387 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 388 389 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 390 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 391 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 392 393 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 394 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 395 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 396 397 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 398 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 399 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 400 401 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 402 403 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 404 405 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 406 407 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 408 409 virtual VOID ComputeThinBlockDimension( 410 UINT_32* pWidth, 411 UINT_32* pHeight, 412 UINT_32* pDepth, 413 UINT_32 bpp, 414 UINT_32 numSamples, 415 AddrResourceType resourceType, 416 AddrSwizzleMode swizzleMode) const; 417 418private: 419 VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const; 420 421 VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType, 422 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 423 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const; 424 425 VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq, 426 UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2, 427 UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType, 428 AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const; 429 430 VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip, 431 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2, 432 ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType, 433 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 434 UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2, 435 UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2, 436 UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const; 437 438 const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams); 439 440 VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim, 441 BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo, 442 UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth, 443 UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const; 444 445 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 446 447 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding( 448 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 449 UINT_32* pMipmap0PaddedWidth, 450 UINT_32* pSlice0PaddedHeight, 451 ADDR2_MIP_INFO* pMipInfo = NULL) const; 452 453 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 454 { 455 ADDR2_BLOCK_SET allowedBlockSet = {}; 456 457 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE; 458 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE; 459 460 if (rsrcType == ADDR_RSRC_TEX_3D) 461 { 462 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin4KBSwModeMask) ? TRUE : FALSE; 463 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 464 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 465 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 466 } 467 else 468 { 469 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE; 470 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE; 471 } 472 473 return allowedBlockSet; 474 } 475 476 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 477 { 478 ADDR2_SWTYPE_SET allowedSwSet = {}; 479 480 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE; 481 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE; 482 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE; 483 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE; 484 485 return allowedSwSet; 486 } 487 488 BOOL_32 IsInMipTail( 489 AddrResourceType resourceType, 490 AddrSwizzleMode swizzleMode, 491 Dim3d mipTailDim, 492 UINT_32 width, 493 UINT_32 height, 494 UINT_32 depth) const 495 { 496 BOOL_32 inTail = ((width <= mipTailDim.w) && 497 (height <= mipTailDim.h) && 498 (IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d))); 499 500 return inTail; 501 } 502 503 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 504 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 505 506 UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const 507 { 508 UINT_32 pipeBits = GetPipeXorBits(macroBlockBits); 509 510 // Bank xor bits 511 UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2); 512 513 return bankBits; 514 } 515 516 UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const 517 { 518 UINT_32 baseAlign; 519 520 if (IsXor(swizzleMode)) 521 { 522 baseAlign = GetBlockSize(swizzleMode); 523 } 524 else 525 { 526 baseAlign = 256; 527 } 528 529 return baseAlign; 530 } 531 532 // Initialize equation table 533 VOID InitEquationTable(); 534 535 ADDR_E_RETURNCODE ComputeStereoInfo( 536 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 537 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 538 UINT_32* pHeightAlign) const; 539 540 UINT_32 GetMipChainInfo( 541 AddrResourceType resourceType, 542 AddrSwizzleMode swizzleMode, 543 UINT_32 bpp, 544 UINT_32 mip0Width, 545 UINT_32 mip0Height, 546 UINT_32 mip0Depth, 547 UINT_32 blockWidth, 548 UINT_32 blockHeight, 549 UINT_32 blockDepth, 550 UINT_32 numMipLevel, 551 ADDR2_MIP_INFO* pMipInfo) const; 552 553 VOID GetMetaMiptailInfo( 554 ADDR2_META_MIP_INFO* pInfo, 555 Dim3d mipCoord, 556 UINT_32 numMipInTail, 557 Dim3d* pMetaBlkDim) const; 558 559 Dim3d GetMipStartPos( 560 AddrResourceType resourceType, 561 AddrSwizzleMode swizzleMode, 562 UINT_32 width, 563 UINT_32 height, 564 UINT_32 depth, 565 UINT_32 blockWidth, 566 UINT_32 blockHeight, 567 UINT_32 blockDepth, 568 UINT_32 mipId, 569 UINT_32 log2ElementBytes, 570 UINT_32* pMipTailBytesOffset) const; 571 572 AddrMajorMode GetMajorMode( 573 AddrResourceType resourceType, 574 AddrSwizzleMode swizzleMode, 575 UINT_32 mip0WidthInBlk, 576 UINT_32 mip0HeightInBlk, 577 UINT_32 mip0DepthInBlk) const 578 { 579 BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk); 580 BOOL_32 xMajor = (yMajor == FALSE); 581 582 if (IsThick(resourceType, swizzleMode)) 583 { 584 yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk); 585 xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk); 586 } 587 588 AddrMajorMode majorMode; 589 if (xMajor) 590 { 591 majorMode = ADDR_MAJOR_X; 592 } 593 else if (yMajor) 594 { 595 majorMode = ADDR_MAJOR_Y; 596 } 597 else 598 { 599 majorMode = ADDR_MAJOR_Z; 600 } 601 602 return majorMode; 603 } 604 605 Dim3d GetDccCompressBlk( 606 AddrResourceType resourceType, 607 AddrSwizzleMode swizzleMode, 608 UINT_32 bpp) const 609 { 610 UINT_32 index = Log2(bpp >> 3); 611 Dim3d compressBlkDim; 612 613 if (IsThin(resourceType, swizzleMode)) 614 { 615 compressBlkDim.w = Block256_2d[index].w; 616 compressBlkDim.h = Block256_2d[index].h; 617 compressBlkDim.d = 1; 618 } 619 else if (IsStandardSwizzle(resourceType, swizzleMode)) 620 { 621 compressBlkDim = Block256_3dS[index]; 622 } 623 else 624 { 625 compressBlkDim = Block256_3dZ[index]; 626 } 627 628 return compressBlkDim; 629 } 630 631 static const UINT_32 MaxSeLog2 = 3; 632 static const UINT_32 MaxRbPerSeLog2 = 2; 633 634 static const Dim3d Block256_3dS[MaxNumOfBpp]; 635 static const Dim3d Block256_3dZ[MaxNumOfBpp]; 636 637 static const UINT_32 MipTailOffset256B[]; 638 639 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 640 641 static const UINT_32 MaxCachedMetaEq = 2; 642 643 Gfx9ChipSettings m_settings; 644 645 CoordEq m_cachedMetaEq[MaxCachedMetaEq]; 646 MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq]; 647 UINT_32 m_metaEqOverrideIndex; 648}; 649 650} // V2 651} // Addr 652 653#endif 654 655