1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 * Copyright 2020 Valve Corporation
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef AC_RGP_H
27#define AC_RGP_H
28
29#include <stdint.h>
30#include "compiler/shader_enums.h"
31#include "util/list.h"
32#include "util/simple_mtx.h"
33
34struct radeon_info;
35struct ac_thread_trace;
36struct ac_thread_trace_data;
37
38enum rgp_hardware_stages {
39   RGP_HW_STAGE_VS = 0,
40   RGP_HW_STAGE_LS,
41   RGP_HW_STAGE_HS,
42   RGP_HW_STAGE_ES,
43   RGP_HW_STAGE_GS,
44   RGP_HW_STAGE_PS,
45   RGP_HW_STAGE_CS,
46   RGP_HW_STAGE_MAX,
47};
48
49struct rgp_shader_data {
50   uint64_t hash[2];
51   uint32_t code_size;
52   uint8_t *code;
53   uint32_t vgpr_count;
54   uint32_t sgpr_count;
55   uint32_t scratch_memory_size;
56   uint32_t wavefront_size;
57   uint64_t base_address;
58   uint32_t elf_symbol_offset;
59   uint32_t hw_stage;
60   uint32_t is_combined;
61};
62
63struct rgp_code_object_record {
64   uint32_t shader_stages_mask;
65   struct rgp_shader_data shader_data[MESA_SHADER_STAGES];
66   uint32_t num_shaders_combined; /* count combined shaders as one count */
67   uint64_t pipeline_hash[2];
68   struct list_head list;
69};
70
71struct rgp_code_object {
72   uint32_t record_count;
73   struct list_head record;
74   simple_mtx_t lock;
75};
76
77enum rgp_loader_event_type
78{
79   RGP_LOAD_TO_GPU_MEMORY = 0,
80   RGP_UNLOAD_FROM_GPU_MEMORY,
81};
82
83struct rgp_loader_events_record {
84   uint32_t loader_event_type;
85   uint32_t reserved;
86   uint64_t base_address;
87   uint64_t code_object_hash[2];
88   uint64_t time_stamp;
89   struct list_head list;
90};
91
92struct rgp_loader_events {
93   uint32_t record_count;
94   struct list_head record;
95   simple_mtx_t lock;
96};
97
98struct rgp_pso_correlation_record {
99   uint64_t api_pso_hash;
100   uint64_t pipeline_hash[2];
101   char api_level_obj_name[64];
102   struct list_head list;
103};
104
105struct rgp_pso_correlation {
106   uint32_t record_count;
107   struct list_head record;
108   simple_mtx_t lock;
109};
110
111int
112ac_dump_rgp_capture(struct radeon_info *info,
113                    struct ac_thread_trace *thread_trace);
114
115void
116ac_rgp_file_write_elf_object(FILE *output, size_t file_elf_start,
117                             struct rgp_code_object_record *record,
118                             uint32_t *written_size, uint32_t flags);
119
120#endif
121