101e04c3fSmrg/* 201e04c3fSmrg * Copyright 2012 Advanced Micro Devices, Inc. 301e04c3fSmrg * 401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 501e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 601e04c3fSmrg * to deal in the Software without restriction, including without limitation 701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 901e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1001e04c3fSmrg * 1101e04c3fSmrg * The above copyright notice and this permission notice (including the next 1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1301e04c3fSmrg * Software. 1401e04c3fSmrg * 1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2101e04c3fSmrg * IN THE SOFTWARE. 2201e04c3fSmrg */ 2301e04c3fSmrg 2401e04c3fSmrg#ifndef AC_SHADER_UTIL_H 2501e04c3fSmrg#define AC_SHADER_UTIL_H 2601e04c3fSmrg 277ec681f3Smrg#include "ac_binary.h" 287ec681f3Smrg#include "amd_family.h" 297ec681f3Smrg#include "compiler/nir/nir.h" 307ec681f3Smrg#include "compiler/shader_enums.h" 317ec681f3Smrg 3201e04c3fSmrg#include <stdbool.h> 3301e04c3fSmrg#include <stdint.h> 3401e04c3fSmrg 357ec681f3Smrg#ifdef __cplusplus 367ec681f3Smrgextern "C" { 377ec681f3Smrg#endif 387ec681f3Smrg 397ec681f3Smrgenum ac_image_dim 407ec681f3Smrg{ 417ec681f3Smrg ac_image_1d, 427ec681f3Smrg ac_image_2d, 437ec681f3Smrg ac_image_3d, 447ec681f3Smrg ac_image_cube, // includes cube arrays 457ec681f3Smrg ac_image_1darray, 467ec681f3Smrg ac_image_2darray, 477ec681f3Smrg ac_image_2dmsaa, 487ec681f3Smrg ac_image_2darraymsaa, 497ec681f3Smrg}; 507ec681f3Smrg 517ec681f3Smrgstruct ac_data_format_info { 527ec681f3Smrg uint8_t element_size; 537ec681f3Smrg uint8_t num_channels; 547ec681f3Smrg uint8_t chan_byte_size; 557ec681f3Smrg uint8_t chan_format; 567ec681f3Smrg}; 577ec681f3Smrg 587ec681f3Smrgstruct ac_spi_color_formats { 597ec681f3Smrg unsigned normal : 8; 607ec681f3Smrg unsigned alpha : 8; 617ec681f3Smrg unsigned blend : 8; 627ec681f3Smrg unsigned blend_alpha : 8; 637ec681f3Smrg}; 647ec681f3Smrg 657ec681f3Smrg/* For ac_build_fetch_format. 667ec681f3Smrg * 677ec681f3Smrg * Note: FLOAT must be 0 (used for convenience of encoding in radeonsi). 687ec681f3Smrg */ 697ec681f3Smrgenum ac_fetch_format 707ec681f3Smrg{ 717ec681f3Smrg AC_FETCH_FORMAT_FLOAT = 0, 727ec681f3Smrg AC_FETCH_FORMAT_FIXED, 737ec681f3Smrg AC_FETCH_FORMAT_UNORM, 747ec681f3Smrg AC_FETCH_FORMAT_SNORM, 757ec681f3Smrg AC_FETCH_FORMAT_USCALED, 767ec681f3Smrg AC_FETCH_FORMAT_SSCALED, 777ec681f3Smrg AC_FETCH_FORMAT_UINT, 787ec681f3Smrg AC_FETCH_FORMAT_SINT, 797ec681f3Smrg AC_FETCH_FORMAT_NONE, 807ec681f3Smrg}; 817ec681f3Smrg 827ec681f3Smrgunsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask); 8301e04c3fSmrg 847ec681f3Smrgunsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format); 8501e04c3fSmrg 867ec681f3Smrguint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class); 8701e04c3fSmrg 887ec681f3Smrgunsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt); 8901e04c3fSmrg 907ec681f3Smrgconst struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt); 917ec681f3Smrg 927ec681f3Smrgenum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, 937ec681f3Smrg bool is_array); 947ec681f3Smrg 957ec681f3Smrgenum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim, 967ec681f3Smrg bool is_array); 977ec681f3Smrg 987ec681f3Smrgunsigned ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config, 997ec681f3Smrg signed char *face_vgpr_index, signed char *ancillary_vgpr_index); 1007ec681f3Smrg 1017ec681f3Smrgvoid ac_choose_spi_color_formats(unsigned format, unsigned swap, unsigned ntype, 1027ec681f3Smrg bool is_depth, bool use_rbplus, 1037ec681f3Smrg struct ac_spi_color_formats *formats); 1047ec681f3Smrg 1057ec681f3Smrgvoid ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling, 1067ec681f3Smrg bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask); 1077ec681f3Smrg 1087ec681f3Smrgunsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned max); 1097ec681f3Smrg 1107ec681f3Smrgunsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage, 1117ec681f3Smrg unsigned tess_num_patches, 1127ec681f3Smrg unsigned tess_patch_in_vtx, 1137ec681f3Smrg unsigned tess_patch_out_vtx); 1147ec681f3Smrg 1157ec681f3Smrgunsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size, 1167ec681f3Smrg unsigned es_verts, unsigned gs_inst_prims); 1177ec681f3Smrg 1187ec681f3Smrgunsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims, 1197ec681f3Smrg unsigned max_vtx_out, unsigned prim_amp_factor); 1207ec681f3Smrg 1217ec681f3Smrg#ifdef __cplusplus 1227ec681f3Smrg} 1237ec681f3Smrg#endif 12401e04c3fSmrg 12501e04c3fSmrg#endif 126