1/*
2 * Copyright © 2018 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef ACO_INSTRUCTION_SELECTION_H
26#define ACO_INSTRUCTION_SELECTION_H
27
28#include "aco_ir.h"
29
30#include "vulkan/radv_shader_args.h"
31
32#include <array>
33#include <unordered_map>
34#include <vector>
35
36namespace aco {
37
38struct shader_io_state {
39   uint8_t mask[VARYING_SLOT_MAX];
40   Temp temps[VARYING_SLOT_MAX * 4u];
41
42   shader_io_state()
43   {
44      memset(mask, 0, sizeof(mask));
45      std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1));
46   }
47};
48
49struct isel_context {
50   const struct radv_nir_compiler_options* options;
51   const struct radv_shader_args* args;
52   Program* program;
53   nir_shader* shader;
54   uint32_t constant_data_offset;
55   Block* block;
56   uint32_t first_temp_id;
57   std::unordered_map<unsigned, std::array<Temp, NIR_MAX_VEC_COMPONENTS>> allocated_vec;
58   Stage stage;
59   struct {
60      bool has_branch;
61      struct {
62         unsigned header_idx;
63         Block* exit;
64         bool has_divergent_continue = false;
65         bool has_divergent_branch = false;
66      } parent_loop;
67      struct {
68         bool is_divergent = false;
69      } parent_if;
70      bool exec_potentially_empty_discard =
71         false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
72      uint16_t exec_potentially_empty_break_depth = UINT16_MAX;
73      /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
74       * and parent_if.is_divergent==false. Called _break but it's also used for
75       * loop continues. */
76      bool exec_potentially_empty_break = false;
77      std::unique_ptr<unsigned[]> nir_to_aco; /* NIR block index to ACO block index */
78   } cf_info;
79
80   /* NIR range analysis. */
81   struct hash_table* range_ht;
82   nir_unsigned_upper_bound_config ub_config;
83
84   Temp arg_temps[AC_MAX_ARGS];
85
86   /* FS inputs */
87   Temp persp_centroid, linear_centroid;
88
89   /* GS inputs */
90   Temp gs_wave_id;
91
92   /* VS output information */
93   bool export_clip_dists;
94   unsigned num_clip_distances;
95   unsigned num_cull_distances;
96
97   /* tessellation information */
98   uint64_t tcs_temp_only_inputs;
99   uint32_t tcs_num_patches;
100   bool tcs_in_out_eq = false;
101
102   /* I/O information */
103   shader_io_state inputs;
104   shader_io_state outputs;
105};
106
107inline Temp
108get_arg(isel_context* ctx, struct ac_arg arg)
109{
110   assert(arg.used);
111   return ctx->arg_temps[arg.arg_index];
112}
113
114void init_context(isel_context* ctx, nir_shader* shader);
115void cleanup_context(isel_context* ctx);
116
117isel_context setup_isel_context(Program* program, unsigned shader_count,
118                                struct nir_shader* const* shaders, ac_shader_config* config,
119                                const struct radv_shader_args* args, bool is_gs_copy_shader);
120
121} // namespace aco
122
123#endif /* ACO_INSTRUCTION_SELECTION_H */
124