xref: /xsrc/external/mit/MesaLib/dist/src/amd/registers/pkt3.json

{
 "enums": {
  "COMMAND__SAIC": {
   "entries": [
    {"name": "INCREMENT", "value": 0},
    {"name": "NO_INCREMENT", "value": 1}
   ]
  },
  "COMMAND__SAS": {
   "entries": [
    {"name": "MEMORY", "value": 0},
    {"name": "REGISTER", "value": 1}
   ]
  },
  "COMMAND__SRC_SWAP": {
   "entries": [
    {"name": "NONE", "value": 0},
    {"name": "8_IN_16", "value": 1},
    {"name": "8_IN_32", "value": 2},
    {"name": "8_IN_64", "value": 3}
   ]
  },
  "CONTROL__DST_SEL": {
   "entries": [
    {"name": "MEM_MAPPED_REGISTER", "value": 0},
    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
    {"name": "TC_L2", "value": 2},
    {"name": "GDS", "value": 3},
    {"name": "RESERVED", "value": 4}
   ]
  },
  "CONTROL__DST_SEL_cik": {
   "entries": [
    {"name": "MEM_MAPPED_REGISTER", "value": 0},
    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
    {"name": "TC_L2", "value": 2},
    {"name": "GDS", "value": 3},
    {"name": "RESERVED", "value": 4},
    {"name": "MEM", "value": 5}
   ]
  },
  "CONTROL__ENGINE_SEL": {
   "entries": [
    {"name": "ME", "value": 0},
    {"name": "PFP", "value": 1},
    {"name": "CE", "value": 2},
    {"name": "DE", "value": 3}
   ]
  },
  "CP_DMA_WORD1__DST_SEL": {
   "entries": [
    {"name": "DST_ADDR", "value": 0},
    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
   ]
  },
  "CP_DMA_WORD1__DST_SEL_cik": {
   "entries": [
    {"name": "DST_ADDR", "value": 0},
    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
    {"name": "DST_ADDR_TC_L2", "value": 3}
   ]
  },
  "CP_DMA_WORD1__DST_SEL_gfx9": {
   "entries": [
    {"name": "DST_ADDR", "value": 0},
    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
    {"name": "NOWHERE", "value": 2},
    {"name": "DST_ADDR_TC_L2", "value": 3}
   ]
  },
  "CP_DMA_WORD1__ENGINE": {
   "entries": [
    {"name": "ME", "value": 0},
    {"name": "PFP", "value": 1}
   ]
  },
  "CP_DMA_WORD1__SRC_SEL": {
   "entries": [
    {"name": "SRC_ADDR", "value": 0},
    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
    {"name": "DATA", "value": 2}
   ]
  },
  "CP_DMA_WORD1__SRC_SEL_cik": {
   "entries": [
    {"name": "SRC_ADDR", "value": 0},
    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
    {"name": "DATA", "value": 2},
    {"name": "SRC_ADDR_TC_L2", "value": 3}
   ]
  },
  "GCR_GL1_RANGE": {
   "entries": [
    {"name": "GL1_ALL", "value": 0},
    {"name": "GL1_RANGE", "value": 2},
    {"name": "GL1_FIRST_LAST", "value": 3}
   ]
  },
  "GCR_GL2_RANGE": {
   "entries": [
    {"name": "GL2_ALL", "value": 0},
    {"name": "GL2_VOL", "value": 1},
    {"name": "GL2_RANGE", "value": 2},
    {"name": "GL2_FIRST_LAST", "value": 3}
   ]
  },
  "GCR_GLI_INV": {
   "entries": [
    {"name": "GLI_NOP", "value": 0},
    {"name": "GLI_ALL", "value": 1},
    {"name": "GLI_RANGE", "value": 2},
    {"name": "GLI_FIRST_LAST", "value": 3}
   ]
  },
  "GCR_SEQ": {
   "entries": [
    {"name": "SEQ_PARALLEL", "value": 0},
    {"name": "SEQ_FORWARD", "value": 1},
    {"name": "SEQ_REVERSE", "value": 2}
   ]
  }
 },
 "register_mappings": [
  {
   "comment": "This is at offset 0x415 instead of 0x414 due to a conflict with SQ_WAVE_GPR_ALLOC",
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
   "map": {"at": 1045, "to": "pkt3"},
   "name": "COMMAND",
   "type_ref": "COMMAND"
  },
  {
   "chips": ["gfx9", "gfx10", "gfx103"],
   "map": {"at": 1045, "to": "pkt3"},
   "name": "COMMAND",
   "type_ref": "COMMAND_gfx9"
  },
  {
   "chips": ["gfx6"],
   "map": {"at": 880, "to": "pkt3"},
   "name": "CONTROL",
   "type_ref": "CONTROL"
  },
  {
   "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 880, "to": "pkt3"},
   "name": "CONTROL",
   "type_ref": "CONTROL_cik"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1040, "to": "pkt3"},
   "name": "CP_DMA_WORD0",
   "type_ref": "CP_DMA_WORD0"
  },
  {
   "chips": ["gfx6"],
   "map": {"at": 1041, "to": "pkt3"},
   "name": "CP_DMA_WORD1",
   "type_ref": "CP_DMA_WORD1"
  },
  {
   "chips": ["gfx7", "gfx8", "gfx81"],
   "map": {"at": 1041, "to": "pkt3"},
   "name": "CP_DMA_WORD1",
   "type_ref": "CP_DMA_WORD1_cik"
  },
  {
   "chips": ["gfx9", "gfx10", "gfx103"],
   "map": {"at": 1041, "to": "pkt3"},
   "name": "CP_DMA_WORD1",
   "type_ref": "CP_DMA_WORD1_gfx9"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1042, "to": "pkt3"},
   "name": "CP_DMA_WORD2",
   "type_ref": "CP_DMA_WORD2"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1043, "to": "pkt3"},
   "name": "CP_DMA_WORD3",
   "type_ref": "CP_DMA_WORD3"
  },
  {
   "chips": ["gfx6"],
   "map": {"at": 1280, "to": "pkt3"},
   "name": "DMA_DATA_WORD0",
   "type_ref": "DMA_DATA_WORD0"
  },
  {
   "chips": ["gfx7", "gfx8", "gfx81"],
   "map": {"at": 1280, "to": "pkt3"},
   "name": "DMA_DATA_WORD0",
   "type_ref": "DMA_DATA_WORD0_cik"
  },
  {
   "chips": ["gfx9", "gfx10", "gfx103"],
   "map": {"at": 1280, "to": "pkt3"},
   "name": "DMA_DATA_WORD0",
   "type_ref": "DMA_DATA_WORD0_gfx9"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 882, "to": "pkt3"},
   "name": "DST_ADDR_HI"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1284, "to": "pkt3"},
   "name": "DST_ADDR_HI"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 881, "to": "pkt3"},
   "name": "DST_ADDR_LO"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1283, "to": "pkt3"},
   "name": "DST_ADDR_LO"
  },
  {
   "chips": ["gfx10", "gfx103"],
   "map": {"at": 1414, "to": "pkt3"},
   "name": "GCR_CNTL",
   "type_ref": "GCR_CNTL"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1009, "to": "pkt3"},
   "name": "IB_BASE_HI"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1008, "to": "pkt3"},
   "name": "IB_BASE_LO"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1010, "to": "pkt3"},
   "name": "IB_CONTROL",
   "type_ref": "IB_CONTROL"
  },
  {
   "chips": ["gfx10", "gfx103"],
   "map": {"at": 1168, "to": "pkt3"},
   "name": "RELEASE_MEM_OP",
   "type_ref": "RELEASE_MEM_OP"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1282, "to": "pkt3"},
   "name": "SRC_ADDR_HI"
  },
  {
   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
   "map": {"at": 1281, "to": "pkt3"},
   "name": "SRC_ADDR_LO"
  }
 ],
 "register_types": {
  "COMMAND": {
   "fields": [
    {"bits": [0, 20], "name": "BYTE_COUNT"},
    {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
    {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
    {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
    {"bits": [30, 30], "name": "RAW_WAIT"}
   ]
  },
  "COMMAND_gfx9": {
   "fields": [
    {"bits": [0, 25], "name": "BYTE_COUNT"},
    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
    {"bits": [30, 30], "name": "RAW_WAIT"},
    {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
   ]
  },
  "CONTROL": {
   "fields": [
    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
    {"bits": [20, 20], "name": "WR_CONFIRM"},
    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
   ]
  },
  "CONTROL_cik": {
   "fields": [
    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
    {"bits": [20, 20], "name": "WR_CONFIRM"},
    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
   ]
  },
  "CP_DMA_WORD0": {
   "fields": [
    {"bits": [0, 31], "name": "SRC_ADDR_LO"}
   ]
  },
  "CP_DMA_WORD1": {
   "fields": [
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "CP_DMA_WORD1_cik": {
   "fields": [
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "CP_DMA_WORD1_gfx9": {
   "fields": [
    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "CP_DMA_WORD2": {
   "fields": [
    {"bits": [0, 31], "name": "DST_ADDR_LO"}
   ]
  },
  "CP_DMA_WORD3": {
   "fields": [
    {"bits": [0, 15], "name": "DST_ADDR_HI"}
   ]
  },
  "DMA_DATA_WORD0": {
   "fields": [
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "DMA_DATA_WORD0_cik": {
   "fields": [
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "DMA_DATA_WORD0_gfx9": {
   "fields": [
    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
    {"bits": [31, 31], "name": "CP_SYNC"}
   ]
  },
  "GCR_CNTL": {
   "fields": [
    {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
    {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
    {"bits": [4, 4], "name": "GLM_WB"},
    {"bits": [5, 5], "name": "GLM_INV"},
    {"bits": [6, 6], "name": "GLK_WB"},
    {"bits": [7, 7], "name": "GLK_INV"},
    {"bits": [8, 8], "name": "GLV_INV"},
    {"bits": [9, 9], "name": "GL1_INV"},
    {"bits": [10, 10], "name": "GL2_US"},
    {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
    {"bits": [13, 13], "name": "GL2_DISCARD"},
    {"bits": [14, 14], "name": "GL2_INV"},
    {"bits": [15, 15], "name": "GL2_WB"},
    {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
    {"bits": [18, 18], "name": "RANGE_IS_PA"}
   ]
  },
  "IB_CONTROL": {
   "fields": [
    {"bits": [0, 19], "name": "IB_SIZE"},
    {"bits": [20, 20], "name": "CHAIN"},
    {"bits": [23, 23], "name": "VALID"}
   ]
  },
  "RELEASE_MEM_OP": {
   "fields": [
    {"bits": [0, 5], "name": "EVENT_TYPE"},
    {"bits": [8, 11], "name": "EVENT_INDEX"},
    {"bits": [12, 12], "name": "GLM_WB"},
    {"bits": [13, 13], "name": "GLM_INV"},
    {"bits": [14, 14], "name": "GLV_INV"},
    {"bits": [15, 15], "name": "GL1_INV"},
    {"bits": [16, 16], "name": "GL2_US"},
    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
    {"bits": [19, 19], "name": "GL2_DISCARD"},
    {"bits": [20, 20], "name": "GL2_INV"},
    {"bits": [21, 21], "name": "GL2_WB"},
    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
   ]
  }
 }
}