101e04c3fSmrg/* 201e04c3fSmrg * Copyright © 2016 Red Hat 301e04c3fSmrg * based on intel anv code: 401e04c3fSmrg * Copyright © 2015 Intel Corporation 501e04c3fSmrg * 601e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 701e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 801e04c3fSmrg * to deal in the Software without restriction, including without limitation 901e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1001e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 1101e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1201e04c3fSmrg * 1301e04c3fSmrg * The above copyright notice and this permission notice (including the next 1401e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1501e04c3fSmrg * Software. 1601e04c3fSmrg * 1701e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1801e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1901e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2001e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2101e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2201e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2301e04c3fSmrg * IN THE SOFTWARE. 2401e04c3fSmrg */ 2501e04c3fSmrg 2601e04c3fSmrg#ifndef RADV_META_H 2701e04c3fSmrg#define RADV_META_H 2801e04c3fSmrg 2901e04c3fSmrg#include "radv_private.h" 3001e04c3fSmrg#include "radv_shader.h" 3101e04c3fSmrg 3201e04c3fSmrg#ifdef __cplusplus 3301e04c3fSmrgextern "C" { 3401e04c3fSmrg#endif 3501e04c3fSmrg 3601e04c3fSmrgenum radv_meta_save_flags { 377ec681f3Smrg RADV_META_SAVE_PASS = (1 << 0), 387ec681f3Smrg RADV_META_SAVE_CONSTANTS = (1 << 1), 397ec681f3Smrg RADV_META_SAVE_DESCRIPTORS = (1 << 2), 407ec681f3Smrg RADV_META_SAVE_GRAPHICS_PIPELINE = (1 << 3), 417ec681f3Smrg RADV_META_SAVE_COMPUTE_PIPELINE = (1 << 4), 427ec681f3Smrg RADV_META_SAVE_SAMPLE_LOCATIONS = (1 << 5), 4301e04c3fSmrg}; 4401e04c3fSmrg 4501e04c3fSmrgstruct radv_meta_saved_state { 467ec681f3Smrg uint32_t flags; 477ec681f3Smrg 487ec681f3Smrg struct radv_descriptor_set *old_descriptor_set0; 497ec681f3Smrg struct radv_pipeline *old_pipeline; 507ec681f3Smrg struct radv_viewport_state viewport; 517ec681f3Smrg struct radv_scissor_state scissor; 527ec681f3Smrg struct radv_sample_locations_state sample_location; 537ec681f3Smrg 547ec681f3Smrg char push_constants[128]; 557ec681f3Smrg 567ec681f3Smrg struct radv_render_pass *pass; 577ec681f3Smrg const struct radv_subpass *subpass; 587ec681f3Smrg struct radv_attachment_state *attachments; 597ec681f3Smrg struct radv_framebuffer *framebuffer; 607ec681f3Smrg VkRect2D render_area; 617ec681f3Smrg 627ec681f3Smrg VkCullModeFlags cull_mode; 637ec681f3Smrg VkFrontFace front_face; 647ec681f3Smrg 657ec681f3Smrg unsigned primitive_topology; 667ec681f3Smrg 677ec681f3Smrg bool depth_test_enable; 687ec681f3Smrg bool depth_write_enable; 697ec681f3Smrg unsigned depth_compare_op; 707ec681f3Smrg bool depth_bounds_test_enable; 717ec681f3Smrg bool stencil_test_enable; 727ec681f3Smrg 737ec681f3Smrg struct { 747ec681f3Smrg struct { 757ec681f3Smrg VkStencilOp fail_op; 767ec681f3Smrg VkStencilOp pass_op; 777ec681f3Smrg VkStencilOp depth_fail_op; 787ec681f3Smrg VkCompareOp compare_op; 797ec681f3Smrg } front; 807ec681f3Smrg 817ec681f3Smrg struct { 827ec681f3Smrg VkStencilOp fail_op; 837ec681f3Smrg VkStencilOp pass_op; 847ec681f3Smrg VkStencilOp depth_fail_op; 857ec681f3Smrg VkCompareOp compare_op; 867ec681f3Smrg } back; 877ec681f3Smrg } stencil_op; 887ec681f3Smrg 897ec681f3Smrg struct { 907ec681f3Smrg VkExtent2D size; 917ec681f3Smrg VkFragmentShadingRateCombinerOpKHR combiner_ops[2]; 927ec681f3Smrg } fragment_shading_rate; 937ec681f3Smrg 947ec681f3Smrg bool depth_bias_enable; 957ec681f3Smrg bool primitive_restart_enable; 967ec681f3Smrg bool rasterizer_discard_enable; 977ec681f3Smrg 987ec681f3Smrg unsigned logic_op; 997ec681f3Smrg 1007ec681f3Smrg uint32_t color_write_enable; 10101e04c3fSmrg}; 10201e04c3fSmrg 10301e04c3fSmrgVkResult radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand); 10401e04c3fSmrgvoid radv_device_finish_meta_clear_state(struct radv_device *device); 10501e04c3fSmrg 10601e04c3fSmrgVkResult radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand); 10701e04c3fSmrgvoid radv_device_finish_meta_resolve_state(struct radv_device *device); 10801e04c3fSmrg 10901e04c3fSmrgVkResult radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_demand); 11001e04c3fSmrgvoid radv_device_finish_meta_depth_decomp_state(struct radv_device *device); 11101e04c3fSmrg 11201e04c3fSmrgVkResult radv_device_init_meta_fast_clear_flush_state(struct radv_device *device, bool on_demand); 11301e04c3fSmrgvoid radv_device_finish_meta_fast_clear_flush_state(struct radv_device *device); 11401e04c3fSmrg 11501e04c3fSmrgVkResult radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand); 11601e04c3fSmrgvoid radv_device_finish_meta_blit_state(struct radv_device *device); 11701e04c3fSmrg 11801e04c3fSmrgVkResult radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand); 11901e04c3fSmrgvoid radv_device_finish_meta_blit2d_state(struct radv_device *device); 12001e04c3fSmrg 12101e04c3fSmrgVkResult radv_device_init_meta_buffer_state(struct radv_device *device); 12201e04c3fSmrgvoid radv_device_finish_meta_buffer_state(struct radv_device *device); 12301e04c3fSmrg 12401e04c3fSmrgVkResult radv_device_init_meta_query_state(struct radv_device *device, bool on_demand); 12501e04c3fSmrgvoid radv_device_finish_meta_query_state(struct radv_device *device); 12601e04c3fSmrg 12701e04c3fSmrgVkResult radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_demand); 12801e04c3fSmrgvoid radv_device_finish_meta_resolve_compute_state(struct radv_device *device); 12901e04c3fSmrg 13001e04c3fSmrgVkResult radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand); 13101e04c3fSmrgvoid radv_device_finish_meta_resolve_fragment_state(struct radv_device *device); 13201e04c3fSmrg 133ed98bd31SmayaVkResult radv_device_init_meta_fmask_expand_state(struct radv_device *device); 134ed98bd31Smayavoid radv_device_finish_meta_fmask_expand_state(struct radv_device *device); 135ed98bd31Smaya 1367ec681f3Smrgvoid radv_device_finish_meta_dcc_retile_state(struct radv_device *device); 1377ec681f3Smrg 1387ec681f3Smrgvoid radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device); 1397ec681f3Smrg 1407ec681f3SmrgVkResult radv_device_init_accel_struct_build_state(struct radv_device *device); 1417ec681f3Smrgvoid radv_device_finish_accel_struct_build_state(struct radv_device *device); 1427ec681f3Smrg 1437ec681f3Smrgvoid radv_meta_save(struct radv_meta_saved_state *saved_state, struct radv_cmd_buffer *cmd_buffer, 1447ec681f3Smrg uint32_t flags); 14501e04c3fSmrg 14601e04c3fSmrgvoid radv_meta_restore(const struct radv_meta_saved_state *state, 1477ec681f3Smrg struct radv_cmd_buffer *cmd_buffer); 14801e04c3fSmrg 14901e04c3fSmrgVkImageViewType radv_meta_get_view_type(const struct radv_image *image); 15001e04c3fSmrg 15101e04c3fSmrguint32_t radv_meta_get_iview_layer(const struct radv_image *dest_image, 1527ec681f3Smrg const VkImageSubresourceLayers *dest_subresource, 1537ec681f3Smrg const VkOffset3D *dest_offset); 15401e04c3fSmrg 15501e04c3fSmrgstruct radv_meta_blit2d_surf { 1567ec681f3Smrg /** The size of an element in bytes. */ 1577ec681f3Smrg uint8_t bs; 1587ec681f3Smrg VkFormat format; 1597ec681f3Smrg 1607ec681f3Smrg struct radv_image *image; 1617ec681f3Smrg unsigned level; 1627ec681f3Smrg unsigned layer; 1637ec681f3Smrg VkImageAspectFlags aspect_mask; 1647ec681f3Smrg VkImageLayout current_layout; 1657ec681f3Smrg bool disable_compression; 16601e04c3fSmrg}; 16701e04c3fSmrg 16801e04c3fSmrgstruct radv_meta_blit2d_buffer { 1697ec681f3Smrg struct radv_buffer *buffer; 1707ec681f3Smrg uint32_t offset; 1717ec681f3Smrg uint32_t pitch; 1727ec681f3Smrg uint8_t bs; 1737ec681f3Smrg VkFormat format; 17401e04c3fSmrg}; 17501e04c3fSmrg 17601e04c3fSmrgstruct radv_meta_blit2d_rect { 1777ec681f3Smrg uint32_t src_x, src_y; 1787ec681f3Smrg uint32_t dst_x, dst_y; 1797ec681f3Smrg uint32_t width, height; 18001e04c3fSmrg}; 18101e04c3fSmrg 1827ec681f3Smrgvoid radv_meta_begin_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save); 18301e04c3fSmrg 1847ec681f3Smrgvoid radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src_img, 1857ec681f3Smrg struct radv_meta_blit2d_buffer *src_buf, struct radv_meta_blit2d_surf *dst, 1867ec681f3Smrg unsigned num_rects, struct radv_meta_blit2d_rect *rects); 18701e04c3fSmrg 1887ec681f3Smrgvoid radv_meta_end_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_saved_state *save); 18901e04c3fSmrg 19001e04c3fSmrgVkResult radv_device_init_meta_bufimage_state(struct radv_device *device); 19101e04c3fSmrgvoid radv_device_finish_meta_bufimage_state(struct radv_device *device); 19201e04c3fSmrgvoid radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, 1937ec681f3Smrg struct radv_meta_blit2d_surf *src, 1947ec681f3Smrg struct radv_meta_blit2d_buffer *dst, unsigned num_rects, 1957ec681f3Smrg struct radv_meta_blit2d_rect *rects); 19601e04c3fSmrg 19701e04c3fSmrgvoid radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, 1987ec681f3Smrg struct radv_meta_blit2d_buffer *src, 1997ec681f3Smrg struct radv_meta_blit2d_surf *dst, unsigned num_rects, 2007ec681f3Smrg struct radv_meta_blit2d_rect *rects); 20101e04c3fSmrgvoid radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, 2027ec681f3Smrg struct radv_meta_blit2d_surf *src, 2037ec681f3Smrg struct radv_meta_blit2d_surf *dst, unsigned num_rects, 2047ec681f3Smrg struct radv_meta_blit2d_rect *rects); 2057ec681f3Smrgvoid radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *dst, 2067ec681f3Smrg const VkClearColorValue *clear_color); 2077ec681f3Smrg 2087ec681f3Smrgvoid radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2097ec681f3Smrg const VkImageSubresourceRange *subresourceRange, 2107ec681f3Smrg struct radv_sample_locations_state *sample_locs); 2117ec681f3Smrgvoid radv_resummarize_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2127ec681f3Smrg const VkImageSubresourceRange *subresourceRange, 2137ec681f3Smrg struct radv_sample_locations_state *sample_locs); 21401e04c3fSmrgvoid radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer, 2157ec681f3Smrg struct radv_image *image, 2167ec681f3Smrg const VkImageSubresourceRange *subresourceRange); 2177ec681f3Smrgvoid radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2187ec681f3Smrg const VkImageSubresourceRange *subresourceRange); 2197ec681f3Smrgvoid radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image); 2207ec681f3Smrgvoid radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2217ec681f3Smrg const VkImageSubresourceRange *subresourceRange); 2227ec681f3Smrgvoid radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, 2237ec681f3Smrg VkExtent2D *extent, struct radv_image *dst_image, 2247ec681f3Smrg struct radv_buffer *htile_buffer, bool read_htile_value); 22501e04c3fSmrg 22601e04c3fSmrgvoid radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, 2277ec681f3Smrg struct radv_image *src_image, VkFormat src_format, 2287ec681f3Smrg VkImageLayout src_image_layout, struct radv_image *dest_image, 2297ec681f3Smrg VkFormat dest_format, VkImageLayout dest_image_layout, 2307ec681f3Smrg const VkImageResolve2KHR *region); 23101e04c3fSmrg 23201e04c3fSmrgvoid radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, 2337ec681f3Smrg struct radv_image *src_image, VkImageLayout src_image_layout, 2347ec681f3Smrg struct radv_image *dest_image, 2357ec681f3Smrg VkImageLayout dest_image_layout, 2367ec681f3Smrg const VkImageResolve2KHR *region); 23701e04c3fSmrg 23801e04c3fSmrgvoid radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer); 23901e04c3fSmrg 2407ec681f3Smrgvoid radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, 2417ec681f3Smrg VkImageLayout src_image_layout, const VkImageResolve2KHR *region); 2427ec681f3Smrg 2437ec681f3Smrguint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2447ec681f3Smrg const VkImageSubresourceRange *range, uint32_t value); 2457ec681f3Smrguint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2467ec681f3Smrg const VkImageSubresourceRange *range, uint32_t value); 2477ec681f3Smrguint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, 2487ec681f3Smrg const VkImageSubresourceRange *range, uint32_t value); 2497ec681f3Smrguint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, 2507ec681f3Smrg const VkImageSubresourceRange *range, uint32_t value); 2517ec681f3Smrg 2527ec681f3Smrgvoid radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, 2537ec681f3Smrg uint64_t size); 25401e04c3fSmrg 2557ec681f3Smrg/** 2567ec681f3Smrg * Return whether the bound pipeline is the FMASK decompress pass. 2577ec681f3Smrg */ 2587ec681f3Smrgstatic inline bool 2597ec681f3Smrgradv_is_fmask_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer) 2607ec681f3Smrg{ 2617ec681f3Smrg struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; 2627ec681f3Smrg struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; 2637ec681f3Smrg 2647ec681f3Smrg return radv_pipeline_to_handle(pipeline) == 2657ec681f3Smrg meta_state->fast_clear_flush.fmask_decompress_pipeline; 2667ec681f3Smrg} 2677ec681f3Smrg 2687ec681f3Smrg/** 2697ec681f3Smrg * Return whether the bound pipeline is the DCC decompress pass. 2707ec681f3Smrg */ 2717ec681f3Smrgstatic inline bool 2727ec681f3Smrgradv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer) 2737ec681f3Smrg{ 2747ec681f3Smrg struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state; 2757ec681f3Smrg struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; 2767ec681f3Smrg 2777ec681f3Smrg return radv_pipeline_to_handle(pipeline) == meta_state->fast_clear_flush.dcc_decompress_pipeline; 2787ec681f3Smrg} 27901e04c3fSmrg 28001e04c3fSmrg/* common nir builder helpers */ 28101e04c3fSmrg#include "nir/nir_builder.h" 28201e04c3fSmrg 28301e04c3fSmrgnir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b); 28401e04c3fSmrgnir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2); 28501e04c3fSmrgnir_shader *radv_meta_build_nir_vs_generate_vertices(void); 28601e04c3fSmrgnir_shader *radv_meta_build_nir_fs_noop(void); 28701e04c3fSmrg 2887ec681f3Smrgvoid radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples, 2897ec681f3Smrg nir_variable *input_img, nir_variable *color, 2907ec681f3Smrg nir_ssa_def *img_coord); 2917ec681f3Smrg 2927ec681f3Smrgnir_ssa_def *radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding); 2937ec681f3Smrg 2947ec681f3Smrgnir_ssa_def *get_global_ids(nir_builder *b, unsigned num_components); 2957ec681f3Smrg 29601e04c3fSmrg#ifdef __cplusplus 29701e04c3fSmrg} 29801e04c3fSmrg#endif 29901e04c3fSmrg 30001e04c3fSmrg#endif /* RADV_META_H */ 301