1/*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "nir.h"
25
26static bool
27assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
28{
29   assert(def->bit_size > 1);
30   return true;
31}
32
33static bool
34rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
35{
36   bool *progress = _progress;
37   if (def->bit_size == 1) {
38      def->bit_size = 32;
39      *progress = true;
40   }
41   return true;
42}
43
44static bool
45lower_alu_instr(nir_alu_instr *alu)
46{
47   const nir_op_info *op_info = &nir_op_infos[alu->op];
48
49   assert(alu->dest.dest.is_ssa);
50
51   switch (alu->op) {
52   case nir_op_mov:
53   case nir_op_vec2:
54   case nir_op_vec3:
55   case nir_op_vec4:
56   case nir_op_vec5:
57   case nir_op_vec8:
58   case nir_op_vec16:
59   case nir_op_inot:
60   case nir_op_iand:
61   case nir_op_ior:
62   case nir_op_ixor:
63      if (alu->dest.dest.ssa.bit_size != 1)
64         return false;
65      /* These we expect to have booleans but the opcode doesn't change */
66      break;
67
68   case nir_op_f2b1: alu->op = nir_op_f2b32; break;
69   case nir_op_i2b1: alu->op = nir_op_i2b32; break;
70
71   case nir_op_b2b32:
72   case nir_op_b2b1:
73      /* We're mutating instructions in a dominance-preserving order so our
74       * source boolean should be 32-bit by now.
75       */
76      assert(nir_src_bit_size(alu->src[0].src) == 32);
77      alu->op = nir_op_mov;
78      break;
79
80   case nir_op_flt: alu->op = nir_op_flt32; break;
81   case nir_op_fge: alu->op = nir_op_fge32; break;
82   case nir_op_feq: alu->op = nir_op_feq32; break;
83   case nir_op_fneu: alu->op = nir_op_fneu32; break;
84   case nir_op_ilt: alu->op = nir_op_ilt32; break;
85   case nir_op_ige: alu->op = nir_op_ige32; break;
86   case nir_op_ieq: alu->op = nir_op_ieq32; break;
87   case nir_op_ine: alu->op = nir_op_ine32; break;
88   case nir_op_ult: alu->op = nir_op_ult32; break;
89   case nir_op_uge: alu->op = nir_op_uge32; break;
90
91   case nir_op_ball_fequal2:  alu->op = nir_op_b32all_fequal2; break;
92   case nir_op_ball_fequal3:  alu->op = nir_op_b32all_fequal3; break;
93   case nir_op_ball_fequal4:  alu->op = nir_op_b32all_fequal4; break;
94   case nir_op_bany_fnequal2: alu->op = nir_op_b32any_fnequal2; break;
95   case nir_op_bany_fnequal3: alu->op = nir_op_b32any_fnequal3; break;
96   case nir_op_bany_fnequal4: alu->op = nir_op_b32any_fnequal4; break;
97   case nir_op_ball_iequal2:  alu->op = nir_op_b32all_iequal2; break;
98   case nir_op_ball_iequal3:  alu->op = nir_op_b32all_iequal3; break;
99   case nir_op_ball_iequal4:  alu->op = nir_op_b32all_iequal4; break;
100   case nir_op_bany_inequal2: alu->op = nir_op_b32any_inequal2; break;
101   case nir_op_bany_inequal3: alu->op = nir_op_b32any_inequal3; break;
102   case nir_op_bany_inequal4: alu->op = nir_op_b32any_inequal4; break;
103
104   case nir_op_bcsel: alu->op = nir_op_b32csel; break;
105
106   case nir_op_fisfinite: alu->op = nir_op_fisfinite32; break;
107
108   default:
109      assert(alu->dest.dest.ssa.bit_size > 1);
110      for (unsigned i = 0; i < op_info->num_inputs; i++)
111         assert(alu->src[i].src.ssa->bit_size > 1);
112      return false;
113   }
114
115   if (alu->dest.dest.ssa.bit_size == 1)
116      alu->dest.dest.ssa.bit_size = 32;
117
118   return true;
119}
120
121static bool
122lower_tex_instr(nir_tex_instr *tex)
123{
124   bool progress = false;
125   rewrite_1bit_ssa_def_to_32bit(&tex->dest.ssa, &progress);
126   if (tex->dest_type == nir_type_bool1) {
127      tex->dest_type = nir_type_bool32;
128      progress = true;
129   }
130   return progress;
131}
132
133static bool
134nir_lower_bool_to_int32_impl(nir_function_impl *impl)
135{
136   bool progress = false;
137
138   nir_foreach_block(block, impl) {
139      nir_foreach_instr_safe(instr, block) {
140         switch (instr->type) {
141         case nir_instr_type_alu:
142            progress |= lower_alu_instr(nir_instr_as_alu(instr));
143            break;
144
145         case nir_instr_type_load_const: {
146            nir_load_const_instr *load = nir_instr_as_load_const(instr);
147            if (load->def.bit_size == 1) {
148               nir_const_value *value = load->value;
149               for (unsigned i = 0; i < load->def.num_components; i++)
150                  load->value[i].u32 = value[i].b ? NIR_TRUE : NIR_FALSE;
151               load->def.bit_size = 32;
152               progress = true;
153            }
154            break;
155         }
156
157         case nir_instr_type_intrinsic:
158         case nir_instr_type_ssa_undef:
159         case nir_instr_type_phi:
160            nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
161                                &progress);
162            break;
163
164         case nir_instr_type_tex:
165            progress |= lower_tex_instr(nir_instr_as_tex(instr));
166            break;
167
168         default:
169            nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
170         }
171      }
172   }
173
174   if (progress) {
175      nir_metadata_preserve(impl, nir_metadata_block_index |
176                                  nir_metadata_dominance);
177   } else {
178      nir_metadata_preserve(impl, nir_metadata_all);
179   }
180
181   return progress;
182}
183
184bool
185nir_lower_bool_to_int32(nir_shader *shader)
186{
187   bool progress = false;
188
189   nir_foreach_function(function, shader) {
190      if (function->impl && nir_lower_bool_to_int32_impl(function->impl))
191         progress = true;
192   }
193
194   return progress;
195}
196