17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2016 Intel Corporation 37ec681f3Smrg * Copyright © 2019 Valve Corporation 47ec681f3Smrg * 57ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 67ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 77ec681f3Smrg * to deal in the Software without restriction, including without limitation 87ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 97ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 107ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 117ec681f3Smrg * 127ec681f3Smrg * The above copyright notice and this permission notice (including the next 137ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 147ec681f3Smrg * Software. 157ec681f3Smrg * 167ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 177ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 187ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 197ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 207ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 217ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 227ec681f3Smrg * IN THE SOFTWARE. 237ec681f3Smrg */ 247ec681f3Smrg 257ec681f3Smrg#include "nir.h" 267ec681f3Smrg 277ec681f3Smrg/** 287ec681f3Smrg * \file nir_opt_move.c 297ec681f3Smrg * 307ec681f3Smrg * This pass can move various operations just before their first use inside the 317ec681f3Smrg * same basic block. Usually this is to reduce register usage. It's probably 327ec681f3Smrg * not a good idea to use this in an optimization loop. 337ec681f3Smrg * 347ec681f3Smrg * Moving comparisons is useful because many GPUs generate condition codes 357ec681f3Smrg * for comparisons, and use predication for conditional selects and control 367ec681f3Smrg * flow. In a sequence such as: 377ec681f3Smrg * 387ec681f3Smrg * vec1 32 ssa_1 = flt a b 397ec681f3Smrg * <some other operations> 407ec681f3Smrg * vec1 32 ssa_2 = bcsel ssa_1 c d 417ec681f3Smrg * 427ec681f3Smrg * the backend would likely do the comparison, producing condition codes, 437ec681f3Smrg * then save those to a boolean value. The intervening operations might 447ec681f3Smrg * trash the condition codes. Then, in order to do the bcsel, it would 457ec681f3Smrg * need to re-populate the condition code register based on the boolean. 467ec681f3Smrg * 477ec681f3Smrg * By moving the comparison just before the bcsel, the condition codes could 487ec681f3Smrg * be used directly. This eliminates the need to reload them from the boolean 497ec681f3Smrg * (generally eliminating an instruction). It may also eliminate the need to 507ec681f3Smrg * create a boolean value altogether (unless it's used elsewhere), which could 517ec681f3Smrg * lower register pressure. 527ec681f3Smrg */ 537ec681f3Smrg 547ec681f3Smrgstatic bool 557ec681f3Smrgmove_source(nir_src *src, nir_block *block, nir_instr *before, nir_move_options options) 567ec681f3Smrg{ 577ec681f3Smrg if (!src->is_ssa) 587ec681f3Smrg return false; 597ec681f3Smrg 607ec681f3Smrg nir_instr *src_instr = src->ssa->parent_instr; 617ec681f3Smrg 627ec681f3Smrg if (src_instr->block == block && nir_can_move_instr(src_instr, options)) { 637ec681f3Smrg exec_node_remove(&src_instr->node); 647ec681f3Smrg 657ec681f3Smrg if (before) 667ec681f3Smrg exec_node_insert_node_before(&before->node, &src_instr->node); 677ec681f3Smrg else 687ec681f3Smrg exec_list_push_tail(&block->instr_list, &src_instr->node); 697ec681f3Smrg 707ec681f3Smrg return true; 717ec681f3Smrg } 727ec681f3Smrg return false; 737ec681f3Smrg} 747ec681f3Smrg 757ec681f3Smrgstruct source_cb_data { 767ec681f3Smrg bool *progress; 777ec681f3Smrg nir_move_options options; 787ec681f3Smrg}; 797ec681f3Smrg 807ec681f3Smrgstatic bool 817ec681f3Smrgmove_source_cb(nir_src *src, void *data_ptr) 827ec681f3Smrg{ 837ec681f3Smrg struct source_cb_data data = *(struct source_cb_data*)data_ptr; 847ec681f3Smrg 857ec681f3Smrg nir_instr *instr = src->parent_instr; 867ec681f3Smrg if (move_source(src, instr->block, instr, data.options)) 877ec681f3Smrg *data.progress = true; 887ec681f3Smrg 897ec681f3Smrg return true; /* nir_foreach_src should keep going */ 907ec681f3Smrg} 917ec681f3Smrg 927ec681f3Smrgstatic bool 937ec681f3Smrgmove(nir_block *block, nir_move_options options) 947ec681f3Smrg{ 957ec681f3Smrg bool progress = false; 967ec681f3Smrg 977ec681f3Smrg /* We use a simple approach: walk instructions backwards. 987ec681f3Smrg * 997ec681f3Smrg * If the instruction's source is a comparison from the same block, 1007ec681f3Smrg * simply move it here. This may break SSA if it's used earlier in 1017ec681f3Smrg * the block as well. However, as we walk backwards, we'll find the 1027ec681f3Smrg * earlier use and move it again, further up. It eventually ends up 1037ec681f3Smrg * dominating all uses again, restoring SSA form. 1047ec681f3Smrg * 1057ec681f3Smrg * Before walking instructions, we consider the if-condition at the 1067ec681f3Smrg * end of the block, if one exists. It's effectively a use at the 1077ec681f3Smrg * bottom of the block. 1087ec681f3Smrg */ 1097ec681f3Smrg nir_if *iff = nir_block_get_following_if(block); 1107ec681f3Smrg if (iff) { 1117ec681f3Smrg progress |= move_source(&iff->condition, block, NULL, options); 1127ec681f3Smrg } 1137ec681f3Smrg 1147ec681f3Smrg nir_foreach_instr_reverse(instr, block) { 1157ec681f3Smrg /* The sources of phi instructions happen after the predecessor block 1167ec681f3Smrg * but before this block. (Yes, that's between blocks). This means 1177ec681f3Smrg * that we don't need to move them in order for them to be correct. 1187ec681f3Smrg * We could move them to encourage comparisons that are used in a phi to 1197ec681f3Smrg * the end of the block, doing so correctly would make the pass 1207ec681f3Smrg * substantially more complicated and wouldn't gain us anything since 1217ec681f3Smrg * the phi can't use a flag value anyway. 1227ec681f3Smrg */ 1237ec681f3Smrg 1247ec681f3Smrg if (instr->type == nir_instr_type_phi) { 1257ec681f3Smrg /* We're going backwards so everything else is a phi too */ 1267ec681f3Smrg break; 1277ec681f3Smrg } else if (instr->type == nir_instr_type_alu) { 1287ec681f3Smrg /* Walk ALU instruction sources backwards so that bcsel's boolean 1297ec681f3Smrg * condition is processed last for when comparisons are being moved. 1307ec681f3Smrg */ 1317ec681f3Smrg nir_alu_instr *alu = nir_instr_as_alu(instr); 1327ec681f3Smrg for (int i = nir_op_infos[alu->op].num_inputs - 1; i >= 0; i--) { 1337ec681f3Smrg progress |= move_source(&alu->src[i].src, block, instr, options); 1347ec681f3Smrg } 1357ec681f3Smrg } else { 1367ec681f3Smrg struct source_cb_data data; 1377ec681f3Smrg data.progress = &progress; 1387ec681f3Smrg data.options = options; 1397ec681f3Smrg nir_foreach_src(instr, move_source_cb, &data); 1407ec681f3Smrg } 1417ec681f3Smrg } 1427ec681f3Smrg 1437ec681f3Smrg return progress; 1447ec681f3Smrg} 1457ec681f3Smrg 1467ec681f3Smrgbool 1477ec681f3Smrgnir_opt_move(nir_shader *shader, nir_move_options options) 1487ec681f3Smrg{ 1497ec681f3Smrg bool progress = false; 1507ec681f3Smrg 1517ec681f3Smrg nir_foreach_function(func, shader) { 1527ec681f3Smrg if (!func->impl) 1537ec681f3Smrg continue; 1547ec681f3Smrg 1557ec681f3Smrg bool impl_progress = false; 1567ec681f3Smrg nir_foreach_block(block, func->impl) { 1577ec681f3Smrg if (move(block, options)) 1587ec681f3Smrg impl_progress = true; 1597ec681f3Smrg } 1607ec681f3Smrg 1617ec681f3Smrg if (impl_progress) { 1627ec681f3Smrg nir_metadata_preserve(func->impl, nir_metadata_block_index | 1637ec681f3Smrg nir_metadata_dominance | 1647ec681f3Smrg nir_metadata_live_ssa_defs); 1657ec681f3Smrg progress = true; 1667ec681f3Smrg } else { 1677ec681f3Smrg nir_metadata_preserve(func->impl, nir_metadata_all); 1687ec681f3Smrg } 1697ec681f3Smrg } 1707ec681f3Smrg 1717ec681f3Smrg return progress; 1727ec681f3Smrg} 173