17ec681f3Smrg/* 27ec681f3Smrg * Copyright (c) 2019 Etnaviv Project 37ec681f3Smrg * Copyright (c) 2019 Zodiac Inflight Innovations 47ec681f3Smrg * 57ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 67ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 77ec681f3Smrg * to deal in the Software without restriction, including without limitation 87ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sub license, 97ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 107ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 117ec681f3Smrg * 127ec681f3Smrg * The above copyright notice and this permission notice (including the 137ec681f3Smrg * next paragraph) shall be included in all copies or substantial portions 147ec681f3Smrg * of the Software. 157ec681f3Smrg * 167ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 177ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 187ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 197ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 207ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 217ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 227ec681f3Smrg * DEALINGS IN THE SOFTWARE. 237ec681f3Smrg * 247ec681f3Smrg * Authors: 257ec681f3Smrg * Christian Gmeiner <christian.gmeiner@gmail.com> 267ec681f3Smrg */ 277ec681f3Smrg 287ec681f3Smrg#include <stdio.h> 297ec681f3Smrg#include <sys/ioctl.h> 307ec681f3Smrg#include "drm-uapi/etnaviv_drm.h" 317ec681f3Smrg#include "drm-shim/drm_shim.h" 327ec681f3Smrg#include "util/u_debug.h" 337ec681f3Smrg 347ec681f3Smrgbool drm_shim_driver_prefers_first_render_node = true; 357ec681f3Smrg 367ec681f3Smrgstruct etna_shim_gpu 377ec681f3Smrg{ 387ec681f3Smrg const char *name; 397ec681f3Smrg const uint64_t *reg_map; 407ec681f3Smrg}; 417ec681f3Smrg 427ec681f3Smrgstatic const struct etna_shim_gpu gpus[] = { 437ec681f3Smrg { 447ec681f3Smrg .name = "GC400", 457ec681f3Smrg .reg_map = (const uint64_t[]){ 467ec681f3Smrg [ETNAVIV_PARAM_GPU_MODEL] = 0x400, 477ec681f3Smrg [ETNAVIV_PARAM_GPU_REVISION] = 0x4652, 487ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_0] = 0xa0e9e004, 497ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_1] = 0xe1299fff, 507ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_2] = 0xbe13b219, 517ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_3] = 0xce110010, 527ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_4] = 0x8000001, 537ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_5] = 0x20102, 547ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_6] = 0x120000, 557ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_7] = 0x0, 567ec681f3Smrg [ETNAVIV_PARAM_GPU_STREAM_COUNT] = 0x4, 577ec681f3Smrg [ETNAVIV_PARAM_GPU_REGISTER_MAX] = 0x40, 587ec681f3Smrg [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x80, 597ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE] = 0x8, 607ec681f3Smrg [ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT] = 0x1, 617ec681f3Smrg [ETNAVIV_PARAM_GPU_PIXEL_PIPES] = 0x1, 627ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x80, 637ec681f3Smrg [ETNAVIV_PARAM_GPU_BUFFER_SIZE] = 0x0, 647ec681f3Smrg [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x100, 657ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_CONSTANTS] = 0x140, 667ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_VARYINGS] = 0x8, 677ec681f3Smrg [ETNAVIV_PARAM_SOFTPIN_START_ADDR] = ~0ULL, 687ec681f3Smrg } 697ec681f3Smrg }, 707ec681f3Smrg { 717ec681f3Smrg .name = "GC2000", 727ec681f3Smrg .reg_map = (const uint64_t[]){ 737ec681f3Smrg [ETNAVIV_PARAM_GPU_MODEL] = 0x2000, 747ec681f3Smrg [ETNAVIV_PARAM_GPU_REVISION] = 0x5108, 757ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_0] = 0xe0296cad, 767ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_1] = 0xc9799eff, 777ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_2] = 0x2efbf2d9, 787ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_3] = 0x0, 797ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_4] = 0x0, 807ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_5] = 0x0, 817ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_6] = 0x0, 827ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_7] = 0x0, 837ec681f3Smrg [ETNAVIV_PARAM_GPU_STREAM_COUNT] = 0x8, 847ec681f3Smrg [ETNAVIV_PARAM_GPU_REGISTER_MAX] = 0x40, 857ec681f3Smrg [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400, 867ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE] = 0x10, 877ec681f3Smrg [ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT] = 0x4, 887ec681f3Smrg [ETNAVIV_PARAM_GPU_PIXEL_PIPES] = 0x2, 897ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x200, 907ec681f3Smrg [ETNAVIV_PARAM_GPU_BUFFER_SIZE] = 0x0, 917ec681f3Smrg [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x200, 927ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_CONSTANTS] = 0xa8, 937ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_VARYINGS] = 0xb, 947ec681f3Smrg [ETNAVIV_PARAM_SOFTPIN_START_ADDR] = ~0ULL, 957ec681f3Smrg } 967ec681f3Smrg }, 977ec681f3Smrg { 987ec681f3Smrg .name = "GC3000", 997ec681f3Smrg .reg_map = (const uint64_t[]){ 1007ec681f3Smrg [ETNAVIV_PARAM_GPU_MODEL] = 0x3000, 1017ec681f3Smrg [ETNAVIV_PARAM_GPU_REVISION] = 0x5450, 1027ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_0] = 0xe0287cad, 1037ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_1] = 0xc9799efb, 1047ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_2] = 0xfefbfadb, 1057ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_3] = 0xeb9d4bbf, 1067ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_4] = 0xedffdced, 1077ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_5] = 0x930d2f47, 1087ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_6] = 0x10000133, 1097ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_7] = 0x0, 1107ec681f3Smrg [ETNAVIV_PARAM_GPU_STREAM_COUNT] = 0x10, 1117ec681f3Smrg [ETNAVIV_PARAM_GPU_REGISTER_MAX] = 0x40, 1127ec681f3Smrg [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400, 1137ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE] = 0x10, 1147ec681f3Smrg [ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT] = 0x4, 1157ec681f3Smrg [ETNAVIV_PARAM_GPU_PIXEL_PIPES] = 0x2, 1167ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x400, 1177ec681f3Smrg [ETNAVIV_PARAM_GPU_BUFFER_SIZE] = 0x0, 1187ec681f3Smrg [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x100, 1197ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_CONSTANTS] = 0x140, 1207ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_VARYINGS] = 0x10, 1217ec681f3Smrg [ETNAVIV_PARAM_SOFTPIN_START_ADDR] = ~0ULL, 1227ec681f3Smrg } 1237ec681f3Smrg }, 1247ec681f3Smrg { 1257ec681f3Smrg .name = "GC7000L", 1267ec681f3Smrg .reg_map = (const uint64_t[]){ 1277ec681f3Smrg [ETNAVIV_PARAM_GPU_MODEL] = 0x7000, 1287ec681f3Smrg [ETNAVIV_PARAM_GPU_REVISION] = 0x6214, 1297ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_0] = 0xe0287cad, 1307ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_1] = 0xc1799eff, 1317ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_2] = 0xfefbfad9, 1327ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_3] = 0xeb9d4fbf, 1337ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_4] = 0xedfffced, 1347ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_5] = 0xdb0dafc7, 1357ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_6] = 0xbb5ac333, 1367ec681f3Smrg [ETNAVIV_PARAM_GPU_FEATURES_7] = 0xfc8ee200, 1377ec681f3Smrg [ETNAVIV_PARAM_GPU_STREAM_COUNT] = 0x10, 1387ec681f3Smrg [ETNAVIV_PARAM_GPU_REGISTER_MAX] = 0x40, 1397ec681f3Smrg [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400, 1407ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE] = 0x10, 1417ec681f3Smrg [ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT] = 0x4, 1427ec681f3Smrg [ETNAVIV_PARAM_GPU_PIXEL_PIPES] = 0x2, 1437ec681f3Smrg [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x400, 1447ec681f3Smrg [ETNAVIV_PARAM_GPU_BUFFER_SIZE] = 0x0, 1457ec681f3Smrg [ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT] = 0x200, 1467ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_CONSTANTS] = 0x140, 1477ec681f3Smrg [ETNAVIV_PARAM_GPU_NUM_VARYINGS] = 0x10, 1487ec681f3Smrg [ETNAVIV_PARAM_SOFTPIN_START_ADDR] = 0x00400000, 1497ec681f3Smrg } 1507ec681f3Smrg } 1517ec681f3Smrg}; 1527ec681f3Smrg 1537ec681f3Smrgstatic const struct etna_shim_gpu *shim_gpu; 1547ec681f3Smrg 1557ec681f3Smrgstatic int 1567ec681f3Smrgetnaviv_ioctl_noop(int fd, unsigned long request, void *arg) 1577ec681f3Smrg{ 1587ec681f3Smrg return 0; 1597ec681f3Smrg} 1607ec681f3Smrg 1617ec681f3Smrgstatic int 1627ec681f3Smrgetnaviv_ioctl_gem_new(int fd, unsigned long request, void *arg) 1637ec681f3Smrg{ 1647ec681f3Smrg struct shim_fd *shim_fd = drm_shim_fd_lookup(fd); 1657ec681f3Smrg struct drm_etnaviv_gem_new *create = arg; 1667ec681f3Smrg struct shim_bo *bo = calloc(1, sizeof(*bo)); 1677ec681f3Smrg 1687ec681f3Smrg drm_shim_bo_init(bo, create->size); 1697ec681f3Smrg create->handle = drm_shim_bo_get_handle(shim_fd, bo); 1707ec681f3Smrg drm_shim_bo_put(bo); 1717ec681f3Smrg 1727ec681f3Smrg return 0; 1737ec681f3Smrg} 1747ec681f3Smrg 1757ec681f3Smrgstatic int 1767ec681f3Smrgetnaviv_ioctl_gem_info(int fd, unsigned long request, void *arg) 1777ec681f3Smrg{ 1787ec681f3Smrg struct shim_fd *shim_fd = drm_shim_fd_lookup(fd); 1797ec681f3Smrg struct drm_etnaviv_gem_info *args = arg; 1807ec681f3Smrg struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle); 1817ec681f3Smrg 1827ec681f3Smrg args->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo); 1837ec681f3Smrg drm_shim_bo_put(bo); 1847ec681f3Smrg 1857ec681f3Smrg return 0; 1867ec681f3Smrg} 1877ec681f3Smrg 1887ec681f3Smrgstatic int 1897ec681f3Smrgetnaviv_ioctl_get_param(int fd, unsigned long request, void *arg) 1907ec681f3Smrg{ 1917ec681f3Smrg struct drm_etnaviv_param *gp = arg; 1927ec681f3Smrg 1937ec681f3Smrg if (gp->param > ETNAVIV_PARAM_SOFTPIN_START_ADDR) { 1947ec681f3Smrg fprintf(stderr, "Unknown DRM_IOCTL_ETNAVIV_GET_PARAM %d\n", gp->param); 1957ec681f3Smrg return -1; 1967ec681f3Smrg } 1977ec681f3Smrg 1987ec681f3Smrg gp->value = shim_gpu->reg_map[gp->param]; 1997ec681f3Smrg 2007ec681f3Smrg return 0; 2017ec681f3Smrg} 2027ec681f3Smrg 2037ec681f3Smrgstatic ioctl_fn_t driver_ioctls[] = { 2047ec681f3Smrg [DRM_ETNAVIV_GET_PARAM] = etnaviv_ioctl_get_param, 2057ec681f3Smrg [DRM_ETNAVIV_GEM_NEW] = etnaviv_ioctl_gem_new, 2067ec681f3Smrg [DRM_ETNAVIV_GEM_INFO] = etnaviv_ioctl_gem_info, 2077ec681f3Smrg [DRM_ETNAVIV_GEM_CPU_PREP] = etnaviv_ioctl_noop, 2087ec681f3Smrg [DRM_ETNAVIV_GEM_CPU_FINI] = etnaviv_ioctl_noop, 2097ec681f3Smrg [DRM_ETNAVIV_GEM_SUBMIT] = etnaviv_ioctl_noop, 2107ec681f3Smrg [DRM_ETNAVIV_WAIT_FENCE] = etnaviv_ioctl_noop, 2117ec681f3Smrg [DRM_ETNAVIV_GEM_USERPTR] = etnaviv_ioctl_noop, 2127ec681f3Smrg [DRM_ETNAVIV_GEM_WAIT] = etnaviv_ioctl_noop, 2137ec681f3Smrg [DRM_ETNAVIV_PM_QUERY_DOM] = etnaviv_ioctl_noop, 2147ec681f3Smrg [DRM_ETNAVIV_PM_QUERY_SIG] = etnaviv_ioctl_noop, 2157ec681f3Smrg}; 2167ec681f3Smrg 2177ec681f3Smrgvoid 2187ec681f3Smrgdrm_shim_driver_init(void) 2197ec681f3Smrg{ 2207ec681f3Smrg shim_device.bus_type = DRM_BUS_PLATFORM; 2217ec681f3Smrg shim_device.driver_name = "etnaviv"; 2227ec681f3Smrg shim_device.driver_ioctls = driver_ioctls; 2237ec681f3Smrg shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls); 2247ec681f3Smrg 2257ec681f3Smrg /* etnaviv uses the DRM version to expose features, instead of getparam. */ 2267ec681f3Smrg shim_device.version_major = 1; 2277ec681f3Smrg shim_device.version_minor = 1; 2287ec681f3Smrg shim_device.version_patchlevel = 0; 2297ec681f3Smrg 2307ec681f3Smrg drm_shim_override_file("DRIVER=etnaviv\n" 2317ec681f3Smrg "MODALIAS=platform:etnaviv\n", 2327ec681f3Smrg "/sys/dev/char/%d:%d/device/uevent", 2337ec681f3Smrg DRM_MAJOR, render_node_minor); 2347ec681f3Smrg 2357ec681f3Smrg /* decide what GPU to emulate */ 2367ec681f3Smrg const char *gpu = debug_get_option("ETNA_SHIM_GPU", "GC2000"); 2377ec681f3Smrg 2387ec681f3Smrg for (unsigned i = 0; i < ARRAY_SIZE(gpus); i++) { 2397ec681f3Smrg if (strncasecmp(gpu, gpus[i].name, strlen(gpus[i].name)) == 0) { 2407ec681f3Smrg shim_gpu = &gpus[i]; 2417ec681f3Smrg break; 2427ec681f3Smrg } 2437ec681f3Smrg } 2447ec681f3Smrg 2457ec681f3Smrg /* NOTE: keep keep default value and fallback index in sync */ 2467ec681f3Smrg if (!shim_gpu) 2477ec681f3Smrg shim_gpu = &gpus[1]; 2487ec681f3Smrg 2497ec681f3Smrg fprintf(stderr, "Using %s as shim gpu\n", shim_gpu->name); 2507ec681f3Smrg} 251