1/* 2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include <math.h> 28#include "util/half_float.h" 29#include "util/u_math.h" 30 31#include "ir3.h" 32#include "ir3_compiler.h" 33#include "ir3_shader.h" 34 35#define swap(a, b) \ 36 do { \ 37 __typeof(a) __tmp = (a); \ 38 (a) = (b); \ 39 (b) = __tmp; \ 40 } while (0) 41 42/* 43 * Copy Propagate: 44 */ 45 46struct ir3_cp_ctx { 47 struct ir3 *shader; 48 struct ir3_shader_variant *so; 49 bool progress; 50}; 51 52/* is it a type preserving mov, with ok flags? 53 * 54 * @instr: the mov to consider removing 55 * @dst_instr: the instruction consuming the mov (instr) 56 * 57 * TODO maybe drop allow_flags since this is only false when dst is 58 * NULL (ie. outputs) 59 */ 60static bool 61is_eligible_mov(struct ir3_instruction *instr, 62 struct ir3_instruction *dst_instr, bool allow_flags) 63{ 64 if (is_same_type_mov(instr)) { 65 struct ir3_register *dst = instr->dsts[0]; 66 struct ir3_register *src = instr->srcs[0]; 67 struct ir3_instruction *src_instr = ssa(src); 68 69 /* only if mov src is SSA (not const/immed): */ 70 if (!src_instr) 71 return false; 72 73 /* no indirect: */ 74 if (dst->flags & IR3_REG_RELATIV) 75 return false; 76 if (src->flags & IR3_REG_RELATIV) 77 return false; 78 79 if (src->flags & IR3_REG_ARRAY) 80 return false; 81 82 if (!allow_flags) 83 if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG | IR3_REG_SABS | 84 IR3_REG_SNEG | IR3_REG_BNOT)) 85 return false; 86 87 return true; 88 } 89 return false; 90} 91 92/* we can end up with extra cmps.s from frontend, which uses a 93 * 94 * cmps.s p0.x, cond, 0 95 * 96 * as a way to mov into the predicate register. But frequently 'cond' 97 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case. 98 */ 99static bool 100is_foldable_double_cmp(struct ir3_instruction *cmp) 101{ 102 struct ir3_instruction *cond = ssa(cmp->srcs[0]); 103 return (cmp->dsts[0]->num == regid(REG_P0, 0)) && cond && 104 (cmp->srcs[1]->flags & IR3_REG_IMMED) && 105 (cmp->srcs[1]->iim_val == 0) && 106 (cmp->cat2.condition == IR3_COND_NE) && 107 (!cond->address || cond->address->def->instr->block == cmp->block); 108} 109 110/* propagate register flags from src to dst.. negates need special 111 * handling to cancel each other out. 112 */ 113static void 114combine_flags(unsigned *dstflags, struct ir3_instruction *src) 115{ 116 unsigned srcflags = src->srcs[0]->flags; 117 118 /* if what we are combining into already has (abs) flags, 119 * we can drop (neg) from src: 120 */ 121 if (*dstflags & IR3_REG_FABS) 122 srcflags &= ~IR3_REG_FNEG; 123 if (*dstflags & IR3_REG_SABS) 124 srcflags &= ~IR3_REG_SNEG; 125 126 if (srcflags & IR3_REG_FABS) 127 *dstflags |= IR3_REG_FABS; 128 if (srcflags & IR3_REG_SABS) 129 *dstflags |= IR3_REG_SABS; 130 if (srcflags & IR3_REG_FNEG) 131 *dstflags ^= IR3_REG_FNEG; 132 if (srcflags & IR3_REG_SNEG) 133 *dstflags ^= IR3_REG_SNEG; 134 if (srcflags & IR3_REG_BNOT) 135 *dstflags ^= IR3_REG_BNOT; 136 137 *dstflags &= ~IR3_REG_SSA; 138 *dstflags |= srcflags & IR3_REG_SSA; 139 *dstflags |= srcflags & IR3_REG_CONST; 140 *dstflags |= srcflags & IR3_REG_IMMED; 141 *dstflags |= srcflags & IR3_REG_RELATIV; 142 *dstflags |= srcflags & IR3_REG_ARRAY; 143 *dstflags |= srcflags & IR3_REG_SHARED; 144 145 /* if src of the src is boolean we can drop the (abs) since we know 146 * the source value is already a postitive integer. This cleans 147 * up the absnegs that get inserted when converting between nir and 148 * native boolean (see ir3_b2n/n2b) 149 */ 150 struct ir3_instruction *srcsrc = ssa(src->srcs[0]); 151 if (srcsrc && is_bool(srcsrc)) 152 *dstflags &= ~IR3_REG_SABS; 153} 154 155/* Tries lowering an immediate register argument to a const buffer access by 156 * adding to the list of immediates to be pushed to the const buffer when 157 * switching to this shader. 158 */ 159static bool 160lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n, 161 struct ir3_register *reg, unsigned new_flags) 162{ 163 if (!(new_flags & IR3_REG_IMMED)) 164 return false; 165 166 new_flags &= ~IR3_REG_IMMED; 167 new_flags |= IR3_REG_CONST; 168 169 if (!ir3_valid_flags(instr, n, new_flags)) 170 return false; 171 172 reg = ir3_reg_clone(ctx->shader, reg); 173 174 /* Half constant registers seems to handle only 32-bit values 175 * within floating-point opcodes. So convert back to 32-bit values. 176 */ 177 bool f_opcode = 178 (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false; 179 if (f_opcode && (new_flags & IR3_REG_HALF)) 180 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val)); 181 182 /* in some cases, there are restrictions on (abs)/(neg) plus const.. 183 * so just evaluate those and clear the flags: 184 */ 185 if (new_flags & IR3_REG_SABS) { 186 reg->iim_val = abs(reg->iim_val); 187 new_flags &= ~IR3_REG_SABS; 188 } 189 190 if (new_flags & IR3_REG_FABS) { 191 reg->fim_val = fabs(reg->fim_val); 192 new_flags &= ~IR3_REG_FABS; 193 } 194 195 if (new_flags & IR3_REG_SNEG) { 196 reg->iim_val = -reg->iim_val; 197 new_flags &= ~IR3_REG_SNEG; 198 } 199 200 if (new_flags & IR3_REG_FNEG) { 201 reg->fim_val = -reg->fim_val; 202 new_flags &= ~IR3_REG_FNEG; 203 } 204 205 /* Reallocate for 4 more elements whenever it's necessary. Note that ir3 206 * printing relies on having groups of 4 dwords, so we fill the unused 207 * slots with a dummy value. 208 */ 209 struct ir3_const_state *const_state = ir3_const_state(ctx->so); 210 if (const_state->immediates_count == const_state->immediates_size) { 211 const_state->immediates = rerzalloc( 212 const_state, const_state->immediates, 213 __typeof__(const_state->immediates[0]), const_state->immediates_size, 214 const_state->immediates_size + 4); 215 const_state->immediates_size += 4; 216 217 for (int i = const_state->immediates_count; 218 i < const_state->immediates_size; i++) 219 const_state->immediates[i] = 0xd0d0d0d0; 220 } 221 222 int i; 223 for (i = 0; i < const_state->immediates_count; i++) { 224 if (const_state->immediates[i] == reg->uim_val) 225 break; 226 } 227 228 if (i == const_state->immediates_count) { 229 /* Add on a new immediate to be pushed, if we have space left in the 230 * constbuf. 231 */ 232 if (const_state->offsets.immediate + const_state->immediates_count / 4 >= 233 ir3_max_const(ctx->so)) 234 return false; 235 236 const_state->immediates[i] = reg->uim_val; 237 const_state->immediates_count++; 238 } 239 240 reg->flags = new_flags; 241 reg->num = i + (4 * const_state->offsets.immediate); 242 243 instr->srcs[n] = reg; 244 245 return true; 246} 247 248static void 249unuse(struct ir3_instruction *instr) 250{ 251 debug_assert(instr->use_count > 0); 252 253 if (--instr->use_count == 0) { 254 struct ir3_block *block = instr->block; 255 256 instr->barrier_class = 0; 257 instr->barrier_conflict = 0; 258 259 /* we don't want to remove anything in keeps (which could 260 * be things like array store's) 261 */ 262 for (unsigned i = 0; i < block->keeps_count; i++) { 263 debug_assert(block->keeps[i] != instr); 264 } 265 } 266} 267 268/** 269 * Handles the special case of the 2nd src (n == 1) to "normal" mad 270 * instructions, which cannot reference a constant. See if it is 271 * possible to swap the 1st and 2nd sources. 272 */ 273static bool 274try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags) 275{ 276 if (!is_mad(instr->opc)) 277 return false; 278 279 /* NOTE: pre-swap first two src's before valid_flags(), 280 * which might try to dereference the n'th src: 281 */ 282 swap(instr->srcs[0], instr->srcs[1]); 283 284 /* cat3 doesn't encode immediate, but we can lower immediate 285 * to const if that helps: 286 */ 287 if (new_flags & IR3_REG_IMMED) { 288 new_flags &= ~IR3_REG_IMMED; 289 new_flags |= IR3_REG_CONST; 290 } 291 292 bool valid_swap = 293 /* can we propagate mov if we move 2nd src to first? */ 294 ir3_valid_flags(instr, 0, new_flags) && 295 /* and does first src fit in second slot? */ 296 ir3_valid_flags(instr, 1, instr->srcs[1]->flags); 297 298 if (!valid_swap) { 299 /* put things back the way they were: */ 300 swap(instr->srcs[0], instr->srcs[1]); 301 } /* otherwise leave things swapped */ 302 303 return valid_swap; 304} 305 306/* Values that are uniform inside a loop can become divergent outside 307 * it if the loop has a divergent trip count. This means that we can't 308 * propagate a copy of a shared to non-shared register if it would 309 * make the shared reg's live range extend outside of its loop. Users 310 * outside the loop would see the value for the thread(s) that last 311 * exited the loop, rather than for their own thread. 312 */ 313static bool 314is_valid_shared_copy(struct ir3_instruction *dst_instr, 315 struct ir3_instruction *src_instr, 316 struct ir3_register *src_reg) 317{ 318 return !(src_reg->flags & IR3_REG_SHARED) || 319 dst_instr->block->loop_id == src_instr->block->loop_id; 320} 321 322/** 323 * Handle cp for a given src register. This additionally handles 324 * the cases of collapsing immedate/const (which replace the src 325 * register with a non-ssa src) or collapsing mov's from relative 326 * src (which needs to also fixup the address src reference by the 327 * instruction). 328 */ 329static bool 330reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, 331 struct ir3_register *reg, unsigned n) 332{ 333 struct ir3_instruction *src = ssa(reg); 334 335 if (is_eligible_mov(src, instr, true)) { 336 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */ 337 struct ir3_register *src_reg = src->srcs[0]; 338 unsigned new_flags = reg->flags; 339 340 if (!is_valid_shared_copy(instr, src, src_reg)) 341 return false; 342 343 combine_flags(&new_flags, src); 344 345 if (ir3_valid_flags(instr, n, new_flags)) { 346 if (new_flags & IR3_REG_ARRAY) { 347 debug_assert(!(reg->flags & IR3_REG_ARRAY)); 348 reg->array = src_reg->array; 349 } 350 reg->flags = new_flags; 351 reg->def = src_reg->def; 352 353 instr->barrier_class |= src->barrier_class; 354 instr->barrier_conflict |= src->barrier_conflict; 355 356 unuse(src); 357 reg->def->instr->use_count++; 358 359 return true; 360 } 361 } else if ((is_same_type_mov(src) || is_const_mov(src)) && 362 /* cannot collapse const/immed/etc into control flow: */ 363 opc_cat(instr->opc) != 0) { 364 /* immed/const/etc cases, which require some special handling: */ 365 struct ir3_register *src_reg = src->srcs[0]; 366 unsigned new_flags = reg->flags; 367 368 if (!is_valid_shared_copy(instr, src, src_reg)) 369 return false; 370 371 if (src_reg->flags & IR3_REG_ARRAY) 372 return false; 373 374 combine_flags(&new_flags, src); 375 376 if (!ir3_valid_flags(instr, n, new_flags)) { 377 /* See if lowering an immediate to const would help. */ 378 if (lower_immed(ctx, instr, n, src_reg, new_flags)) 379 return true; 380 381 /* special case for "normal" mad instructions, we can 382 * try swapping the first two args if that fits better. 383 * 384 * the "plain" MAD's (ie. the ones that don't shift first 385 * src prior to multiply) can swap their first two srcs if 386 * src[0] is !CONST and src[1] is CONST: 387 */ 388 if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) { 389 return true; 390 } else { 391 return false; 392 } 393 } 394 395 /* Here we handle the special case of mov from 396 * CONST and/or RELATIV. These need to be handled 397 * specially, because in the case of move from CONST 398 * there is no src ir3_instruction so we need to 399 * replace the ir3_register. And in the case of 400 * RELATIV we need to handle the address register 401 * dependency. 402 */ 403 if (src_reg->flags & IR3_REG_CONST) { 404 /* an instruction cannot reference two different 405 * address registers: 406 */ 407 if ((src_reg->flags & IR3_REG_RELATIV) && 408 conflicts(instr->address, reg->def->instr->address)) 409 return false; 410 411 /* This seems to be a hw bug, or something where the timings 412 * just somehow don't work out. This restriction may only 413 * apply if the first src is also CONST. 414 */ 415 if ((opc_cat(instr->opc) == 3) && (n == 2) && 416 (src_reg->flags & IR3_REG_RELATIV) && (src_reg->array.offset == 0)) 417 return false; 418 419 /* When narrowing constant from 32b to 16b, it seems 420 * to work only for float. So we should do this only with 421 * float opcodes. 422 */ 423 if (src->cat1.dst_type == TYPE_F16) { 424 /* TODO: should we have a way to tell phi/collect to use a 425 * float move so that this is legal? 426 */ 427 if (is_meta(instr)) 428 return false; 429 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type)) 430 return false; 431 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc)) 432 return false; 433 } else if (src->cat1.dst_type == TYPE_U16) { 434 /* Since we set CONSTANT_DEMOTION_ENABLE, a float reference of 435 * what was a U16 value read from the constbuf would incorrectly 436 * do 32f->16f conversion, when we want to read a 16f value. 437 */ 438 if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) 439 return false; 440 if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type)) 441 return false; 442 } 443 444 src_reg = ir3_reg_clone(instr->block->shader, src_reg); 445 src_reg->flags = new_flags; 446 instr->srcs[n] = src_reg; 447 448 if (src_reg->flags & IR3_REG_RELATIV) 449 ir3_instr_set_address(instr, reg->def->instr->address->def->instr); 450 451 return true; 452 } 453 454 if (src_reg->flags & IR3_REG_IMMED) { 455 int32_t iim_val = src_reg->iim_val; 456 457 debug_assert((opc_cat(instr->opc) == 1) || 458 (opc_cat(instr->opc) == 2) || 459 (opc_cat(instr->opc) == 6) || 460 is_meta(instr) || 461 (is_mad(instr->opc) && (n == 0))); 462 463 if ((opc_cat(instr->opc) == 2) && 464 !ir3_cat2_int(instr->opc)) { 465 iim_val = ir3_flut(src_reg); 466 if (iim_val < 0) { 467 /* Fall back to trying to load the immediate as a const: */ 468 return lower_immed(ctx, instr, n, src_reg, new_flags); 469 } 470 } 471 472 if (new_flags & IR3_REG_SABS) 473 iim_val = abs(iim_val); 474 475 if (new_flags & IR3_REG_SNEG) 476 iim_val = -iim_val; 477 478 if (new_flags & IR3_REG_BNOT) 479 iim_val = ~iim_val; 480 481 if (ir3_valid_flags(instr, n, new_flags) && 482 ir3_valid_immediate(instr, iim_val)) { 483 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT); 484 src_reg = ir3_reg_clone(instr->block->shader, src_reg); 485 src_reg->flags = new_flags; 486 src_reg->iim_val = iim_val; 487 instr->srcs[n] = src_reg; 488 489 return true; 490 } else { 491 /* Fall back to trying to load the immediate as a const: */ 492 return lower_immed(ctx, instr, n, src_reg, new_flags); 493 } 494 } 495 } 496 497 return false; 498} 499 500/* Handle special case of eliminating output mov, and similar cases where 501 * there isn't a normal "consuming" instruction. In this case we cannot 502 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot 503 * be eliminated) 504 */ 505static struct ir3_instruction * 506eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr) 507{ 508 if (is_eligible_mov(instr, NULL, false)) { 509 struct ir3_register *reg = instr->srcs[0]; 510 if (!(reg->flags & IR3_REG_ARRAY)) { 511 struct ir3_instruction *src_instr = ssa(reg); 512 debug_assert(src_instr); 513 ctx->progress = true; 514 return src_instr; 515 } 516 } 517 return instr; 518} 519 520/** 521 * Find instruction src's which are mov's that can be collapsed, replacing 522 * the mov dst with the mov src 523 */ 524static void 525instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr) 526{ 527 if (instr->srcs_count == 0) 528 return; 529 530 if (ir3_instr_check_mark(instr)) 531 return; 532 533 /* walk down the graph from each src: */ 534 bool progress; 535 do { 536 progress = false; 537 foreach_src_n (reg, n, instr) { 538 struct ir3_instruction *src = ssa(reg); 539 540 if (!src) 541 continue; 542 543 instr_cp(ctx, src); 544 545 /* TODO non-indirect access we could figure out which register 546 * we actually want and allow cp.. 547 */ 548 if ((reg->flags & IR3_REG_ARRAY) && src->opc != OPC_META_PHI) 549 continue; 550 551 /* Don't CP absneg into meta instructions, that won't end well: */ 552 if (is_meta(instr) && 553 (src->opc == OPC_ABSNEG_F || src->opc == OPC_ABSNEG_S)) 554 continue; 555 556 /* Don't CP mova and mova1 into their users */ 557 if (writes_addr0(src) || writes_addr1(src)) 558 continue; 559 560 progress |= reg_cp(ctx, instr, reg, n); 561 ctx->progress |= progress; 562 } 563 } while (progress); 564 565 /* After folding a mov's source we may wind up with a type-converting mov 566 * of an immediate. This happens e.g. with texture descriptors, since we 567 * narrow the descriptor (which may be a constant) to a half-reg in ir3. 568 * By converting the immediate in-place to the destination type, we can 569 * turn the mov into a same-type mov so that it can be further propagated. 570 */ 571 if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) && 572 instr->cat1.src_type != instr->cat1.dst_type && 573 /* Only do uint types for now, until we generate other types of 574 * mov's during instruction selection. 575 */ 576 full_type(instr->cat1.src_type) == TYPE_U32 && 577 full_type(instr->cat1.dst_type) == TYPE_U32) { 578 uint32_t uimm = instr->srcs[0]->uim_val; 579 if (instr->cat1.dst_type == TYPE_U16) 580 uimm &= 0xffff; 581 instr->srcs[0]->uim_val = uimm; 582 if (instr->dsts[0]->flags & IR3_REG_HALF) 583 instr->srcs[0]->flags |= IR3_REG_HALF; 584 else 585 instr->srcs[0]->flags &= ~IR3_REG_HALF; 586 instr->cat1.src_type = instr->cat1.dst_type; 587 ctx->progress = true; 588 } 589 590 /* Re-write the instruction writing predicate register to get rid 591 * of the double cmps. 592 */ 593 if ((instr->opc == OPC_CMPS_S) && is_foldable_double_cmp(instr)) { 594 struct ir3_instruction *cond = ssa(instr->srcs[0]); 595 switch (cond->opc) { 596 case OPC_CMPS_S: 597 case OPC_CMPS_F: 598 case OPC_CMPS_U: 599 instr->opc = cond->opc; 600 instr->flags = cond->flags; 601 instr->cat2 = cond->cat2; 602 if (cond->address) 603 ir3_instr_set_address(instr, cond->address->def->instr); 604 instr->srcs[0] = ir3_reg_clone(ctx->shader, cond->srcs[0]); 605 instr->srcs[1] = ir3_reg_clone(ctx->shader, cond->srcs[1]); 606 instr->barrier_class |= cond->barrier_class; 607 instr->barrier_conflict |= cond->barrier_conflict; 608 unuse(cond); 609 ctx->progress = true; 610 break; 611 default: 612 break; 613 } 614 } 615 616 /* Handle converting a sam.s2en (taking samp/tex idx params via register) 617 * into a normal sam (encoding immediate samp/tex idx) if they are 618 * immediate. This saves some instructions and regs in the common case 619 * where we know samp/tex at compile time. This needs to be done in the 620 * frontend for bindless tex, though, so don't replicate it here. 621 */ 622 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) && 623 !(instr->flags & IR3_INSTR_B) && 624 !(ir3_shader_debug & IR3_DBG_FORCES2EN)) { 625 /* The first src will be a collect, if both of it's 626 * two sources are mov from imm, then we can 627 */ 628 struct ir3_instruction *samp_tex = ssa(instr->srcs[0]); 629 630 debug_assert(samp_tex->opc == OPC_META_COLLECT); 631 632 struct ir3_register *samp = samp_tex->srcs[0]; 633 struct ir3_register *tex = samp_tex->srcs[1]; 634 635 if ((samp->flags & IR3_REG_IMMED) && (tex->flags & IR3_REG_IMMED)) { 636 instr->flags &= ~IR3_INSTR_S2EN; 637 instr->cat5.samp = samp->iim_val; 638 instr->cat5.tex = tex->iim_val; 639 640 /* shuffle around the regs to remove the first src: */ 641 instr->srcs_count--; 642 for (unsigned i = 0; i < instr->srcs_count; i++) { 643 instr->srcs[i] = instr->srcs[i + 1]; 644 } 645 646 ctx->progress = true; 647 } 648 } 649} 650 651bool 652ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so) 653{ 654 struct ir3_cp_ctx ctx = { 655 .shader = ir, 656 .so = so, 657 }; 658 659 /* This is a bit annoying, and probably wouldn't be necessary if we 660 * tracked a reverse link from producing instruction to consumer. 661 * But we need to know when we've eliminated the last consumer of 662 * a mov, so we need to do a pass to first count consumers of a 663 * mov. 664 */ 665 foreach_block (block, &ir->block_list) { 666 foreach_instr (instr, &block->instr_list) { 667 668 /* by the way, we don't account for false-dep's, so the CP 669 * pass should always happen before false-dep's are inserted 670 */ 671 debug_assert(instr->deps_count == 0); 672 673 foreach_ssa_src (src, instr) { 674 src->use_count++; 675 } 676 } 677 } 678 679 ir3_clear_mark(ir); 680 681 foreach_block (block, &ir->block_list) { 682 if (block->condition) { 683 instr_cp(&ctx, block->condition); 684 block->condition = eliminate_output_mov(&ctx, block->condition); 685 } 686 687 for (unsigned i = 0; i < block->keeps_count; i++) { 688 instr_cp(&ctx, block->keeps[i]); 689 block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]); 690 } 691 } 692 693 return ctx.progress; 694} 695