17ec681f3Smrg<?xml version="1.0" encoding="UTF-8"?> 27ec681f3Smrg<database xmlns="http://nouveau.freedesktop.org/" 37ec681f3Smrgxmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 47ec681f3Smrgxsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 57ec681f3Smrg<import file="freedreno_copyright.xml"/> 67ec681f3Smrg 77ec681f3Smrg<domain name="MMSS_CC" width="32"> 87ec681f3Smrg <brief> 97ec681f3Smrg Multimedia sub-system clock control.. appears to be used by DSI 107ec681f3Smrg for clocks.. 117ec681f3Smrg </brief> 127ec681f3Smrg 137ec681f3Smrg <reg32 offset="0x0008" name="AHB"/> 147ec681f3Smrg 157ec681f3Smrg <enum name="mmss_cc_clk"> 167ec681f3Smrg <value name="CLK" value="0"/> 177ec681f3Smrg <value name="PCLK" value="1"/> 187ec681f3Smrg </enum> 197ec681f3Smrg 207ec681f3Smrg <!-- 217ec681f3Smrg possibly these sequences of registers are same, except pre_div_func 227ec681f3Smrg is shifted by 12 in pclk and 14 in clk.. I'm going to guess that 237ec681f3Smrg the register is same and they just multiply value by 4.. 247ec681f3Smrg --> 257ec681f3Smrg <array offsets="0x004c,0x0130" name="CLK" length="2" stride="0x10" index="mmss_cc_clk"> 267ec681f3Smrg <reg32 offset="0x00" name="CC"> 277ec681f3Smrg <bitfield name="CLK_EN" pos="0" type="boolean"/> 287ec681f3Smrg <bitfield name="ROOT_EN" pos="2" type="boolean"/> 297ec681f3Smrg <bitfield name="MND_EN" pos="5" type="boolean"/> 307ec681f3Smrg <bitfield name="MND_MODE" low="6" high="7"/> 317ec681f3Smrg <bitfield name="PMXO_SEL" low="8" high="9"/> <!-- not sure high --> 327ec681f3Smrg </reg32> 337ec681f3Smrg <reg32 offset="0x04" name="MD"> 347ec681f3Smrg <bitfield name="D" low="0" high="7"/> 357ec681f3Smrg <bitfield name="M" low="8" high="15"/> 367ec681f3Smrg </reg32> 377ec681f3Smrg <reg32 offset="0x08" name="NS"> 387ec681f3Smrg <bitfield name="SRC" low="0" high="3"/> <!-- not sure high, but it is >= 1 --> 397ec681f3Smrg <bitfield name="PRE_DIV_FUNC" low="12" high="23"/> 407ec681f3Smrg <bitfield name="VAL" low="24" high="31"></bitfield> 417ec681f3Smrg </reg32> 427ec681f3Smrg </array> 437ec681f3Smrg <reg32 offset="0x0094" name="DSI2_PIXEL_CC"/> 447ec681f3Smrg <reg32 offset="0x00e4" name="DSI2_PIXEL_NS"/> 457ec681f3Smrg <reg32 offset="0x0264" name="DSI2_PIXEL_CC2"/> 467ec681f3Smrg</domain> 477ec681f3Smrg 487ec681f3Smrg</database> 49