1/**************************************************************************
2 *
3 * Copyright 2010-2012 VMware, Inc.
4 * All Rights Reserved.
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6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
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11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 * of the Software.
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26 **************************************************************************/
27
28
29#ifndef LP_BLD_LIMITS_H_
30#define LP_BLD_LIMITS_H_
31
32
33#include <limits.h>
34
35#include "pipe/p_state.h"
36#include "pipe/p_defines.h"
37#include "util/u_cpu_detect.h"
38
39/*
40 * TGSI translation limits.
41 *
42 * Some are slightly above SM 3.0 requirements to give some wiggle room to
43 * the gallium frontends.
44 */
45
46#define LP_MAX_TGSI_TEMPS 4096
47
48#define LP_MAX_TGSI_ADDRS 16
49
50#define LP_MAX_TGSI_IMMEDIATES 4096
51
52#define LP_MAX_TGSI_CONSTS 4096
53
54#define LP_MAX_TGSI_CONST_BUFFERS 16
55
56#define LP_MAX_TGSI_CONST_BUFFER_SIZE (LP_MAX_TGSI_CONSTS * sizeof(float[4]))
57
58#define LP_MAX_TGSI_SHADER_BUFFERS 16
59
60#define LP_MAX_TGSI_SHADER_BUFFER_SIZE (1 << 27)
61
62#define LP_MAX_TGSI_SHADER_IMAGES 16
63
64/*
65 * For quick access we cache registers in statically
66 * allocated arrays. Here we define the maximum size
67 * for those arrays.
68 */
69#define LP_MAX_INLINED_TEMPS 256
70
71#define LP_MAX_INLINED_IMMEDIATES 256
72
73/**
74 * Maximum control flow nesting
75 *
76 * Vulkan CTS tests seem to have up to 76 levels. Add a few for safety.
77 * SM4.0 requires 64 (per subroutine actually, subroutine nesting itself is 32)
78 * SM3.0 requires 24 (most likely per subroutine too)
79 * add 2 more (some translation could add one more)
80 */
81#define LP_MAX_TGSI_NESTING 80
82
83/**
84 * Maximum iterations before loop termination
85 * Shared between every loop in a TGSI shader
86 */
87#define LP_MAX_TGSI_LOOP_ITERATIONS 65535
88
89static inline bool
90lp_has_fp16(void)
91{
92   return util_get_cpu_caps()->has_f16c;
93}
94
95/**
96 * Some of these limits are actually infinite (i.e., only limited by available
97 * memory), however advertising INT_MAX would cause some test problems to
98 * actually try to allocate the maximum and run out of memory and crash.  So
99 * stick with something reasonable here.
100 */
101static inline int
102gallivm_get_shader_param(enum pipe_shader_cap param)
103{
104   switch(param) {
105   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
106   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
107   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
108   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
109      return 1 * 1024 * 1024;
110   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
111      return LP_MAX_TGSI_NESTING;
112   case PIPE_SHADER_CAP_MAX_INPUTS:
113      return 32;
114   case PIPE_SHADER_CAP_MAX_OUTPUTS:
115      return 32;
116   case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
117      return LP_MAX_TGSI_CONST_BUFFER_SIZE;
118   case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
119      return LP_MAX_TGSI_CONST_BUFFERS;
120   case PIPE_SHADER_CAP_MAX_TEMPS:
121      return LP_MAX_TGSI_TEMPS;
122   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
123      return 1;
124   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
125   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
126   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
127   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
128      return 1;
129   case PIPE_SHADER_CAP_SUBROUTINES:
130      return 1;
131   case PIPE_SHADER_CAP_INTEGERS:
132      return 1;
133   case PIPE_SHADER_CAP_FP16:
134   case PIPE_SHADER_CAP_FP16_DERIVATIVES:
135      return lp_has_fp16();
136   //enabling this breaks GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUniform
137   case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
138      return 0;
139   case PIPE_SHADER_CAP_INT64_ATOMICS:
140      return 0;
141   case PIPE_SHADER_CAP_INT16:
142   case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
143      return 1;
144   case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
145      return PIPE_MAX_SAMPLERS;
146   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
147      return PIPE_MAX_SHADER_SAMPLER_VIEWS;
148   case PIPE_SHADER_CAP_PREFERRED_IR:
149      return PIPE_SHADER_IR_TGSI;
150   case PIPE_SHADER_CAP_SUPPORTED_IRS:
151      return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
152   case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
153   case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
154      return 1;
155   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
156   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
157   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
158   case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
159   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
160   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
161   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
162   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
163      return 0;
164   case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
165      return 32;
166   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
167      return LP_MAX_TGSI_SHADER_BUFFERS;
168   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
169      return LP_MAX_TGSI_SHADER_IMAGES;
170   }
171   /* if we get here, we missed a shader cap above (and should have seen
172    * a compiler warning.)
173    */
174   return 0;
175}
176
177
178#endif /* LP_BLD_LIMITS_H_ */
179