1/*
2 * Copyright (c) 2019 Zodiac Inflight Innovations
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Jonathan Marek <jonathan@marek.ca>
25 */
26
27#include "etnaviv_compiler_nir.h"
28#include "util/register_allocate.h"
29
30/* use "r63.z" for depth reg, it will wrap around to r0.z by reg_get_base
31 * (fs registers are offset by 1 to avoid reserving r0)
32 */
33#define REG_FRAG_DEPTH ((ETNA_MAX_TEMPS - 1) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Z)
34
35/* precomputed by register_allocate  */
36static unsigned int *q_values[] = {
37   (unsigned int[]) {1, 2, 3, 4, 2, 2, 3, },
38   (unsigned int[]) {3, 5, 6, 6, 5, 5, 6, },
39   (unsigned int[]) {3, 4, 4, 4, 4, 4, 4, },
40   (unsigned int[]) {1, 1, 1, 1, 1, 1, 1, },
41   (unsigned int[]) {1, 2, 2, 2, 1, 2, 2, },
42   (unsigned int[]) {2, 3, 3, 3, 2, 3, 3, },
43   (unsigned int[]) {2, 2, 2, 2, 2, 2, 2, },
44};
45
46static inline int reg_get_class(int virt_reg)
47{
48   switch (reg_get_type(virt_reg)) {
49   case REG_TYPE_VEC4:
50      return REG_CLASS_VEC4;
51   case REG_TYPE_VIRT_VEC3_XYZ:
52   case REG_TYPE_VIRT_VEC3_XYW:
53   case REG_TYPE_VIRT_VEC3_XZW:
54   case REG_TYPE_VIRT_VEC3_YZW:
55      return REG_CLASS_VIRT_VEC3;
56   case REG_TYPE_VIRT_VEC2_XY:
57   case REG_TYPE_VIRT_VEC2_XZ:
58   case REG_TYPE_VIRT_VEC2_XW:
59   case REG_TYPE_VIRT_VEC2_YZ:
60   case REG_TYPE_VIRT_VEC2_YW:
61   case REG_TYPE_VIRT_VEC2_ZW:
62      return REG_CLASS_VIRT_VEC2;
63   case REG_TYPE_VIRT_SCALAR_X:
64   case REG_TYPE_VIRT_SCALAR_Y:
65   case REG_TYPE_VIRT_SCALAR_Z:
66   case REG_TYPE_VIRT_SCALAR_W:
67      return REG_CLASS_VIRT_SCALAR;
68   case REG_TYPE_VIRT_VEC2T_XY:
69   case REG_TYPE_VIRT_VEC2T_ZW:
70      return REG_CLASS_VIRT_VEC2T;
71   case REG_TYPE_VIRT_VEC2C_XY:
72   case REG_TYPE_VIRT_VEC2C_YZ:
73   case REG_TYPE_VIRT_VEC2C_ZW:
74      return REG_CLASS_VIRT_VEC2C;
75   case REG_TYPE_VIRT_VEC3C_XYZ:
76   case REG_TYPE_VIRT_VEC3C_YZW:
77      return REG_CLASS_VIRT_VEC3C;
78   }
79
80   assert(false);
81   return 0;
82}
83
84struct ra_regs *
85etna_ra_setup(void *mem_ctx)
86{
87   struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, ETNA_MAX_TEMPS *
88                  NUM_REG_TYPES, false);
89
90   /* classes always be created from index 0, so equal to the class enum
91    * which represents a register with (c+1) components
92    */
93   struct ra_class *classes[NUM_REG_CLASSES];
94   for (int c = 0; c < NUM_REG_CLASSES; c++)
95      classes[c] = ra_alloc_reg_class(regs);
96   /* add each register of each class */
97   for (int r = 0; r < NUM_REG_TYPES * ETNA_MAX_TEMPS; r++)
98      ra_class_add_reg(classes[reg_get_class(r)], r);
99   /* set conflicts */
100   for (int r = 0; r < ETNA_MAX_TEMPS; r++) {
101      for (int i = 0; i < NUM_REG_TYPES; i++) {
102         for (int j = 0; j < i; j++) {
103            if (reg_writemask[i] & reg_writemask[j]) {
104               ra_add_reg_conflict(regs, NUM_REG_TYPES * r + i,
105                                         NUM_REG_TYPES * r + j);
106            }
107         }
108      }
109   }
110   ra_set_finalize(regs, q_values);
111
112   return regs;
113}
114
115void
116etna_ra_assign(struct etna_compile *c, nir_shader *shader)
117{
118   struct etna_compiler *compiler = c->variant->shader->compiler;
119   struct ra_regs *regs = compiler->regs;
120
121   nir_function_impl *impl = nir_shader_get_entrypoint(shader);
122
123   /* liveness and interference */
124
125   nir_index_blocks(impl);
126   nir_index_ssa_defs(impl);
127   nir_foreach_block(block, impl) {
128      nir_foreach_instr(instr, block)
129         instr->pass_flags = 0;
130   }
131
132   /* this gives an approximation/upper limit on how many nodes are needed
133    * (some ssa values do not represent an allocated register)
134    */
135   unsigned max_nodes = impl->ssa_alloc + impl->reg_alloc;
136   unsigned *live_map = ralloc_array(NULL, unsigned, max_nodes);
137   memset(live_map, 0xff, sizeof(unsigned) * max_nodes);
138   struct live_def *defs = rzalloc_array(NULL, struct live_def, max_nodes);
139
140   unsigned num_nodes = etna_live_defs(impl, defs, live_map);
141   struct ra_graph *g = ra_alloc_interference_graph(regs, num_nodes);
142
143   /* set classes from num_components */
144   for (unsigned i = 0; i < num_nodes; i++) {
145      nir_instr *instr = defs[i].instr;
146      nir_dest *dest = defs[i].dest;
147      unsigned comp = nir_dest_num_components(*dest) - 1;
148
149      if (instr->type == nir_instr_type_alu &&
150          c->specs->has_new_transcendentals) {
151         switch (nir_instr_as_alu(instr)->op) {
152         case nir_op_fdiv:
153         case nir_op_flog2:
154         case nir_op_fsin:
155         case nir_op_fcos:
156            assert(dest->is_ssa);
157            comp = REG_CLASS_VIRT_VEC2T;
158            break;
159         default:
160            break;
161         }
162      }
163
164      if (instr->type == nir_instr_type_intrinsic) {
165         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
166         /* can't have dst swizzle or sparse writemask on UBO loads */
167         if (intr->intrinsic == nir_intrinsic_load_ubo) {
168            assert(dest == &intr->dest);
169            if (dest->ssa.num_components == 2)
170               comp = REG_CLASS_VIRT_VEC2C;
171            if (dest->ssa.num_components == 3)
172               comp = REG_CLASS_VIRT_VEC3C;
173         }
174      }
175
176      ra_set_node_class(g, i, ra_get_class_from_index(regs, comp));
177   }
178
179   nir_foreach_block(block, impl) {
180      nir_foreach_instr(instr, block) {
181         if (instr->type != nir_instr_type_intrinsic)
182            continue;
183
184         nir_dest *dest = dest_for_instr(instr);
185         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
186         unsigned reg;
187
188         switch (intr->intrinsic) {
189         case nir_intrinsic_store_deref: {
190            /* don't want outputs to be swizzled
191             * TODO: better would be to set the type to X/XY/XYZ/XYZW
192             * TODO: what if fragcoord.z is read after writing fragdepth?
193             */
194            nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
195            unsigned index = live_map[src_index(impl, &intr->src[1])];
196
197            if (shader->info.stage == MESA_SHADER_FRAGMENT &&
198                deref->var->data.location == FRAG_RESULT_DEPTH) {
199               ra_set_node_reg(g, index, REG_FRAG_DEPTH);
200            } else {
201               ra_set_node_class(g, index, ra_get_class_from_index(regs, REG_CLASS_VEC4));
202            }
203         } continue;
204         case nir_intrinsic_load_input:
205            reg = nir_intrinsic_base(intr) * NUM_REG_TYPES + (unsigned[]) {
206               REG_TYPE_VIRT_SCALAR_X,
207               REG_TYPE_VIRT_VEC2_XY,
208               REG_TYPE_VIRT_VEC3_XYZ,
209               REG_TYPE_VEC4,
210            }[nir_dest_num_components(*dest) - 1];
211            break;
212         case nir_intrinsic_load_instance_id:
213            reg = c->variant->infile.num_reg * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Y;
214            break;
215         default:
216            continue;
217         }
218
219         ra_set_node_reg(g, live_map[dest_index(impl, dest)], reg);
220      }
221   }
222
223   /* add interference for intersecting live ranges */
224   for (unsigned i = 0; i < num_nodes; i++) {
225      assert(defs[i].live_start < defs[i].live_end);
226      for (unsigned j = 0; j < i; j++) {
227         if (defs[i].live_start >= defs[j].live_end || defs[j].live_start >= defs[i].live_end)
228            continue;
229         ra_add_node_interference(g, i, j);
230      }
231   }
232
233   ralloc_free(defs);
234
235   /* Allocate registers */
236   ASSERTED bool ok = ra_allocate(g);
237   assert(ok);
238
239   c->g = g;
240   c->live_map = live_map;
241   c->num_nodes = num_nodes;
242}
243
244unsigned
245etna_ra_finish(struct etna_compile *c)
246{
247   /* TODO: better way to get number of registers used? */
248   unsigned j = 0;
249   for (unsigned i = 0; i < c->num_nodes; i++) {
250      j = MAX2(j, reg_get_base(c, ra_get_node_reg(c->g, i)) + 1);
251   }
252
253   ralloc_free(c->g);
254   ralloc_free(c->live_map);
255
256   return j;
257}
258