1/* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 * Christian Gmeiner <christian.gmeiner@gmail.com> 26 */ 27 28#include "etnaviv_screen.h" 29 30#include "hw/common.xml.h" 31 32#include "etnaviv_compiler.h" 33#include "etnaviv_context.h" 34#include "etnaviv_debug.h" 35#include "etnaviv_fence.h" 36#include "etnaviv_format.h" 37#include "etnaviv_query.h" 38#include "etnaviv_resource.h" 39#include "etnaviv_translate.h" 40 41#include "util/hash_table.h" 42#include "util/os_time.h" 43#include "util/u_math.h" 44#include "util/u_memory.h" 45#include "util/u_screen.h" 46#include "util/u_string.h" 47 48#include "frontend/drm_driver.h" 49 50#include "drm-uapi/drm_fourcc.h" 51 52#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) 53#define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2) 54 55static const struct debug_named_value etna_debug_options[] = { 56 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, 57 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, 58 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"}, 59 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"}, 60 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"}, 61 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"}, 62 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"}, 63 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"}, 64 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"}, 65 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"}, 66 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"}, 67 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"}, 68 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"}, 69 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, 70 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, 71 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, 72 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, 73 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"}, 74 {"nir", ETNA_DBG_NIR, "use new NIR compiler"}, 75 {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */ 76 {"nocache", ETNA_DBG_NOCACHE, "Disable shader cache"}, 77 DEBUG_NAMED_VALUE_END 78}; 79 80DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", etna_debug_options, 0) 81int etna_mesa_debug = 0; 82 83static void 84etna_screen_destroy(struct pipe_screen *pscreen) 85{ 86 struct etna_screen *screen = etna_screen(pscreen); 87 88 if (screen->perfmon) 89 etna_perfmon_del(screen->perfmon); 90 91 if (screen->compiler) 92 etna_compiler_destroy(screen->compiler); 93 94 if (screen->pipe) 95 etna_pipe_del(screen->pipe); 96 97 if (screen->gpu) 98 etna_gpu_del(screen->gpu); 99 100 if (screen->ro) 101 screen->ro->destroy(screen->ro); 102 103 if (screen->dev) 104 etna_device_del(screen->dev); 105 106 FREE(screen); 107} 108 109static const char * 110etna_screen_get_name(struct pipe_screen *pscreen) 111{ 112 struct etna_screen *priv = etna_screen(pscreen); 113 static char buffer[128]; 114 115 snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model, 116 priv->revision); 117 118 return buffer; 119} 120 121static const char * 122etna_screen_get_vendor(struct pipe_screen *pscreen) 123{ 124 return "etnaviv"; 125} 126 127static const char * 128etna_screen_get_device_vendor(struct pipe_screen *pscreen) 129{ 130 return "Vivante"; 131} 132 133static int 134etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 135{ 136 struct etna_screen *screen = etna_screen(pscreen); 137 138 switch (param) { 139 /* Supported features (boolean caps). */ 140 case PIPE_CAP_POINT_SPRITE: 141 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 144 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 145 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 146 case PIPE_CAP_VERTEX_SHADER_SATURATE: 147 case PIPE_CAP_TEXTURE_BARRIER: 148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 149 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 150 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 151 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 152 case PIPE_CAP_TGSI_TEXCOORD: 153 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 154 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 155 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 156 case PIPE_CAP_STRING_MARKER: 157 return 1; 158 case PIPE_CAP_NATIVE_FENCE_FD: 159 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; 160 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 161 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */ 162 return DBG_ENABLED(ETNA_DBG_NIR); 163 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL: 164 return 0; 165 166 /* Memory */ 167 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 168 return 256; 169 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 170 return 4; /* XXX could easily be supported */ 171 172 case PIPE_CAP_NPOT_TEXTURES: 173 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, 174 NON_POWER_OF_TWO); */ 175 176 case PIPE_CAP_ANISOTROPIC_FILTER: 177 case PIPE_CAP_TEXTURE_SWIZZLE: 178 case PIPE_CAP_PRIMITIVE_RESTART: 179 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 180 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 181 182 case PIPE_CAP_ALPHA_TEST: 183 if (DBG_ENABLED(ETNA_DBG_NIR)) 184 return !VIV_FEATURE(screen, chipMinorFeatures7, PE_NO_ALPHA_TEST); 185 else 186 return 1; 187 188 /* Unsupported features. */ 189 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 190 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 191 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 192 case PIPE_CAP_TEXRECT: 193 return 0; 194 195 /* Stream output. */ 196 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 197 return DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0; 198 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 199 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 200 return 0; 201 202 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 203 return 128; 204 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: 205 return 255; 206 case PIPE_CAP_MAX_VERTEX_BUFFERS: 207 return screen->specs.stream_count; 208 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 209 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 210 211 212 /* Texturing. */ 213 case PIPE_CAP_TEXTURE_SHADOW_MAP: 214 return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2; 215 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 216 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */ 217 return screen->specs.max_texture_size; 218 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 219 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 220 { 221 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); 222 assert(log2_max_tex_size > 0); 223 return log2_max_tex_size; 224 } 225 226 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 227 case PIPE_CAP_MIN_TEXEL_OFFSET: 228 return -8; 229 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 230 case PIPE_CAP_MAX_TEXEL_OFFSET: 231 return 7; 232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 233 return screen->specs.seamless_cube_map; 234 235 /* Queries. */ 236 case PIPE_CAP_OCCLUSION_QUERY: 237 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 238 239 /* Preferences */ 240 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 241 return 0; 242 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: { 243 /* etnaviv is being run on systems as small as 256MB total RAM so 244 * we need to provide a sane value for such a device. Limit the 245 * memory budget to min(~3% of pyhiscal memory, 64MB). 246 * 247 * a simple divison by 32 provides the numbers we want. 248 * 256MB / 32 = 8MB 249 * 2048MB / 32 = 64MB 250 */ 251 uint64_t system_memory; 252 253 if (!os_get_total_physical_memory(&system_memory)) 254 system_memory = (uint64_t)4096 << 20; 255 256 return MIN2(system_memory / 32, 64 * 1024 * 1024); 257 } 258 259 case PIPE_CAP_MAX_VARYINGS: 260 return screen->specs.max_varyings; 261 262 case PIPE_CAP_SUPPORTED_PRIM_MODES: 263 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: { 264 /* Generate the bitmask of supported draw primitives. */ 265 uint32_t modes = 1 << PIPE_PRIM_POINTS | 266 1 << PIPE_PRIM_LINES | 267 1 << PIPE_PRIM_LINE_STRIP | 268 1 << PIPE_PRIM_TRIANGLES | 269 1 << PIPE_PRIM_TRIANGLE_FAN; 270 271 /* TODO: The bug relates only to indexed draws, but here we signal 272 * that there is no support for triangle strips at all. This should 273 * be refined. 274 */ 275 if (VIV_FEATURE(screen, chipMinorFeatures2, BUG_FIXES8)) 276 modes |= 1 << PIPE_PRIM_TRIANGLE_STRIP; 277 278 if (VIV_FEATURE(screen, chipMinorFeatures2, LINE_LOOP)) 279 modes |= 1 << PIPE_PRIM_LINE_LOOP; 280 281 return modes; 282 } 283 284 case PIPE_CAP_PCI_GROUP: 285 case PIPE_CAP_PCI_BUS: 286 case PIPE_CAP_PCI_DEVICE: 287 case PIPE_CAP_PCI_FUNCTION: 288 return 0; 289 case PIPE_CAP_ACCELERATED: 290 return 1; 291 case PIPE_CAP_VIDEO_MEMORY: 292 return 0; 293 case PIPE_CAP_UMA: 294 return 1; 295 default: 296 return u_pipe_screen_get_param_defaults(pscreen, param); 297 } 298} 299 300static float 301etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 302{ 303 struct etna_screen *screen = etna_screen(pscreen); 304 305 switch (param) { 306 case PIPE_CAPF_MAX_LINE_WIDTH: 307 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 308 case PIPE_CAPF_MAX_POINT_WIDTH: 309 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 310 return 8192.0f; 311 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 312 return 16.0f; 313 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 314 return util_last_bit(screen->specs.max_texture_size); 315 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 316 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 317 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 318 return 0.0f; 319 } 320 321 debug_printf("unknown paramf %d", param); 322 return 0; 323} 324 325static int 326etna_screen_get_shader_param(struct pipe_screen *pscreen, 327 enum pipe_shader_type shader, 328 enum pipe_shader_cap param) 329{ 330 struct etna_screen *screen = etna_screen(pscreen); 331 bool ubo_enable = screen->specs.halti >= 2 && DBG_ENABLED(ETNA_DBG_NIR); 332 333 if (DBG_ENABLED(ETNA_DBG_DEQP)) 334 ubo_enable = true; 335 336 switch (shader) { 337 case PIPE_SHADER_FRAGMENT: 338 case PIPE_SHADER_VERTEX: 339 break; 340 case PIPE_SHADER_COMPUTE: 341 case PIPE_SHADER_GEOMETRY: 342 case PIPE_SHADER_TESS_CTRL: 343 case PIPE_SHADER_TESS_EVAL: 344 return 0; 345 default: 346 DBG("unknown shader type %d", shader); 347 return 0; 348 } 349 350 switch (param) { 351 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 352 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 353 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 354 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 355 return ETNA_MAX_TOKENS; 356 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 357 return ETNA_MAX_DEPTH; /* XXX */ 358 case PIPE_SHADER_CAP_MAX_INPUTS: 359 /* Maximum number of inputs for the vertex shader is the number 360 * of vertex elements - each element defines one vertex shader 361 * input register. For the fragment shader, this is the number 362 * of varyings. */ 363 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings 364 : screen->specs.vertex_max_elements; 365 case PIPE_SHADER_CAP_MAX_OUTPUTS: 366 return 16; /* see VIVS_VS_OUTPUT */ 367 case PIPE_SHADER_CAP_MAX_TEMPS: 368 return 64; /* Max native temporaries. */ 369 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 370 return ubo_enable ? ETNA_MAX_CONST_BUF : 1; 371 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 372 return 1; 373 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 374 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 375 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 376 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 377 return 1; 378 case PIPE_SHADER_CAP_SUBROUTINES: 379 return 0; 380 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 381 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 382 case PIPE_SHADER_CAP_INT64_ATOMICS: 383 case PIPE_SHADER_CAP_FP16: 384 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 385 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 386 case PIPE_SHADER_CAP_INT16: 387 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 388 return 0; 389 case PIPE_SHADER_CAP_INTEGERS: 390 return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2; 391 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 392 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 393 return shader == PIPE_SHADER_FRAGMENT 394 ? screen->specs.fragment_sampler_count 395 : screen->specs.vertex_sampler_count; 396 case PIPE_SHADER_CAP_PREFERRED_IR: 397 return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; 398 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 399 if (ubo_enable) 400 return 16384; /* 16384 so state tracker enables UBOs */ 401 return shader == PIPE_SHADER_FRAGMENT 402 ? screen->specs.max_ps_uniforms * sizeof(float[4]) 403 : screen->specs.max_vs_uniforms * sizeof(float[4]); 404 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 405 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 406 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 407 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 408 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 409 return false; 410 case PIPE_SHADER_CAP_SUPPORTED_IRS: 411 return (1 << PIPE_SHADER_IR_TGSI) | 412 (DBG_ENABLED(ETNA_DBG_NIR) ? 1 << PIPE_SHADER_IR_NIR : 0); 413 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 414 return 32; 415 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 417 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 418 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 419 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 420 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 421 return 0; 422 } 423 424 debug_printf("unknown shader param %d", param); 425 return 0; 426} 427 428static uint64_t 429etna_screen_get_timestamp(struct pipe_screen *pscreen) 430{ 431 return os_time_get_nano(); 432} 433 434static bool 435gpu_supports_texture_target(struct etna_screen *screen, 436 enum pipe_texture_target target) 437{ 438 if (target == PIPE_TEXTURE_CUBE_ARRAY) 439 return false; 440 441 /* pre-halti has no array/3D */ 442 if (screen->specs.halti < 0 && 443 (target == PIPE_TEXTURE_1D_ARRAY || 444 target == PIPE_TEXTURE_2D_ARRAY || 445 target == PIPE_TEXTURE_3D)) 446 return false; 447 448 return true; 449} 450 451static bool 452gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt, 453 enum pipe_format format) 454{ 455 bool supported = true; 456 457 if (fmt == TEXTURE_FORMAT_ETC1) 458 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); 459 460 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) 461 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); 462 463 if (util_format_is_srgb(format)) 464 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 465 466 if (fmt & EXT_FORMAT) 467 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 468 469 if (fmt & ASTC_FORMAT) { 470 supported = screen->specs.tex_astc; 471 } 472 473 if (util_format_is_snorm(format)) 474 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); 475 476 if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM && 477 (util_format_is_pure_integer(format) || util_format_is_float(format))) 478 supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 479 480 481 if (!supported) 482 return false; 483 484 if (texture_format_needs_swiz(format)) 485 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 486 487 return true; 488} 489 490static bool 491gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format, 492 unsigned sample_count) 493{ 494 const uint32_t fmt = translate_pe_format(format); 495 496 if (fmt == ETNA_NO_MATCH) 497 return false; 498 499 /* MSAA is broken */ 500 if (sample_count > 1) 501 return false; 502 503 if (format == PIPE_FORMAT_R8_UNORM) 504 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); 505 506 /* figure out 8bpp RS clear to enable these formats */ 507 if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT) 508 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); 509 510 if (util_format_is_srgb(format)) 511 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3); 512 513 if (util_format_is_pure_integer(format) || util_format_is_float(format)) 514 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 515 516 if (format == PIPE_FORMAT_R8G8_UNORM) 517 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 518 519 /* any other extended format is HALTI0 (only R10G10B10A2?) */ 520 if (fmt >= PE_FORMAT_R16F) 521 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 522 523 return true; 524} 525 526static bool 527gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format) 528{ 529 if (translate_vertex_format_type(format) == ETNA_NO_MATCH) 530 return false; 531 532 if (util_format_is_pure_integer(format)) 533 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 534 535 return true; 536} 537 538static bool 539etna_screen_is_format_supported(struct pipe_screen *pscreen, 540 enum pipe_format format, 541 enum pipe_texture_target target, 542 unsigned sample_count, 543 unsigned storage_sample_count, 544 unsigned usage) 545{ 546 struct etna_screen *screen = etna_screen(pscreen); 547 unsigned allowed = 0; 548 549 if (!gpu_supports_texture_target(screen, target)) 550 return false; 551 552 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 553 return false; 554 555 if (usage & PIPE_BIND_RENDER_TARGET) { 556 if (gpu_supports_render_format(screen, format, sample_count)) 557 allowed |= PIPE_BIND_RENDER_TARGET; 558 } 559 560 if (usage & PIPE_BIND_DEPTH_STENCIL) { 561 if (translate_depth_format(format) != ETNA_NO_MATCH) 562 allowed |= PIPE_BIND_DEPTH_STENCIL; 563 } 564 565 if (usage & PIPE_BIND_SAMPLER_VIEW) { 566 uint32_t fmt = translate_texture_format(format); 567 568 if (!gpu_supports_texture_format(screen, fmt, format)) 569 fmt = ETNA_NO_MATCH; 570 571 if (sample_count < 2 && fmt != ETNA_NO_MATCH) 572 allowed |= PIPE_BIND_SAMPLER_VIEW; 573 } 574 575 if (usage & PIPE_BIND_VERTEX_BUFFER) { 576 if (gpu_supports_vertex_format(screen, format)) 577 allowed |= PIPE_BIND_VERTEX_BUFFER; 578 } 579 580 if (usage & PIPE_BIND_INDEX_BUFFER) { 581 /* must be supported index format */ 582 if (format == PIPE_FORMAT_R8_UINT || format == PIPE_FORMAT_R16_UINT || 583 (format == PIPE_FORMAT_R32_UINT && 584 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { 585 allowed |= PIPE_BIND_INDEX_BUFFER; 586 } 587 } 588 589 /* Always allowed */ 590 allowed |= 591 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); 592 593 if (usage != allowed) { 594 DBG("not supported: format=%s, target=%d, sample_count=%d, " 595 "usage=%x, allowed=%x", 596 util_format_name(format), target, sample_count, usage, allowed); 597 } 598 599 return usage == allowed; 600} 601 602const uint64_t supported_modifiers[] = { 603 DRM_FORMAT_MOD_LINEAR, 604 DRM_FORMAT_MOD_VIVANTE_TILED, 605 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED, 606 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED, 607 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED, 608}; 609 610static bool modifier_num_supported(struct pipe_screen *pscreen, int num) 611{ 612 struct etna_screen *screen = etna_screen(pscreen); 613 614 /* don't advertise split tiled formats on single pipe/buffer GPUs */ 615 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) && 616 num >= 3) 617 return false; 618 619 return true; 620} 621 622static void 623etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 624 enum pipe_format format, int max, 625 uint64_t *modifiers, 626 unsigned int *external_only, int *count) 627{ 628 int i, num_modifiers = 0; 629 630 if (max > ARRAY_SIZE(supported_modifiers)) 631 max = ARRAY_SIZE(supported_modifiers); 632 633 if (!max) { 634 modifiers = NULL; 635 max = ARRAY_SIZE(supported_modifiers); 636 } 637 638 for (i = 0; num_modifiers < max; i++) { 639 if (!modifier_num_supported(pscreen, i)) 640 break; 641 642 if (modifiers) 643 modifiers[num_modifiers] = supported_modifiers[i]; 644 if (external_only) 645 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0; 646 num_modifiers++; 647 } 648 649 *count = num_modifiers; 650} 651 652static bool 653etna_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen, 654 uint64_t modifier, 655 enum pipe_format format, 656 bool *external_only) 657{ 658 int i; 659 660 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) { 661 if (!modifier_num_supported(pscreen, i)) 662 break; 663 664 if (modifier == supported_modifiers[i]) { 665 if (external_only) 666 *external_only = util_format_is_yuv(format) ? 1 : 0; 667 668 return true; 669 } 670 } 671 672 return false; 673} 674 675static void 676etna_determine_uniform_limits(struct etna_screen *screen) 677{ 678 /* values for the non unified case are taken from 679 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file 680 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h. 681 */ 682 if (screen->model == chipModel_GC2000 && 683 (screen->revision == 0x5118 || screen->revision == 0x5140)) { 684 screen->specs.max_vs_uniforms = 256; 685 screen->specs.max_ps_uniforms = 64; 686 } else if (screen->specs.num_constants == 320) { 687 screen->specs.max_vs_uniforms = 256; 688 screen->specs.max_ps_uniforms = 64; 689 } else if (screen->specs.num_constants > 256 && 690 screen->model == chipModel_GC1000) { 691 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */ 692 screen->specs.max_vs_uniforms = 256; 693 screen->specs.max_ps_uniforms = 64; 694 } else if (screen->specs.num_constants > 256) { 695 screen->specs.max_vs_uniforms = 256; 696 screen->specs.max_ps_uniforms = 256; 697 } else if (screen->specs.num_constants == 256) { 698 screen->specs.max_vs_uniforms = 256; 699 screen->specs.max_ps_uniforms = 256; 700 } else { 701 screen->specs.max_vs_uniforms = 168; 702 screen->specs.max_ps_uniforms = 64; 703 } 704} 705 706static void 707etna_determine_sampler_limits(struct etna_screen *screen) 708{ 709 /* vertex and fragment samplers live in one address space */ 710 if (screen->specs.halti >= 1) { 711 screen->specs.vertex_sampler_offset = 16; 712 screen->specs.fragment_sampler_count = 16; 713 screen->specs.vertex_sampler_count = 16; 714 } else { 715 screen->specs.vertex_sampler_offset = 8; 716 screen->specs.fragment_sampler_count = 8; 717 screen->specs.vertex_sampler_count = 4; 718 } 719 720 if (screen->model == 0x400) 721 screen->specs.vertex_sampler_count = 0; 722} 723 724static bool 725etna_get_specs(struct etna_screen *screen) 726{ 727 uint64_t val; 728 uint32_t instruction_count; 729 730 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { 731 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); 732 goto fail; 733 } 734 instruction_count = val; 735 736 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, 737 &val)) { 738 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); 739 goto fail; 740 } 741 screen->specs.vertex_output_buffer_size = val; 742 743 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { 744 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); 745 goto fail; 746 } 747 screen->specs.vertex_cache_size = val; 748 749 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { 750 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); 751 goto fail; 752 } 753 screen->specs.shader_core_count = val; 754 755 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { 756 DBG("could not get ETNA_GPU_STREAM_COUNT"); 757 goto fail; 758 } 759 screen->specs.stream_count = val; 760 761 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { 762 DBG("could not get ETNA_GPU_REGISTER_MAX"); 763 goto fail; 764 } 765 screen->specs.max_registers = val; 766 767 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { 768 DBG("could not get ETNA_GPU_PIXEL_PIPES"); 769 goto fail; 770 } 771 screen->specs.pixel_pipes = val; 772 773 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { 774 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); 775 goto fail; 776 } 777 if (val == 0) { 778 fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); 779 val = 168; 780 } 781 screen->specs.num_constants = val; 782 783 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_VARYINGS, &val)) { 784 DBG("could not get ETNA_GPU_NUM_VARYINGS"); 785 goto fail; 786 } 787 screen->specs.max_varyings = MAX2(val, ETNA_NUM_VARYINGS); 788 789 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific 790 * description of the differences. */ 791 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) 792 screen->specs.halti = 5; /* New GC7000/GC8x00 */ 793 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) 794 screen->specs.halti = 4; /* Old GC7000/GC7400 */ 795 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) 796 screen->specs.halti = 3; /* None? */ 797 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) 798 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ 799 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) 800 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ 801 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) 802 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ 803 else 804 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ 805 if (screen->specs.halti >= 0) 806 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); 807 else 808 DBG("etnaviv: GPU arch: pre-HALTI"); 809 810 screen->specs.can_supertile = 811 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); 812 screen->specs.bits_per_tile = 813 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; 814 screen->specs.ts_clear_value = 815 VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE) ? 0xffffffff : 816 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : 817 0x11111111; 818 819 screen->specs.vs_need_z_div = 820 screen->model < 0x1000 && screen->model != 0x880; 821 screen->specs.has_sin_cos_sqrt = 822 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 823 screen->specs.has_sign_floor_ceil = 824 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); 825 screen->specs.has_shader_range_registers = 826 screen->model >= 0x1000 || screen->model == 0x880; 827 screen->specs.npot_tex_any_wrap = 828 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); 829 screen->specs.has_new_transcendentals = 830 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); 831 screen->specs.has_halti2_instructions = 832 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 833 screen->specs.v4_compression = 834 VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION); 835 screen->specs.seamless_cube_map = 836 (screen->model != 0x880) && /* Seamless cubemap is broken on GC880? */ 837 VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP); 838 839 if (screen->specs.halti >= 5) { 840 /* GC7000 - this core must load shaders from memory. */ 841 screen->specs.vs_offset = 0; 842 screen->specs.ps_offset = 0; 843 screen->specs.max_instructions = 0; /* Do not program shaders manually */ 844 screen->specs.has_icache = true; 845 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { 846 /* GC3000 - this core is capable of loading shaders from 847 * memory. It can also run shaders from registers, as a fallback, but 848 * "max_instructions" does not have the correct value. It has place for 849 * 2*256 instructions just like GC2000, but the offsets are slightly 850 * different. 851 */ 852 screen->specs.vs_offset = 0xC000; 853 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses 854 * this mirror for writing PS instructions, probably safest to do the 855 * same. 856 */ 857 screen->specs.ps_offset = 0x8000 + 0x1000; 858 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ 859 screen->specs.has_icache = true; 860 } else { 861 if (instruction_count > 256) { /* unified instruction memory? */ 862 screen->specs.vs_offset = 0xC000; 863 screen->specs.ps_offset = 0xD000; /* like vivante driver */ 864 screen->specs.max_instructions = 256; 865 } else { 866 screen->specs.vs_offset = 0x4000; 867 screen->specs.ps_offset = 0x6000; 868 screen->specs.max_instructions = instruction_count / 2; 869 } 870 screen->specs.has_icache = false; 871 } 872 873 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { 874 screen->specs.vertex_max_elements = 16; 875 } else { 876 /* Etna_viv documentation seems confused over the correct value 877 * here so choose the lower to be safe: HALTI0 says 16 i.s.o. 878 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ 879 screen->specs.vertex_max_elements = 10; 880 } 881 882 etna_determine_uniform_limits(screen); 883 etna_determine_sampler_limits(screen); 884 885 if (screen->specs.halti >= 5) { 886 screen->specs.has_unified_uniforms = true; 887 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); 888 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); 889 } else if (screen->specs.halti >= 1) { 890 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess 891 */ 892 screen->specs.has_unified_uniforms = true; 893 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); 894 /* hardcode PS uniforms to start after end of VS uniforms - 895 * for more flexibility this offset could be variable based on the 896 * shader. 897 */ 898 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); 899 } else { 900 screen->specs.has_unified_uniforms = false; 901 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); 902 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); 903 } 904 905 screen->specs.max_texture_size = 906 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; 907 screen->specs.max_rendertarget_size = 908 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; 909 910 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); 911 if (screen->specs.single_buffer) 912 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); 913 914 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) && 915 !VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC); 916 917 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); 918 919 return true; 920 921fail: 922 return false; 923} 924 925struct etna_bo * 926etna_screen_bo_from_handle(struct pipe_screen *pscreen, 927 struct winsys_handle *whandle) 928{ 929 struct etna_screen *screen = etna_screen(pscreen); 930 struct etna_bo *bo; 931 932 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 933 bo = etna_bo_from_name(screen->dev, whandle->handle); 934 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 935 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle); 936 } else { 937 DBG("Attempt to import unsupported handle type %d", whandle->type); 938 return NULL; 939 } 940 941 if (!bo) { 942 DBG("ref name 0x%08x failed", whandle->handle); 943 return NULL; 944 } 945 946 return bo; 947} 948 949static const void * 950etna_get_compiler_options(struct pipe_screen *pscreen, 951 enum pipe_shader_ir ir, unsigned shader) 952{ 953 return &etna_screen(pscreen)->options; 954} 955 956static struct disk_cache * 957etna_get_disk_shader_cache(struct pipe_screen *pscreen) 958{ 959 struct etna_screen *screen = etna_screen(pscreen); 960 struct etna_compiler *compiler = screen->compiler; 961 962 return compiler->disk_cache; 963} 964 965struct pipe_screen * 966etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, 967 struct renderonly *ro) 968{ 969 struct etna_screen *screen = CALLOC_STRUCT(etna_screen); 970 struct pipe_screen *pscreen; 971 uint64_t val; 972 973 if (!screen) 974 return NULL; 975 976 pscreen = &screen->base; 977 screen->dev = dev; 978 screen->gpu = gpu; 979 screen->ro = ro; 980 screen->refcnt = 1; 981 982 screen->drm_version = etnaviv_device_version(screen->dev); 983 etna_mesa_debug = debug_get_option_etna_mesa_debug(); 984 985 /* Disable autodisable for correct rendering with TS */ 986 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; 987 988 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); 989 if (!screen->pipe) { 990 DBG("could not create 3d pipe"); 991 goto fail; 992 } 993 994 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { 995 DBG("could not get ETNA_GPU_MODEL"); 996 goto fail; 997 } 998 screen->model = val; 999 1000 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { 1001 DBG("could not get ETNA_GPU_REVISION"); 1002 goto fail; 1003 } 1004 screen->revision = val; 1005 1006 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { 1007 DBG("could not get ETNA_GPU_FEATURES_0"); 1008 goto fail; 1009 } 1010 screen->features[0] = val; 1011 1012 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { 1013 DBG("could not get ETNA_GPU_FEATURES_1"); 1014 goto fail; 1015 } 1016 screen->features[1] = val; 1017 1018 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { 1019 DBG("could not get ETNA_GPU_FEATURES_2"); 1020 goto fail; 1021 } 1022 screen->features[2] = val; 1023 1024 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { 1025 DBG("could not get ETNA_GPU_FEATURES_3"); 1026 goto fail; 1027 } 1028 screen->features[3] = val; 1029 1030 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { 1031 DBG("could not get ETNA_GPU_FEATURES_4"); 1032 goto fail; 1033 } 1034 screen->features[4] = val; 1035 1036 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { 1037 DBG("could not get ETNA_GPU_FEATURES_5"); 1038 goto fail; 1039 } 1040 screen->features[5] = val; 1041 1042 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { 1043 DBG("could not get ETNA_GPU_FEATURES_6"); 1044 goto fail; 1045 } 1046 screen->features[6] = val; 1047 1048 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) { 1049 DBG("could not get ETNA_GPU_FEATURES_7"); 1050 goto fail; 1051 } 1052 screen->features[7] = val; 1053 1054 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_8, &val)) { 1055 DBG("could not get ETNA_GPU_FEATURES_8"); 1056 goto fail; 1057 } 1058 screen->features[8] = val; 1059 1060 if (!etna_get_specs(screen)) 1061 goto fail; 1062 1063 if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) { 1064 DBG("halti5 requires softpin"); 1065 goto fail; 1066 } 1067 1068 screen->options = (nir_shader_compiler_options) { 1069 .lower_fpow = true, 1070 .lower_ftrunc = true, 1071 .fuse_ffma16 = true, 1072 .fuse_ffma32 = true, 1073 .fuse_ffma64 = true, 1074 .lower_bitops = true, 1075 .lower_all_io_to_temps = true, 1076 .vertex_id_zero_based = true, 1077 .lower_flrp32 = true, 1078 .lower_fmod = true, 1079 .lower_vector_cmp = true, 1080 .lower_fdph = true, 1081 .lower_insert_byte = true, 1082 .lower_insert_word = true, 1083 .lower_fdiv = true, /* !screen->specs.has_new_transcendentals */ 1084 .lower_fsign = !screen->specs.has_sign_floor_ceil, 1085 .lower_ffloor = !screen->specs.has_sign_floor_ceil, 1086 .lower_fceil = !screen->specs.has_sign_floor_ceil, 1087 .lower_fsqrt = !screen->specs.has_sin_cos_sqrt, 1088 .lower_sincos = !screen->specs.has_sin_cos_sqrt, 1089 .lower_uniforms_to_ubo = screen->specs.halti >= 2, 1090 .force_indirect_unrolling = nir_var_all, 1091 }; 1092 1093 /* apply debug options that disable individual features */ 1094 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) 1095 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; 1096 if (DBG_ENABLED(ETNA_DBG_NO_TS)) 1097 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 1098 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) 1099 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; 1100 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) 1101 screen->specs.can_supertile = 0; 1102 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) 1103 screen->specs.single_buffer = 0; 1104 1105 pscreen->destroy = etna_screen_destroy; 1106 pscreen->get_param = etna_screen_get_param; 1107 pscreen->get_paramf = etna_screen_get_paramf; 1108 pscreen->get_shader_param = etna_screen_get_shader_param; 1109 pscreen->get_compiler_options = etna_get_compiler_options; 1110 pscreen->get_disk_shader_cache = etna_get_disk_shader_cache; 1111 1112 pscreen->get_name = etna_screen_get_name; 1113 pscreen->get_vendor = etna_screen_get_vendor; 1114 pscreen->get_device_vendor = etna_screen_get_device_vendor; 1115 1116 pscreen->get_timestamp = etna_screen_get_timestamp; 1117 pscreen->context_create = etna_context_create; 1118 pscreen->is_format_supported = etna_screen_is_format_supported; 1119 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; 1120 pscreen->is_dmabuf_modifier_supported = etna_screen_is_dmabuf_modifier_supported; 1121 1122 screen->compiler = etna_compiler_create(etna_screen_get_name(pscreen)); 1123 if (!screen->compiler) 1124 goto fail; 1125 1126 etna_fence_screen_init(pscreen); 1127 etna_query_screen_init(pscreen); 1128 etna_resource_screen_init(pscreen); 1129 1130 util_dynarray_init(&screen->supported_pm_queries, NULL); 1131 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); 1132 1133 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) 1134 etna_pm_query_setup(screen); 1135 1136 return pscreen; 1137 1138fail: 1139 etna_screen_destroy(pscreen); 1140 return NULL; 1141} 1142