1/* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 * Christian Gmeiner <christian.gmeiner@gmail.com> 26 */ 27 28#include "etnaviv_state.h" 29 30#include "hw/common.xml.h" 31 32#include "etnaviv_blend.h" 33#include "etnaviv_clear_blit.h" 34#include "etnaviv_context.h" 35#include "etnaviv_format.h" 36#include "etnaviv_rasterizer.h" 37#include "etnaviv_screen.h" 38#include "etnaviv_shader.h" 39#include "etnaviv_surface.h" 40#include "etnaviv_translate.h" 41#include "etnaviv_util.h" 42#include "etnaviv_zsa.h" 43#include "util/u_framebuffer.h" 44#include "util/u_helpers.h" 45#include "util/u_inlines.h" 46#include "util/u_math.h" 47#include "util/u_memory.h" 48#include "util/u_upload_mgr.h" 49 50static void 51etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref sr) 52{ 53 struct etna_context *ctx = etna_context(pctx); 54 struct compiled_stencil_ref *cs = &ctx->stencil_ref; 55 56 ctx->stencil_ref_s = sr; 57 58 for (unsigned i = 0; i < 2; i++) { 59 cs->PE_STENCIL_CONFIG[i] = 60 VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr.ref_value[i]); 61 cs->PE_STENCIL_CONFIG_EXT[i] = 62 VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr.ref_value[!i]); 63 } 64 ctx->dirty |= ETNA_DIRTY_STENCIL_REF; 65} 66 67static void 68etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs) 69{ 70 /* NOOP */ 71} 72 73static void 74etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask) 75{ 76 struct etna_context *ctx = etna_context(pctx); 77 78 ctx->sample_mask = sample_mask; 79 ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK; 80} 81 82static void 83etna_set_constant_buffer(struct pipe_context *pctx, 84 enum pipe_shader_type shader, uint index, bool take_ownership, 85 const struct pipe_constant_buffer *cb) 86{ 87 struct etna_context *ctx = etna_context(pctx); 88 struct etna_constbuf_state *so = &ctx->constant_buffer[shader]; 89 90 assert(index < ETNA_MAX_CONST_BUF); 91 92 util_copy_constant_buffer(&so->cb[index], cb, take_ownership); 93 94 /* Note that the gallium frontends can unbind constant buffers by 95 * passing NULL here. */ 96 if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) { 97 so->enabled_mask &= ~(1 << index); 98 return; 99 } 100 101 assert(index != 0 || cb->user_buffer != NULL); 102 103 if (!cb->buffer) { 104 struct pipe_constant_buffer *cb = &so->cb[index]; 105 u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer); 106 } 107 108 so->enabled_mask |= 1 << index; 109 ctx->dirty |= ETNA_DIRTY_CONSTBUF; 110} 111 112static void 113etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base) 114{ 115 struct etna_resource *to = base, *from = base; 116 117 if (base->texture && etna_resource_newer(etna_resource(base->texture), base)) 118 from = etna_resource(base->texture); 119 120 if (base->render) 121 to = etna_resource(base->render); 122 123 if ((to != from) && etna_resource_older(to, from)) { 124 etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level); 125 to->seqno = from->seqno; 126 } 127} 128 129static void 130etna_set_framebuffer_state(struct pipe_context *pctx, 131 const struct pipe_framebuffer_state *fb) 132{ 133 struct etna_context *ctx = etna_context(pctx); 134 struct etna_screen *screen = ctx->screen; 135 struct compiled_framebuffer_state *cs = &ctx->framebuffer; 136 int nr_samples_color = -1; 137 int nr_samples_depth = -1; 138 139 /* Set up TS as well. Warning: this state is used by both the RS and PE */ 140 uint32_t ts_mem_config = 0; 141 uint32_t pe_mem_config = 0; 142 uint32_t pe_logic_op = 0; 143 144 if (fb->nr_cbufs > 0) { /* at least one color buffer? */ 145 struct etna_surface *cbuf = etna_surface(fb->cbufs[0]); 146 struct etna_resource *res = etna_resource(cbuf->base.texture); 147 bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0; 148 uint32_t fmt = translate_pe_format(cbuf->base.format); 149 150 assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */ 151 etna_update_render_resource(pctx, etna_resource(cbuf->prsc)); 152 153 if (fmt >= PE_FORMAT_R16F) 154 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) | 155 VIVS_PE_COLOR_FORMAT_FORMAT_MASK; 156 else 157 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt); 158 159 cs->PE_COLOR_FORMAT |= 160 VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | 161 VIVS_PE_COLOR_FORMAT_OVERWRITE | 162 COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) | 163 COND(color_supertiled && screen->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); 164 /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and 165 * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state 166 * but only if we set the bits above. */ 167 /* merged with depth_stencil_alpha */ 168 if ((cbuf->surf.offset & 63) || 169 (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) { 170 /* XXX Must make temporary surface here. 171 * Need the same mechanism on gc2000 when we want to do mipmap 172 * generation by 173 * rendering to levels > 1 due to multitiled / tiled conversion. */ 174 BUG("Alignment error, trying to render to offset %08x with tile " 175 "stride %i", 176 cbuf->surf.offset, cbuf->surf.stride * 4); 177 } 178 179 if (screen->specs.pixel_pipes == 1) { 180 cs->PE_COLOR_ADDR = cbuf->reloc[0]; 181 cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 182 } else { 183 /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */ 184 assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer); 185 for (int i = 0; i < screen->specs.pixel_pipes; i++) { 186 cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i]; 187 cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 188 } 189 } 190 cs->PE_COLOR_STRIDE = cbuf->surf.stride; 191 192 if (cbuf->surf.ts_size) { 193 cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value; 194 cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32; 195 196 cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc; 197 cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 198 199 cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0]; 200 cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 201 202 pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode); 203 204 if (cbuf->level->ts_compress_fmt >= 0) { 205 /* overwrite bit breaks v1/v2 compression */ 206 if (!screen->specs.v4_compression) 207 cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE; 208 209 ts_mem_config |= 210 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION | 211 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt); 212 } 213 } 214 215 nr_samples_color = cbuf->base.texture->nr_samples; 216 217 if (util_format_is_srgb(cbuf->base.format)) 218 pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB; 219 220 cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0); 221 cs->PS_CONTROL_EXT = 222 VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5)); 223 } else { 224 /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and 225 * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the 226 * color target */ 227 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE; 228 cs->PE_COLOR_STRIDE = 0; 229 cs->TS_COLOR_STATUS_BASE.bo = NULL; 230 cs->TS_COLOR_SURFACE_BASE.bo = NULL; 231 232 cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc; 233 for (int i = 0; i < screen->specs.pixel_pipes; i++) 234 cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc; 235 } 236 237 if (fb->zsbuf != NULL) { 238 struct etna_surface *zsbuf = etna_surface(fb->zsbuf); 239 struct etna_resource *res = etna_resource(zsbuf->base.texture); 240 241 etna_update_render_resource(pctx, etna_resource(zsbuf->prsc)); 242 243 assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */ 244 245 uint32_t depth_format = translate_depth_format(zsbuf->base.format); 246 unsigned depth_bits = 247 depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24; 248 bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0; 249 250 cs->PE_DEPTH_CONFIG = 251 depth_format | 252 COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) | 253 VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z | 254 VIVS_PE_DEPTH_CONFIG_UNK18; /* something to do with clipping? */ 255 /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ 256 /* merged with depth_stencil_alpha */ 257 258 if (screen->specs.pixel_pipes == 1) { 259 cs->PE_DEPTH_ADDR = zsbuf->reloc[0]; 260 cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 261 } else { 262 for (int i = 0; i < screen->specs.pixel_pipes; i++) { 263 cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i]; 264 cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 265 } 266 } 267 268 cs->PE_DEPTH_STRIDE = zsbuf->surf.stride; 269 cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED; 270 cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f); 271 272 if (zsbuf->surf.ts_size) { 273 cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value; 274 275 cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc; 276 cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 277 278 cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0]; 279 cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 280 281 pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode); 282 283 if (zsbuf->level->ts_compress_fmt >= 0) { 284 ts_mem_config |= 285 VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION | 286 COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8, 287 VIVS_TS_MEM_CONFIG_STENCIL_ENABLE); 288 } 289 } 290 291 ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP); 292 293 nr_samples_depth = zsbuf->base.texture->nr_samples; 294 } else { 295 cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE; 296 cs->PE_DEPTH_ADDR.bo = NULL; 297 cs->PE_DEPTH_STRIDE = 0; 298 cs->TS_DEPTH_STATUS_BASE.bo = NULL; 299 cs->TS_DEPTH_SURFACE_BASE.bo = NULL; 300 301 for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++) 302 cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL; 303 } 304 305 /* MSAA setup */ 306 if (nr_samples_depth != -1 && nr_samples_color != -1 && 307 nr_samples_depth != nr_samples_color) { 308 BUG("Number of samples in color and depth texture must match (%i and %i respectively)", 309 nr_samples_color, nr_samples_depth); 310 } 311 312 switch (MAX2(nr_samples_depth, nr_samples_color)) { 313 case 0: 314 case 1: /* Are 0 and 1 samples allowed? */ 315 cs->GL_MULTI_SAMPLE_CONFIG = 316 VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE; 317 cs->msaa_mode = false; 318 break; 319 case 2: 320 cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X; 321 cs->msaa_mode = true; /* Add input to PS */ 322 cs->RA_MULTISAMPLE_UNK00E04 = 0x0; 323 cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22; 324 cs->RA_CENTROID_TABLE[0] = 0x66aa2288; 325 cs->RA_CENTROID_TABLE[1] = 0x88558800; 326 cs->RA_CENTROID_TABLE[2] = 0x88881100; 327 cs->RA_CENTROID_TABLE[3] = 0x33888800; 328 break; 329 case 4: 330 cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X; 331 cs->msaa_mode = true; /* Add input to PS */ 332 cs->RA_MULTISAMPLE_UNK00E04 = 0x0; 333 cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26; 334 cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a; 335 cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22; 336 cs->RA_CENTROID_TABLE[0] = 0x4a6e2688; 337 cs->RA_CENTROID_TABLE[1] = 0x888888a2; 338 cs->RA_CENTROID_TABLE[2] = 0x888888ea; 339 cs->RA_CENTROID_TABLE[3] = 0x888888c6; 340 cs->RA_CENTROID_TABLE[4] = 0x46622a88; 341 cs->RA_CENTROID_TABLE[5] = 0x888888ae; 342 cs->RA_CENTROID_TABLE[6] = 0x888888e6; 343 cs->RA_CENTROID_TABLE[7] = 0x888888ca; 344 cs->RA_CENTROID_TABLE[8] = 0x262a2288; 345 cs->RA_CENTROID_TABLE[9] = 0x886688a2; 346 cs->RA_CENTROID_TABLE[10] = 0x888866aa; 347 cs->RA_CENTROID_TABLE[11] = 0x668888a6; 348 break; 349 } 350 351 cs->TS_MEM_CONFIG = ts_mem_config; 352 cs->PE_MEM_CONFIG = pe_mem_config; 353 354 /* Single buffer setup. There is only one switch for this, not a separate 355 * one per color buffer / depth buffer. To keep the logic simple always use 356 * single buffer when this feature is available. 357 * note: the blob will use 2 in some situations, figure out why? 358 */ 359 pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen->specs.single_buffer ? 3 : 0); 360 cs->PE_LOGIC_OP = pe_logic_op; 361 362 /* keep copy of original structure */ 363 util_copy_framebuffer_state(&ctx->framebuffer_s, fb); 364 ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS; 365} 366 367static void 368etna_set_polygon_stipple(struct pipe_context *pctx, 369 const struct pipe_poly_stipple *stipple) 370{ 371 /* NOP */ 372} 373 374static void 375etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot, 376 unsigned num_scissors, const struct pipe_scissor_state *ss) 377{ 378 struct etna_context *ctx = etna_context(pctx); 379 assert(ss->minx <= ss->maxx); 380 assert(ss->miny <= ss->maxy); 381 382 ctx->scissor = *ss; 383 ctx->dirty |= ETNA_DIRTY_SCISSOR; 384} 385 386static void 387etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot, 388 unsigned num_scissors, const struct pipe_viewport_state *vs) 389{ 390 struct etna_context *ctx = etna_context(pctx); 391 struct compiled_viewport_state *cs = &ctx->viewport; 392 393 ctx->viewport_s = *vs; 394 /** 395 * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of 396 * -1..1 to 0..1. 397 * scaling and translation to 0..1 already happened, so remove that 398 * 399 * z' = (z * 2 - 1) * scale + translate 400 * = z * (2 * scale) + (translate - scale) 401 * 402 * scale' = 2 * scale 403 * translate' = translate - scale 404 */ 405 406 /* must be fixp as v4 state deltas assume it is */ 407 cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]); 408 cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]); 409 cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f); 410 cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]); 411 cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]); 412 cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]); 413 414 /* Compute scissor rectangle (fixp) from viewport. 415 * Make sure left is always < right and top always < bottom. 416 */ 417 cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f); 418 cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f); 419 cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f)); 420 cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f)); 421 422 cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */ 423 cs->PE_DEPTH_FAR = fui(1.0); 424 ctx->dirty |= ETNA_DIRTY_VIEWPORT; 425} 426 427static void 428etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot, 429 unsigned num_buffers, unsigned unbind_num_trailing_slots, bool take_ownership, 430 const struct pipe_vertex_buffer *vb) 431{ 432 struct etna_context *ctx = etna_context(pctx); 433 struct etna_vertexbuf_state *so = &ctx->vertex_buffer; 434 435 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, 436 num_buffers, unbind_num_trailing_slots, 437 take_ownership); 438 so->count = util_last_bit(so->enabled_mask); 439 440 for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) { 441 struct compiled_set_vertex_buffer *cs = &so->cvb[idx]; 442 struct pipe_vertex_buffer *vbi = &so->vb[idx]; 443 444 assert(!vbi->is_user_buffer); /* XXX support user_buffer using 445 etna_usermem_map */ 446 447 if (vbi->buffer.resource) { /* GPU buffer */ 448 cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo; 449 cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset; 450 cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ; 451 cs->FE_VERTEX_STREAM_CONTROL = 452 FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride); 453 } else { 454 cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL; 455 cs->FE_VERTEX_STREAM_CONTROL = 0; 456 } 457 } 458 459 ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS; 460} 461 462static void 463etna_blend_state_bind(struct pipe_context *pctx, void *bs) 464{ 465 struct etna_context *ctx = etna_context(pctx); 466 467 ctx->blend = bs; 468 ctx->dirty |= ETNA_DIRTY_BLEND; 469} 470 471static void 472etna_blend_state_delete(struct pipe_context *pctx, void *bs) 473{ 474 FREE(bs); 475} 476 477static void 478etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs) 479{ 480 struct etna_context *ctx = etna_context(pctx); 481 482 ctx->rasterizer = rs; 483 ctx->dirty |= ETNA_DIRTY_RASTERIZER; 484} 485 486static void 487etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs) 488{ 489 FREE(rs); 490} 491 492static void 493etna_zsa_state_bind(struct pipe_context *pctx, void *zs) 494{ 495 struct etna_context *ctx = etna_context(pctx); 496 497 ctx->zsa = zs; 498 ctx->dirty |= ETNA_DIRTY_ZSA; 499} 500 501static void 502etna_zsa_state_delete(struct pipe_context *pctx, void *zs) 503{ 504 FREE(zs); 505} 506 507/** Create vertex element states, which define a layout for fetching 508 * vertices for rendering. 509 */ 510static void * 511etna_vertex_elements_state_create(struct pipe_context *pctx, 512 unsigned num_elements, const struct pipe_vertex_element *elements) 513{ 514 struct etna_context *ctx = etna_context(pctx); 515 struct etna_screen *screen = ctx->screen; 516 struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state); 517 518 if (!cs) 519 return NULL; 520 521 if (num_elements > screen->specs.vertex_max_elements) { 522 BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements, 523 screen->specs.vertex_max_elements); 524 FREE(cs); 525 return NULL; 526 } 527 528 /* XXX could minimize number of consecutive stretches here by sorting, and 529 * permuting the inputs in shader or does Mesa do this already? */ 530 531 cs->num_elements = num_elements; 532 533 unsigned start_offset = 0; /* start of current consecutive stretch */ 534 bool nonconsecutive = true; /* previous value of nonconsecutive */ 535 uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */ 536 537 for (unsigned idx = 0; idx < num_elements; ++idx) { 538 unsigned buffer_idx = elements[idx].vertex_buffer_index; 539 unsigned element_size = util_format_get_blocksize(elements[idx].src_format); 540 unsigned end_offset = elements[idx].src_offset + element_size; 541 uint32_t format_type, normalize; 542 543 if (nonconsecutive) 544 start_offset = elements[idx].src_offset; 545 546 /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */ 547 assert(buffer_idx < screen->specs.stream_count); 548 549 /* maximum vertex size is 256 bytes */ 550 assert(element_size != 0 && (end_offset - start_offset) < 256); 551 552 /* check whether next element is consecutive to this one */ 553 nonconsecutive = (idx == (num_elements - 1)) || 554 elements[idx + 1].vertex_buffer_index != buffer_idx || 555 end_offset != elements[idx + 1].src_offset; 556 557 format_type = translate_vertex_format_type(elements[idx].src_format); 558 normalize = translate_vertex_format_normalize(elements[idx].src_format); 559 560 assert(format_type != ETNA_NO_MATCH); 561 assert(normalize != ETNA_NO_MATCH); 562 563 if (screen->specs.halti < 5) { 564 cs->FE_VERTEX_ELEMENT_CONFIG[idx] = 565 COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | 566 format_type | 567 VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) | 568 normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) | 569 VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) | 570 VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) | 571 VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset); 572 } else { /* HALTI5 spread vertex attrib config over two registers */ 573 cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] = 574 format_type | 575 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) | 576 normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) | 577 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) | 578 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset); 579 cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] = 580 COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) | 581 VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset); 582 } 583 584 if (util_format_is_pure_integer(elements[idx].src_format)) 585 cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1; 586 else 587 cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f); 588 589 /* instance_divisor is part of elements state but should be the same for all buffers */ 590 if (buffer_mask & 1 << buffer_idx) 591 assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor); 592 else 593 cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor; 594 595 buffer_mask |= 1 << buffer_idx; 596 cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1); 597 } 598 599 return cs; 600} 601 602static void 603etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve) 604{ 605 FREE(ve); 606} 607 608static void 609etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve) 610{ 611 struct etna_context *ctx = etna_context(pctx); 612 613 ctx->vertex_elements = ve; 614 ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS; 615} 616 617static void 618etna_set_stream_output_targets(struct pipe_context *pctx, 619 unsigned num_targets, struct pipe_stream_output_target **targets, 620 const unsigned *offsets) 621{ 622 /* stub */ 623} 624 625static bool 626etna_update_ts_config(struct etna_context *ctx) 627{ 628 uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG; 629 630 if (ctx->framebuffer_s.nr_cbufs > 0) { 631 struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]); 632 633 if(c_surf->level->ts_size && c_surf->level->ts_valid) { 634 new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR; 635 } else { 636 new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR; 637 } 638 } 639 640 if (ctx->framebuffer_s.zsbuf) { 641 struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf); 642 643 if(zs_surf->level->ts_size && zs_surf->level->ts_valid) { 644 new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR; 645 } else { 646 new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR; 647 } 648 } 649 650 if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG || 651 (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) { 652 ctx->framebuffer.TS_MEM_CONFIG = new_ts_config; 653 ctx->dirty |= ETNA_DIRTY_TS; 654 } 655 656 ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS; 657 658 return true; 659} 660 661static bool 662etna_update_clipping(struct etna_context *ctx) 663{ 664 const struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); 665 const struct pipe_framebuffer_state *fb = &ctx->framebuffer_s; 666 667 /* clip framebuffer against viewport */ 668 uint32_t scissor_left = ctx->viewport.SE_SCISSOR_LEFT; 669 uint32_t scissor_top = ctx->viewport.SE_SCISSOR_TOP; 670 uint32_t scissor_right = MIN2(fb->width, ctx->viewport.SE_SCISSOR_RIGHT); 671 uint32_t scissor_bottom = MIN2(fb->height, ctx->viewport.SE_SCISSOR_BOTTOM); 672 673 /* clip against scissor */ 674 if (rasterizer->scissor) { 675 scissor_left = MAX2(ctx->scissor.minx, scissor_left); 676 scissor_top = MAX2(ctx->scissor.miny, scissor_top); 677 scissor_right = MIN2(ctx->scissor.maxx, scissor_right); 678 scissor_bottom = MIN2(ctx->scissor.maxy, scissor_bottom); 679 } 680 681 ctx->clipping.minx = scissor_left; 682 ctx->clipping.miny = scissor_top; 683 ctx->clipping.maxx = scissor_right; 684 ctx->clipping.maxy = scissor_bottom; 685 686 ctx->dirty |= ETNA_DIRTY_SCISSOR_CLIP; 687 688 return true; 689} 690 691static bool 692etna_update_zsa(struct etna_context *ctx) 693{ 694 struct compiled_shader_state *shader_state = &ctx->shader_state; 695 struct pipe_depth_stencil_alpha_state *zsa_state = ctx->zsa; 696 struct etna_zsa_state *zsa = etna_zsa_state(zsa_state); 697 struct etna_screen *screen = ctx->screen; 698 uint32_t new_pe_depth, new_ra_depth; 699 bool late_z_write = false, early_z_write = false, 700 late_z_test = false, early_z_test = false; 701 702 if (zsa->z_write_enabled) { 703 if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) && 704 !VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) && 705 !zsa->stencil_enabled && 706 !zsa_state->alpha_enabled && 707 !shader_state->writes_z && 708 !shader_state->uses_discard) 709 early_z_write = true; 710 else 711 late_z_write = true; 712 } 713 714 if (zsa->z_test_enabled) { 715 if (!VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z) && 716 !zsa->stencil_modified && 717 !shader_state->writes_z) 718 early_z_test = true; 719 else 720 late_z_test = true; 721 } 722 723 new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ? 724 /* compare funcs have 1 to 1 mapping */ 725 zsa_state->depth_func : PIPE_FUNC_ALWAYS) | 726 COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | 727 COND(early_z_test, VIVS_PE_DEPTH_CONFIG_EARLY_Z) | 728 COND(!late_z_write && !late_z_test && !zsa->stencil_enabled, 729 VIVS_PE_DEPTH_CONFIG_DISABLE_ZS); 730 731 /* blob sets this to 0x40000031 on GC7000, seems to make no difference, 732 * but keep it in mind if depth behaves strangely. */ 733 new_ra_depth = 0x0000030 | 734 COND(early_z_test, VIVS_RA_EARLY_DEPTH_TEST_ENABLE); 735 736 if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)) { 737 if (!early_z_write) 738 new_ra_depth |= VIVS_RA_EARLY_DEPTH_WRITE_DISABLE; 739 /* The new early hierarchical test seems to only work properly if depth 740 * is also written from the early stage. 741 */ 742 if (late_z_test || (early_z_test && late_z_write)) 743 new_ra_depth |= VIVS_RA_EARLY_DEPTH_HDEPTH_DISABLE; 744 } 745 746 if (new_pe_depth != zsa->PE_DEPTH_CONFIG || 747 new_ra_depth != zsa->RA_DEPTH_CONFIG) 748 ctx->dirty |= ETNA_DIRTY_ZSA; 749 750 zsa->PE_DEPTH_CONFIG = new_pe_depth; 751 zsa->RA_DEPTH_CONFIG = new_ra_depth; 752 753 return true; 754} 755 756static bool 757etna_record_flush_resources(struct etna_context *ctx) 758{ 759 struct pipe_framebuffer_state *fb = &ctx->framebuffer_s; 760 761 if (fb->nr_cbufs > 0) { 762 struct etna_surface *surf = etna_surface(fb->cbufs[0]); 763 764 if (!etna_resource(surf->prsc)->explicit_flush) 765 _mesa_set_add(ctx->flush_resources, surf->prsc); 766 } 767 768 return true; 769} 770 771struct etna_state_updater { 772 bool (*update)(struct etna_context *ctx); 773 uint32_t dirty; 774}; 775 776static const struct etna_state_updater etna_state_updates[] = { 777 { 778 etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS, 779 }, 780 { 781 etna_shader_link, ETNA_DIRTY_SHADER, 782 }, 783 { 784 etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER 785 }, 786 { 787 etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER, 788 }, 789 { 790 etna_update_ts_config, ETNA_DIRTY_DERIVE_TS, 791 }, 792 { 793 etna_update_clipping, ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | 794 ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT, 795 }, 796 { 797 etna_update_zsa, ETNA_DIRTY_ZSA | ETNA_DIRTY_SHADER, 798 }, 799 { 800 etna_record_flush_resources, ETNA_DIRTY_FRAMEBUFFER, 801 } 802}; 803 804bool 805etna_state_update(struct etna_context *ctx) 806{ 807 for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++) 808 if (ctx->dirty & etna_state_updates[i].dirty) 809 if (!etna_state_updates[i].update(ctx)) 810 return false; 811 812 return true; 813} 814 815void 816etna_state_init(struct pipe_context *pctx) 817{ 818 pctx->set_blend_color = etna_set_blend_color; 819 pctx->set_stencil_ref = etna_set_stencil_ref; 820 pctx->set_clip_state = etna_set_clip_state; 821 pctx->set_sample_mask = etna_set_sample_mask; 822 pctx->set_constant_buffer = etna_set_constant_buffer; 823 pctx->set_framebuffer_state = etna_set_framebuffer_state; 824 pctx->set_polygon_stipple = etna_set_polygon_stipple; 825 pctx->set_scissor_states = etna_set_scissor_states; 826 pctx->set_viewport_states = etna_set_viewport_states; 827 828 pctx->set_vertex_buffers = etna_set_vertex_buffers; 829 830 pctx->bind_blend_state = etna_blend_state_bind; 831 pctx->delete_blend_state = etna_blend_state_delete; 832 833 pctx->bind_rasterizer_state = etna_rasterizer_state_bind; 834 pctx->delete_rasterizer_state = etna_rasterizer_state_delete; 835 836 pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind; 837 pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete; 838 839 pctx->create_vertex_elements_state = etna_vertex_elements_state_create; 840 pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete; 841 pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind; 842 843 pctx->set_stream_output_targets = etna_set_stream_output_targets; 844} 845