1/*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Rob Clark <robclark@freedesktop.org>
25 */
26
27#include "pipe/p_state.h"
28
29#include "freedreno_resource.h"
30
31#include "fd5_compute.h"
32#include "fd5_context.h"
33#include "fd5_emit.h"
34
35/* maybe move to fd5_program? */
36static void
37cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
38{
39   const struct ir3_info *i = &v->info;
40   enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
41   unsigned instrlen = v->instrlen;
42
43   /* if shader is more than 32*16 instructions, don't preload it.  Similar
44    * to the combined restriction of 64*16 for VS+FS
45    */
46   if (instrlen > 32)
47      instrlen = 0;
48
49   OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
50   OUT_RING(ring, 0x00000000); /* SP_SP_CNTL */
51
52   OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
53   OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS) |
54                     A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(thrsz) |
55                     0x00000880 /* XXX */);
56
57   OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
58   OUT_RING(ring,
59            A5XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
60               A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
61               A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
62               A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(v)) |
63               0x6 /* XXX */);
64
65   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
66   OUT_RING(ring, A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(0) |
67                     A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(0) |
68                     A5XX_HLSQ_CS_CONFIG_ENABLED);
69
70   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
71   OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(instrlen) |
72                     COND(v->has_ssbo, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE));
73
74   OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
75   OUT_RING(ring, A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(0) |
76                     A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(0) |
77                     A5XX_SP_CS_CONFIG_ENABLED);
78
79   assert(v->constlen % 4 == 0);
80   unsigned constlen = v->constlen / 4;
81   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
82   OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */
83   OUT_RING(ring, instrlen); /* HLSQ_CS_INSTRLEN */
84
85   OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
86   OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
87
88   OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
89   OUT_RING(ring, 0x1f00000);
90
91   uint32_t local_invocation_id, work_group_id;
92   local_invocation_id =
93      ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
94   work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
95
96   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL_0, 2);
97   OUT_RING(ring, A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
98                     A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
99                     A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
100                     A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
101   OUT_RING(ring, 0x1); /* HLSQ_CS_CNTL_1 */
102
103   if (instrlen > 0)
104      fd5_emit_shader(ring, v);
105}
106
107static void
108fd5_launch_grid(struct fd_context *ctx,
109                const struct pipe_grid_info *info) assert_dt
110{
111   struct ir3_shader_key key = {};
112   struct ir3_shader_variant *v;
113   struct fd_ringbuffer *ring = ctx->batch->draw;
114   unsigned nglobal = 0;
115
116   v =
117      ir3_shader_variant(ir3_get_shader(ctx->compute), key, false, &ctx->debug);
118   if (!v)
119      return;
120
121   if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
122      cs_program_emit(ring, v);
123
124   fd5_emit_cs_state(ctx, ring, v);
125   fd5_emit_cs_consts(v, ring, ctx, info);
126
127   u_foreach_bit (i, ctx->global_bindings.enabled_mask)
128      nglobal++;
129
130   if (nglobal > 0) {
131      /* global resources don't otherwise get an OUT_RELOC(), since
132       * the raw ptr address is emitted ir ir3_emit_cs_consts().
133       * So to make the kernel aware that these buffers are referenced
134       * by the batch, emit dummy reloc's as part of a no-op packet
135       * payload:
136       */
137      OUT_PKT7(ring, CP_NOP, 2 * nglobal);
138      u_foreach_bit (i, ctx->global_bindings.enabled_mask) {
139         struct pipe_resource *prsc = ctx->global_bindings.buf[i];
140         OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
141      }
142   }
143
144   const unsigned *local_size =
145      info->block; // v->shader->nir->info->workgroup_size;
146   const unsigned *num_groups = info->grid;
147   /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
148   const unsigned work_dim = info->work_dim ? info->work_dim : 3;
149   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_NDRANGE_0, 7);
150   OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
151                     A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
152                     A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
153                     A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
154   OUT_RING(ring,
155            A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
156   OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
157   OUT_RING(ring,
158            A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
159   OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
160   OUT_RING(ring,
161            A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
162   OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
163
164   OUT_PKT4(ring, REG_A5XX_HLSQ_CS_KERNEL_GROUP_X, 3);
165   OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_X */
166   OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
167   OUT_RING(ring, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
168
169   if (info->indirect) {
170      struct fd_resource *rsc = fd_resource(info->indirect);
171
172      fd5_emit_flush(ctx, ring);
173
174      OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
175      OUT_RING(ring, 0x00000000);
176      OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
177      OUT_RING(ring,
178               A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
179                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
180                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
181   } else {
182      OUT_PKT7(ring, CP_EXEC_CS, 4);
183      OUT_RING(ring, 0x00000000);
184      OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
185      OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
186      OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
187   }
188}
189
190void
191fd5_compute_init(struct pipe_context *pctx) disable_thread_safety_analysis
192{
193   struct fd_context *ctx = fd_context(pctx);
194   ctx->launch_grid = fd5_launch_grid;
195   pctx->create_compute_state = ir3_shader_compute_state_create;
196   pctx->delete_compute_state = ir3_shader_state_delete;
197}
198