1/*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Rob Clark <robclark@freedesktop.org>
25 */
26
27#include "pipe/p_state.h"
28#include "util/u_memory.h"
29#include "util/u_prim.h"
30#include "util/u_string.h"
31
32#include "freedreno_resource.h"
33#include "freedreno_state.h"
34
35#include "fd5_context.h"
36#include "fd5_draw.h"
37#include "fd5_emit.h"
38#include "fd5_format.h"
39#include "fd5_program.h"
40#include "fd5_zsa.h"
41
42static void
43draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
44          struct fd5_emit *emit, unsigned index_offset) assert_dt
45{
46   const struct pipe_draw_info *info = emit->info;
47   enum pc_di_primtype primtype = ctx->screen->primtypes[info->mode];
48
49   fd5_emit_state(ctx, ring, emit);
50
51   if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
52      fd5_emit_vertex_bufs(ring, emit);
53
54   OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
55   OUT_RING(ring, info->index_size ? emit->draw->index_bias
56                                   : emit->draw->start); /* VFD_INDEX_OFFSET */
57   OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
58
59   OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
60   OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61                     info->restart_index
62                                          : 0xffffffff);
63
64   fd5_emit_render_cntl(ctx, false, emit->binning_pass);
65   fd5_draw_emit(ctx->batch, ring, primtype,
66                 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info,
67                 emit->indirect, emit->draw, index_offset);
68}
69
70static bool
71fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
72             unsigned drawid_offset,
73             const struct pipe_draw_indirect_info *indirect,
74             const struct pipe_draw_start_count_bias *draw,
75             unsigned index_offset) in_dt
76{
77   struct fd5_context *fd5_ctx = fd5_context(ctx);
78   struct fd5_emit emit = {
79      .debug = &ctx->debug,
80      .vtx = &ctx->vtx,
81      .info = info,
82      .drawid_offset = drawid_offset,
83      .indirect = indirect,
84      .draw = draw,
85      .key = {
86         .vs = ctx->prog.vs,
87         .fs = ctx->prog.fs,
88         .key = {
89            .rasterflat = ctx->rasterizer->flatshade,
90            .has_per_samp = fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb,
91            .vastc_srgb = fd5_ctx->vastc_srgb,
92            .fastc_srgb = fd5_ctx->fastc_srgb,
93         },
94         .clip_plane_enable = ctx->rasterizer->clip_plane_enable,
95      },
96      .rasterflat = ctx->rasterizer->flatshade,
97      .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
98      .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
99   };
100
101   ir3_fixup_shader_state(&ctx->base, &emit.key.key);
102
103   unsigned dirty = ctx->dirty;
104
105   emit.prog = fd5_program_state(
106      ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
107
108   /* bail if compile failed: */
109   if (!emit.prog)
110      return false;
111
112   const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
113   const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
114
115   ir3_update_max_tf_vtx(ctx, vp);
116
117   /* do regular pass first: */
118
119   if (unlikely(ctx->stats_users > 0)) {
120      ctx->stats.vs_regs += ir3_shader_halfregs(vp);
121      ctx->stats.fs_regs += ir3_shader_halfregs(fp);
122   }
123
124   /* figure out whether we need to disable LRZ write for binning
125    * pass using draw pass's fp:
126    */
127   emit.no_lrz_write = fp->writes_pos || fp->no_earlyz || fp->has_kill;
128
129   emit.binning_pass = false;
130   emit.dirty = dirty;
131
132   draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
133
134   /* and now binning pass: */
135   emit.binning_pass = true;
136   emit.dirty = dirty & ~(FD_DIRTY_BLEND);
137   emit.vs = NULL; /* we changed key so need to refetch vp */
138   emit.fs = NULL;
139   draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
140
141   if (emit.streamout_mask) {
142      struct fd_ringbuffer *ring = ctx->batch->draw;
143
144      for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
145         if (emit.streamout_mask & (1 << i)) {
146            fd5_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
147         }
148      }
149   }
150
151   fd_context_all_clean(ctx);
152
153   return true;
154}
155
156static bool
157is_z32(enum pipe_format format)
158{
159   switch (format) {
160   case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
161   case PIPE_FORMAT_Z32_UNORM:
162   case PIPE_FORMAT_Z32_FLOAT:
163      return true;
164   default:
165      return false;
166   }
167}
168
169static void
170fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
171{
172   struct fd_ringbuffer *ring;
173   uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
174
175   ring = fd_batch_get_prologue(batch);
176
177   OUT_WFI5(ring);
178
179   OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
180   OUT_RING(ring, 0x10000000);
181
182   OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
183   OUT_RING(ring, 0x20fffff);
184
185   OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
186   OUT_RING(ring,
187            A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
188               A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples  > 1 ?
189                                           RECTANGULAR : BRESENHAM));
190
191   OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
192   OUT_RING(ring, 0x00000000);
193
194   OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
195   OUT_RING(ring, 0x00000181);
196
197   OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
198   OUT_RING(ring, 0x00000000);
199
200   OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
201   OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
202                     A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
203                     A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
204   OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
205   OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
206   OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
207
208   OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
209   OUT_RING(ring, 0x00000000);
210
211   OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
212   OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
213
214   OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
215   OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
216
217   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
218   OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
219
220   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
221   OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
222
223   OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
224   OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
225                     A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
226   OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
227
228   OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
229   OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
230
231   OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
232   OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | A5XX_RB_RESOLVE_CNTL_1_Y(0));
233   OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
234                     A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
235
236   fd5_emit_blit(batch, ring);
237}
238
239static bool
240fd5_clear(struct fd_context *ctx, unsigned buffers,
241          const union pipe_color_union *color, double depth,
242          unsigned stencil) assert_dt
243{
244   struct fd_ringbuffer *ring = ctx->batch->draw;
245   struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
246
247   if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
248       is_z32(pfb->zsbuf->format))
249      return false;
250
251   fd5_emit_render_cntl(ctx, true, false);
252
253   if (buffers & PIPE_CLEAR_COLOR) {
254      for (int i = 0; i < pfb->nr_cbufs; i++) {
255         union util_color uc = {0};
256
257         if (!pfb->cbufs[i])
258            continue;
259
260         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
261            continue;
262
263         enum pipe_format pfmt = pfb->cbufs[i]->format;
264
265         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
266         union pipe_color_union swapped;
267         switch (fd5_pipe2swap(pfmt)) {
268         case WZYX:
269            swapped.ui[0] = color->ui[0];
270            swapped.ui[1] = color->ui[1];
271            swapped.ui[2] = color->ui[2];
272            swapped.ui[3] = color->ui[3];
273            break;
274         case WXYZ:
275            swapped.ui[2] = color->ui[0];
276            swapped.ui[1] = color->ui[1];
277            swapped.ui[0] = color->ui[2];
278            swapped.ui[3] = color->ui[3];
279            break;
280         case ZYXW:
281            swapped.ui[3] = color->ui[0];
282            swapped.ui[0] = color->ui[1];
283            swapped.ui[1] = color->ui[2];
284            swapped.ui[2] = color->ui[3];
285            break;
286         case XYZW:
287            swapped.ui[3] = color->ui[0];
288            swapped.ui[2] = color->ui[1];
289            swapped.ui[1] = color->ui[2];
290            swapped.ui[0] = color->ui[3];
291            break;
292         }
293
294         util_pack_color_union(pfmt, &uc, &swapped);
295
296         OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
297         OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
298
299         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
300         OUT_RING(ring,
301                  A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
302
303         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
304         OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
305         OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
306         OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
307         OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
308
309         fd5_emit_blit(ctx->batch, ring);
310      }
311   }
312
313   if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
314      uint32_t clear = util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
315      uint32_t mask = 0;
316
317      if (buffers & PIPE_CLEAR_DEPTH)
318         mask |= 0x1;
319
320      if (buffers & PIPE_CLEAR_STENCIL)
321         mask |= 0x2;
322
323      OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
324      OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
325
326      OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
327      OUT_RING(ring,
328               A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(mask));
329
330      OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
331      OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
332
333      fd5_emit_blit(ctx->batch, ring);
334
335      if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
336         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
337         if (zsbuf->lrz) {
338            zsbuf->lrz_valid = true;
339            fd5_clear_lrz(ctx->batch, zsbuf, depth);
340         }
341      }
342   }
343
344   /* disable fast clear to not interfere w/ gmem->mem, etc.. */
345   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
346   OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
347
348   return true;
349}
350
351void
352fd5_draw_init(struct pipe_context *pctx) disable_thread_safety_analysis
353{
354   struct fd_context *ctx = fd_context(pctx);
355   ctx->draw_vbo = fd5_draw_vbo;
356   ctx->clear = fd5_clear;
357}
358