1/* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "pipe/p_screen.h" 29#include "util/u_inlines.h" 30#include "util/format/u_format.h" 31#include "util/u_upload_mgr.h" 32#include "util/ralloc.h" 33#include "iris_context.h" 34#include "iris_resource.h" 35#include "iris_screen.h" 36#include "intel/compiler/brw_compiler.h" 37 38static bool 39iris_is_color_fast_clear_compatible(struct iris_context *ice, 40 enum isl_format format, 41 const union isl_color_value color) 42{ 43 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 44 const struct intel_device_info *devinfo = &batch->screen->devinfo; 45 46 if (isl_format_has_int_channel(format)) { 47 perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n", 48 isl_format_get_name(format)); 49 return false; 50 } 51 52 for (int i = 0; i < 4; i++) { 53 if (!isl_format_has_color_component(format, i)) { 54 continue; 55 } 56 57 if (devinfo->ver < 9 && 58 color.f32[i] != 0.0f && color.f32[i] != 1.0f) { 59 return false; 60 } 61 } 62 63 return true; 64} 65 66static bool 67can_fast_clear_color(struct iris_context *ice, 68 struct pipe_resource *p_res, 69 unsigned level, 70 const struct pipe_box *box, 71 bool render_condition_enabled, 72 enum isl_format render_format, 73 union isl_color_value color) 74{ 75 struct iris_resource *res = (void *) p_res; 76 77 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR)) 78 return false; 79 80 if (!isl_aux_usage_has_fast_clears(res->aux.usage)) 81 return false; 82 83 /* Check for partial clear */ 84 if (box->x > 0 || box->y > 0 || 85 box->width < minify(p_res->width0, level) || 86 box->height < minify(p_res->height0, level)) { 87 return false; 88 } 89 90 /* Avoid conditional fast clears to maintain correct tracking of the aux 91 * state (see iris_resource_finish_write for more info). Note that partial 92 * fast clears (if they existed) would not pose a problem with conditional 93 * rendering. 94 */ 95 if (render_condition_enabled && 96 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { 97 return false; 98 } 99 100 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and 101 * draw calls, HW expects the clear color to be in two different color 102 * spaces after sRGB fast-clears - sRGB in the former and linear in the 103 * latter. By limiting the allowable values to 0/1, both color space 104 * requirements are satisfied. 105 */ 106 if (isl_format_is_srgb(render_format) && 107 !isl_color_value_is_zero_one(color, render_format)) { 108 return false; 109 } 110 111 /* We store clear colors as floats or uints as needed. If there are 112 * texture views in play, the formats will not properly be respected 113 * during resolves because the resolve operations only know about the 114 * resource and not the renderbuffer. 115 */ 116 if (!iris_render_formats_color_compatible(render_format, res->surf.format, 117 color, false)) { 118 return false; 119 } 120 121 if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color)) 122 return false; 123 124 /* The RENDER_SURFACE_STATE page for TGL says: 125 * 126 * For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not 127 * multiple of 64 pixels and more than 1 mip level in the view, Fast Clear 128 * is not supported when AUX_CCS_E is set in this field. 129 * 130 * The granularity of a fast-clear is one CCS element. For an 8 bpp primary 131 * surface, this maps to 32px x 4rows. Due to the surface layout parameters, 132 * if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS 133 * elements. Assuming LOD2 exists, don't fast-clear any level above LOD0 134 * to avoid stomping on other LODs. 135 */ 136 if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 && 137 res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E && p_res->width0 % 64) { 138 return false; 139 } 140 141 return true; 142} 143 144static union isl_color_value 145convert_clear_color(enum pipe_format format, 146 const union pipe_color_union *color) 147{ 148 /* pipe_color_union and isl_color_value are interchangeable */ 149 union isl_color_value override_color = *(union isl_color_value *)color; 150 151 const struct util_format_description *desc = 152 util_format_description(format); 153 unsigned colormask = util_format_colormask(desc); 154 155 if (util_format_is_intensity(format) || 156 util_format_is_luminance(format)) { 157 override_color.u32[1] = override_color.u32[0]; 158 override_color.u32[2] = override_color.u32[0]; 159 if (util_format_is_intensity(format)) 160 override_color.u32[3] = override_color.u32[0]; 161 } else { 162 for (int chan = 0; chan < 3; chan++) { 163 if (!(colormask & (1 << chan))) 164 override_color.u32[chan] = 0; 165 } 166 } 167 168 if (util_format_is_unorm(format)) { 169 for (int i = 0; i < 4; i++) 170 override_color.f32[i] = SATURATE(override_color.f32[i]); 171 } else if (util_format_is_snorm(format)) { 172 for (int i = 0; i < 4; i++) 173 override_color.f32[i] = CLAMP(override_color.f32[i], -1.0f, 1.0f); 174 } else if (util_format_is_pure_uint(format)) { 175 for (int i = 0; i < 4; i++) { 176 unsigned bits = util_format_get_component_bits( 177 format, UTIL_FORMAT_COLORSPACE_RGB, i); 178 if (bits < 32) { 179 uint32_t max = (1u << bits) - 1; 180 override_color.u32[i] = MIN2(override_color.u32[i], max); 181 } 182 } 183 } else if (util_format_is_pure_sint(format)) { 184 for (int i = 0; i < 4; i++) { 185 unsigned bits = util_format_get_component_bits( 186 format, UTIL_FORMAT_COLORSPACE_RGB, i); 187 if (bits > 0 && bits < 32) { 188 int32_t max = u_intN_max(bits); 189 int32_t min = u_intN_min(bits); 190 override_color.i32[i] = CLAMP(override_color.i32[i], min, max); 191 } 192 } 193 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT || 194 format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 195 /* these packed float formats only store unsigned values */ 196 for (int i = 0; i < 4; i++) 197 override_color.f32[i] = MAX2(override_color.f32[i], 0.0f); 198 } 199 200 if (!(colormask & 1 << 3)) { 201 if (util_format_is_pure_integer(format)) 202 override_color.u32[3] = 1; 203 else 204 override_color.f32[3] = 1.0f; 205 } 206 207 return override_color; 208} 209 210static void 211fast_clear_color(struct iris_context *ice, 212 struct iris_resource *res, 213 unsigned level, 214 const struct pipe_box *box, 215 enum isl_format format, 216 union isl_color_value color) 217{ 218 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 219 struct pipe_resource *p_res = (void *) res; 220 221 bool color_changed = res->aux.clear_color_unknown || 222 memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0; 223 224 if (color_changed) { 225 /* If we are clearing to a new clear value, we need to resolve fast 226 * clears from other levels/layers first, since we can't have different 227 * levels/layers with different fast clear colors. 228 */ 229 for (unsigned res_lvl = 0; res_lvl < res->surf.levels; res_lvl++) { 230 const unsigned level_layers = 231 iris_get_num_logical_layers(res, res_lvl); 232 for (unsigned layer = 0; layer < level_layers; layer++) { 233 if (res_lvl == level && 234 layer >= box->z && 235 layer < box->z + box->depth) { 236 /* We're going to clear this layer anyway. Leave it alone. */ 237 continue; 238 } 239 240 enum isl_aux_state aux_state = 241 iris_resource_get_aux_state(res, res_lvl, layer); 242 243 if (aux_state != ISL_AUX_STATE_CLEAR && 244 aux_state != ISL_AUX_STATE_PARTIAL_CLEAR && 245 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) { 246 /* This slice doesn't have any fast-cleared bits. */ 247 continue; 248 } 249 250 /* If we got here, then the level may have fast-clear bits that use 251 * the old clear value. We need to do a color resolve to get rid 252 * of their use of the clear color before we can change it. 253 * Fortunately, few applications ever change their clear color at 254 * different levels/layers, so this shouldn't happen often. 255 */ 256 iris_resource_prepare_access(ice, res, 257 res_lvl, 1, layer, 1, 258 res->aux.usage, 259 false); 260 if (res->aux.clear_color_unknown) { 261 perf_debug(&ice->dbg, 262 "Resolving resource (%p) level %d, layer %d: color changing from " 263 "(unknown) to (%0.2f, %0.2f, %0.2f, %0.2f)\n", 264 res, res_lvl, layer, 265 color.f32[0], color.f32[1], color.f32[2], color.f32[3]); 266 } else { 267 perf_debug(&ice->dbg, 268 "Resolving resource (%p) level %d, layer %d: color changing from " 269 "(%0.2f, %0.2f, %0.2f, %0.2f) to " 270 "(%0.2f, %0.2f, %0.2f, %0.2f)\n", 271 res, res_lvl, layer, 272 res->aux.clear_color.f32[0], 273 res->aux.clear_color.f32[1], 274 res->aux.clear_color.f32[2], 275 res->aux.clear_color.f32[3], 276 color.f32[0], color.f32[1], color.f32[2], color.f32[3]); 277 } 278 } 279 } 280 } 281 282 iris_resource_set_clear_color(ice, res, color); 283 284 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't 285 * changed, the clear is redundant and can be skipped. 286 */ 287 const enum isl_aux_state aux_state = 288 iris_resource_get_aux_state(res, level, box->z); 289 if (!color_changed && box->depth == 1 && aux_state == ISL_AUX_STATE_CLEAR) 290 return; 291 292 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": 293 * 294 * "Any transition from any value in {Clear, Render, Resolve} to a 295 * different value in {Clear, Render, Resolve} requires end of pipe 296 * synchronization." 297 * 298 * In other words, fast clear ops are not properly synchronized with 299 * other drawing. We need to use a PIPE_CONTROL to ensure that the 300 * contents of the previous draw hit the render target before we resolve 301 * and again afterwards to ensure that the resolve is complete before we 302 * do any more regular drawing. 303 */ 304 iris_emit_end_of_pipe_sync(batch, 305 "fast clear: pre-flush", 306 PIPE_CONTROL_RENDER_TARGET_FLUSH | 307 PIPE_CONTROL_TILE_CACHE_FLUSH); 308 309 iris_batch_sync_region_start(batch); 310 311 /* If we reach this point, we need to fast clear to change the state to 312 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both). 313 */ 314 enum blorp_batch_flags blorp_flags = 0; 315 blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR; 316 317 struct blorp_batch blorp_batch; 318 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 319 320 struct blorp_surf surf; 321 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf, 322 p_res, res->aux.usage, level, true); 323 324 blorp_fast_clear(&blorp_batch, &surf, res->surf.format, 325 ISL_SWIZZLE_IDENTITY, 326 level, box->z, box->depth, 327 box->x, box->y, box->x + box->width, 328 box->y + box->height); 329 blorp_batch_finish(&blorp_batch); 330 iris_emit_end_of_pipe_sync(batch, 331 "fast clear: post flush", 332 PIPE_CONTROL_RENDER_TARGET_FLUSH); 333 iris_batch_sync_region_end(batch); 334 335 iris_resource_set_aux_state(ice, res, level, box->z, 336 box->depth, ISL_AUX_STATE_CLEAR); 337 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER; 338 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS; 339 return; 340} 341 342static void 343clear_color(struct iris_context *ice, 344 struct pipe_resource *p_res, 345 unsigned level, 346 const struct pipe_box *box, 347 bool render_condition_enabled, 348 enum isl_format format, 349 struct isl_swizzle swizzle, 350 union isl_color_value color) 351{ 352 struct iris_resource *res = (void *) p_res; 353 354 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 355 const struct intel_device_info *devinfo = &batch->screen->devinfo; 356 enum blorp_batch_flags blorp_flags = 0; 357 358 if (render_condition_enabled) { 359 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 360 return; 361 362 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 363 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 364 } 365 366 if (p_res->target == PIPE_BUFFER) 367 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width); 368 369 iris_batch_maybe_flush(batch, 1500); 370 371 bool can_fast_clear = can_fast_clear_color(ice, p_res, level, box, 372 render_condition_enabled, 373 format, color); 374 if (can_fast_clear) { 375 fast_clear_color(ice, res, level, box, format, color); 376 return; 377 } 378 379 enum isl_aux_usage aux_usage = 380 iris_resource_render_aux_usage(ice, res, level, format, false); 381 382 iris_resource_prepare_render(ice, res, level, box->z, box->depth, 383 aux_usage); 384 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE); 385 386 struct blorp_surf surf; 387 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf, 388 p_res, aux_usage, level, true); 389 390 iris_batch_sync_region_start(batch); 391 392 struct blorp_batch blorp_batch; 393 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 394 395 if (!isl_format_supports_rendering(devinfo, format) && 396 isl_format_is_rgbx(format)) 397 format = isl_format_rgbx_to_rgba(format); 398 399 blorp_clear(&blorp_batch, &surf, format, swizzle, 400 level, box->z, box->depth, box->x, box->y, 401 box->x + box->width, box->y + box->height, 402 color, 0 /* color_write_disable */); 403 404 blorp_batch_finish(&blorp_batch); 405 iris_batch_sync_region_end(batch); 406 407 iris_flush_and_dirty_for_history(ice, batch, res, 408 PIPE_CONTROL_RENDER_TARGET_FLUSH, 409 "cache history: post color clear"); 410 411 iris_resource_finish_render(ice, res, level, 412 box->z, box->depth, aux_usage); 413} 414 415static bool 416can_fast_clear_depth(struct iris_context *ice, 417 struct iris_resource *res, 418 unsigned level, 419 const struct pipe_box *box, 420 bool render_condition_enabled, 421 float depth) 422{ 423 struct pipe_resource *p_res = (void *) res; 424 struct pipe_context *ctx = (void *) ice; 425 struct iris_screen *screen = (void *) ctx->screen; 426 const struct intel_device_info *devinfo = &screen->devinfo; 427 428 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR)) 429 return false; 430 431 /* Check for partial clears */ 432 if (box->x > 0 || box->y > 0 || 433 box->width < u_minify(p_res->width0, level) || 434 box->height < u_minify(p_res->height0, level)) { 435 return false; 436 } 437 438 /* Avoid conditional fast clears to maintain correct tracking of the aux 439 * state (see iris_resource_finish_write for more info). Note that partial 440 * fast clears would not pose a problem with conditional rendering. 441 */ 442 if (render_condition_enabled && 443 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { 444 return false; 445 } 446 447 if (!iris_resource_level_has_hiz(res, level)) 448 return false; 449 450 if (!blorp_can_hiz_clear_depth(devinfo, &res->surf, res->aux.usage, 451 level, box->z, box->x, box->y, 452 box->x + box->width, 453 box->y + box->height)) { 454 return false; 455 } 456 457 return true; 458} 459 460static void 461fast_clear_depth(struct iris_context *ice, 462 struct iris_resource *res, 463 unsigned level, 464 const struct pipe_box *box, 465 float depth) 466{ 467 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 468 469 bool update_clear_depth = false; 470 471 /* If we're clearing to a new clear value, then we need to resolve any clear 472 * flags out of the HiZ buffer into the real depth buffer. 473 */ 474 if (res->aux.clear_color_unknown || res->aux.clear_color.f32[0] != depth) { 475 for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) { 476 const unsigned level_layers = 477 iris_get_num_logical_layers(res, res_level); 478 for (unsigned layer = 0; layer < level_layers; layer++) { 479 if (res_level == level && 480 layer >= box->z && 481 layer < box->z + box->depth) { 482 /* We're going to clear this layer anyway. Leave it alone. */ 483 continue; 484 } 485 486 enum isl_aux_state aux_state = 487 iris_resource_get_aux_state(res, res_level, layer); 488 489 if (aux_state != ISL_AUX_STATE_CLEAR && 490 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) { 491 /* This slice doesn't have any fast-cleared bits. */ 492 continue; 493 } 494 495 /* If we got here, then the level may have fast-clear bits that 496 * use the old clear value. We need to do a depth resolve to get 497 * rid of their use of the clear value before we can change it. 498 * Fortunately, few applications ever change their depth clear 499 * value so this shouldn't happen often. 500 */ 501 iris_hiz_exec(ice, batch, res, res_level, layer, 1, 502 ISL_AUX_OP_FULL_RESOLVE, false); 503 iris_resource_set_aux_state(ice, res, res_level, layer, 1, 504 ISL_AUX_STATE_RESOLVED); 505 } 506 } 507 const union isl_color_value clear_value = { .f32 = {depth, } }; 508 iris_resource_set_clear_color(ice, res, clear_value); 509 update_clear_depth = true; 510 } 511 512 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) { 513 /* From Bspec 47010 (Depth Buffer Clear): 514 * 515 * Since the fast clear cycles to CCS are not cached in TileCache, 516 * any previous depth buffer writes to overlapping pixels must be 517 * flushed out of TileCache before a succeeding Depth Buffer Clear. 518 * This restriction only applies to Depth Buffer with write-thru 519 * enabled, since fast clears to CCS only occur for write-thru mode. 520 * 521 * There may have been a write to this depth buffer. Flush it from the 522 * tile cache just in case. 523 */ 524 iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear", 525 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 526 PIPE_CONTROL_TILE_CACHE_FLUSH); 527 } 528 529 for (unsigned l = 0; l < box->depth; l++) { 530 enum isl_aux_state aux_state = 531 iris_resource_get_aux_state(res, level, box->z + l); 532 if (update_clear_depth || aux_state != ISL_AUX_STATE_CLEAR) { 533 if (aux_state == ISL_AUX_STATE_CLEAR) { 534 perf_debug(&ice->dbg, "Performing HiZ clear just to update the " 535 "depth clear value\n"); 536 } 537 iris_hiz_exec(ice, batch, res, level, 538 box->z + l, 1, ISL_AUX_OP_FAST_CLEAR, 539 update_clear_depth); 540 } 541 } 542 543 iris_resource_set_aux_state(ice, res, level, box->z, box->depth, 544 ISL_AUX_STATE_CLEAR); 545 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER; 546 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS; 547} 548 549static void 550clear_depth_stencil(struct iris_context *ice, 551 struct pipe_resource *p_res, 552 unsigned level, 553 const struct pipe_box *box, 554 bool render_condition_enabled, 555 bool clear_depth, 556 bool clear_stencil, 557 float depth, 558 uint8_t stencil) 559{ 560 struct iris_resource *res = (void *) p_res; 561 562 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 563 enum blorp_batch_flags blorp_flags = 0; 564 565 if (render_condition_enabled) { 566 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 567 return; 568 569 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 570 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 571 } 572 573 iris_batch_maybe_flush(batch, 1500); 574 575 struct iris_resource *z_res; 576 struct iris_resource *stencil_res; 577 struct blorp_surf z_surf; 578 struct blorp_surf stencil_surf; 579 580 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res); 581 if (z_res && clear_depth && 582 can_fast_clear_depth(ice, z_res, level, box, render_condition_enabled, 583 depth)) { 584 fast_clear_depth(ice, z_res, level, box, depth); 585 iris_flush_and_dirty_for_history(ice, batch, res, 0, 586 "cache history: post fast Z clear"); 587 clear_depth = false; 588 z_res = false; 589 } 590 591 /* At this point, we might have fast cleared the depth buffer. So if there's 592 * no stencil clear pending, return early. 593 */ 594 if (!(clear_depth || (clear_stencil && stencil_res))) { 595 return; 596 } 597 598 if (clear_depth && z_res) { 599 const enum isl_aux_usage aux_usage = 600 iris_resource_render_aux_usage(ice, z_res, level, z_res->surf.format, 601 false); 602 iris_resource_prepare_render(ice, z_res, level, box->z, box->depth, 603 aux_usage); 604 iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE); 605 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &z_surf, 606 &z_res->base.b, aux_usage, level, true); 607 } 608 609 uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0; 610 if (stencil_mask) { 611 iris_resource_prepare_access(ice, stencil_res, level, 1, box->z, 612 box->depth, stencil_res->aux.usage, false); 613 iris_emit_buffer_barrier_for(batch, stencil_res->bo, 614 IRIS_DOMAIN_DEPTH_WRITE); 615 iris_blorp_surf_for_resource(&batch->screen->isl_dev, 616 &stencil_surf, &stencil_res->base.b, 617 stencil_res->aux.usage, level, true); 618 } 619 620 iris_batch_sync_region_start(batch); 621 622 struct blorp_batch blorp_batch; 623 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 624 625 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf, 626 level, box->z, box->depth, 627 box->x, box->y, 628 box->x + box->width, 629 box->y + box->height, 630 clear_depth && z_res, depth, 631 stencil_mask, stencil); 632 633 blorp_batch_finish(&blorp_batch); 634 iris_batch_sync_region_end(batch); 635 636 iris_flush_and_dirty_for_history(ice, batch, res, 0, 637 "cache history: post slow ZS clear"); 638 639 if (clear_depth && z_res) { 640 iris_resource_finish_render(ice, z_res, level, box->z, box->depth, 641 z_surf.aux_usage); 642 } 643 644 if (stencil_mask) { 645 iris_resource_finish_write(ice, stencil_res, level, box->z, box->depth, 646 stencil_res->aux.usage); 647 } 648} 649 650/** 651 * The pipe->clear() driver hook. 652 * 653 * This clears buffers attached to the current draw framebuffer. 654 */ 655static void 656iris_clear(struct pipe_context *ctx, 657 unsigned buffers, 658 const struct pipe_scissor_state *scissor_state, 659 const union pipe_color_union *p_color, 660 double depth, 661 unsigned stencil) 662{ 663 struct iris_context *ice = (void *) ctx; 664 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer; 665 666 assert(buffers != 0); 667 668 struct pipe_box box = { 669 .width = cso_fb->width, 670 .height = cso_fb->height, 671 }; 672 673 if (scissor_state) { 674 box.x = scissor_state->minx; 675 box.y = scissor_state->miny; 676 box.width = MIN2(box.width, scissor_state->maxx - scissor_state->minx); 677 box.height = MIN2(box.height, scissor_state->maxy - scissor_state->miny); 678 } 679 680 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { 681 struct pipe_surface *psurf = cso_fb->zsbuf; 682 683 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1; 684 box.z = psurf->u.tex.first_layer, 685 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true, 686 buffers & PIPE_CLEAR_DEPTH, 687 buffers & PIPE_CLEAR_STENCIL, 688 depth, stencil); 689 } 690 691 if (buffers & PIPE_CLEAR_COLOR) { 692 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) { 693 if (buffers & (PIPE_CLEAR_COLOR0 << i)) { 694 struct pipe_surface *psurf = cso_fb->cbufs[i]; 695 struct iris_surface *isurf = (void *) psurf; 696 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1, 697 box.z = psurf->u.tex.first_layer, 698 699 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 700 true, isurf->view.format, isurf->view.swizzle, 701 convert_clear_color(psurf->format, p_color)); 702 } 703 } 704 } 705} 706 707/** 708 * The pipe->clear_texture() driver hook. 709 * 710 * This clears the given texture resource. 711 */ 712static void 713iris_clear_texture(struct pipe_context *ctx, 714 struct pipe_resource *p_res, 715 unsigned level, 716 const struct pipe_box *box, 717 const void *data) 718{ 719 struct iris_context *ice = (void *) ctx; 720 struct iris_screen *screen = (void *) ctx->screen; 721 const struct intel_device_info *devinfo = &screen->devinfo; 722 723 if (util_format_is_depth_or_stencil(p_res->format)) { 724 const struct util_format_unpack_description *unpack = 725 util_format_unpack_description(p_res->format); 726 727 float depth = 0.0; 728 uint8_t stencil = 0; 729 730 if (unpack->unpack_z_float) 731 util_format_unpack_z_float(p_res->format, &depth, data, 1); 732 733 if (unpack->unpack_s_8uint) 734 util_format_unpack_s_8uint(p_res->format, &stencil, data, 1); 735 736 clear_depth_stencil(ice, p_res, level, box, true, true, true, 737 depth, stencil); 738 } else { 739 union isl_color_value color; 740 struct iris_resource *res = (void *) p_res; 741 enum isl_format format = res->surf.format; 742 743 if (!isl_format_supports_rendering(devinfo, format)) { 744 const struct isl_format_layout *fmtl = isl_format_get_layout(format); 745 // XXX: actually just get_copy_format_for_bpb from BLORP 746 // XXX: don't cut and paste this 747 switch (fmtl->bpb) { 748 case 8: format = ISL_FORMAT_R8_UINT; break; 749 case 16: format = ISL_FORMAT_R8G8_UINT; break; 750 case 24: format = ISL_FORMAT_R8G8B8_UINT; break; 751 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break; 752 case 48: format = ISL_FORMAT_R16G16B16_UINT; break; 753 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break; 754 case 96: format = ISL_FORMAT_R32G32B32_UINT; break; 755 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break; 756 default: 757 unreachable("Unknown format bpb"); 758 } 759 760 /* No aux surfaces for non-renderable surfaces */ 761 assert(res->aux.usage == ISL_AUX_USAGE_NONE); 762 } 763 764 isl_color_value_unpack(&color, format, data); 765 766 clear_color(ice, p_res, level, box, true, format, 767 ISL_SWIZZLE_IDENTITY, color); 768 } 769} 770 771/** 772 * The pipe->clear_render_target() driver hook. 773 * 774 * This clears the given render target surface. 775 */ 776static void 777iris_clear_render_target(struct pipe_context *ctx, 778 struct pipe_surface *psurf, 779 const union pipe_color_union *p_color, 780 unsigned dst_x, unsigned dst_y, 781 unsigned width, unsigned height, 782 bool render_condition_enabled) 783{ 784 struct iris_context *ice = (void *) ctx; 785 struct iris_surface *isurf = (void *) psurf; 786 struct pipe_box box = { 787 .x = dst_x, 788 .y = dst_y, 789 .z = psurf->u.tex.first_layer, 790 .width = width, 791 .height = height, 792 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 793 }; 794 795 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 796 render_condition_enabled, 797 isurf->view.format, isurf->view.swizzle, 798 convert_clear_color(psurf->format, p_color)); 799} 800 801/** 802 * The pipe->clear_depth_stencil() driver hook. 803 * 804 * This clears the given depth/stencil surface. 805 */ 806static void 807iris_clear_depth_stencil(struct pipe_context *ctx, 808 struct pipe_surface *psurf, 809 unsigned flags, 810 double depth, 811 unsigned stencil, 812 unsigned dst_x, unsigned dst_y, 813 unsigned width, unsigned height, 814 bool render_condition_enabled) 815{ 816 struct iris_context *ice = (void *) ctx; 817 struct pipe_box box = { 818 .x = dst_x, 819 .y = dst_y, 820 .z = psurf->u.tex.first_layer, 821 .width = width, 822 .height = height, 823 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 824 }; 825 826 assert(util_format_is_depth_or_stencil(psurf->texture->format)); 827 828 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, 829 render_condition_enabled, 830 flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL, 831 depth, stencil); 832} 833 834void 835iris_init_clear_functions(struct pipe_context *ctx) 836{ 837 ctx->clear = iris_clear; 838 ctx->clear_texture = iris_clear_texture; 839 ctx->clear_render_target = iris_clear_render_target; 840 ctx->clear_depth_stencil = iris_clear_depth_stencil; 841} 842