1#include "pipe/p_defines.h" 2#include "pipe/p_screen.h" 3#include "pipe/p_state.h" 4 5#include "util/u_memory.h" 6#include "util/u_inlines.h" 7#include "util/format/u_format.h" 8#include "util/format/u_format_s3tc.h" 9#include "util/u_string.h" 10 11#include "os/os_mman.h" 12#include "util/os_time.h" 13 14#include <stdio.h> 15#include <errno.h> 16#include <stdlib.h> 17 18#include <nouveau_drm.h> 19#include <xf86drm.h> 20 21#include "nouveau_winsys.h" 22#include "nouveau_screen.h" 23#include "nouveau_context.h" 24#include "nouveau_fence.h" 25#include "nouveau_mm.h" 26#include "nouveau_buffer.h" 27 28#include <compiler/glsl_types.h> 29 30/* XXX this should go away */ 31#include "frontend/drm_driver.h" 32 33/* Even though GPUs might allow addresses with more bits, some engines do not. 34 * Stick with 40 for compatibility. 35 */ 36#define NV_GENERIC_VM_LIMIT_SHIFT 39 37 38int nouveau_mesa_debug = 0; 39 40static const char * 41nouveau_screen_get_name(struct pipe_screen *pscreen) 42{ 43 struct nouveau_screen *screen = nouveau_screen(pscreen); 44 return screen->chipset_name; 45} 46 47static const char * 48nouveau_screen_get_vendor(struct pipe_screen *pscreen) 49{ 50 return "nouveau"; 51} 52 53static const char * 54nouveau_screen_get_device_vendor(struct pipe_screen *pscreen) 55{ 56 return "NVIDIA"; 57} 58 59static uint64_t 60nouveau_screen_get_timestamp(struct pipe_screen *pscreen) 61{ 62 int64_t cpu_time = os_time_get() * 1000; 63 64 /* getparam of PTIMER_TIME takes about x10 as long (several usecs) */ 65 66 return cpu_time + nouveau_screen(pscreen)->cpu_gpu_time_delta; 67} 68 69static struct disk_cache * 70nouveau_screen_get_disk_shader_cache(struct pipe_screen *pscreen) 71{ 72 return nouveau_screen(pscreen)->disk_shader_cache; 73} 74 75static void 76nouveau_screen_fence_ref(struct pipe_screen *pscreen, 77 struct pipe_fence_handle **ptr, 78 struct pipe_fence_handle *pfence) 79{ 80 nouveau_fence_ref(nouveau_fence(pfence), (struct nouveau_fence **)ptr); 81} 82 83static bool 84nouveau_screen_fence_finish(struct pipe_screen *screen, 85 struct pipe_context *ctx, 86 struct pipe_fence_handle *pfence, 87 uint64_t timeout) 88{ 89 if (!timeout) 90 return nouveau_fence_signalled(nouveau_fence(pfence)); 91 92 return nouveau_fence_wait(nouveau_fence(pfence), NULL); 93} 94 95 96struct nouveau_bo * 97nouveau_screen_bo_from_handle(struct pipe_screen *pscreen, 98 struct winsys_handle *whandle, 99 unsigned *out_stride) 100{ 101 struct nouveau_device *dev = nouveau_screen(pscreen)->device; 102 struct nouveau_bo *bo = 0; 103 int ret; 104 105 if (whandle->offset != 0) { 106 debug_printf("%s: attempt to import unsupported winsys offset %d\n", 107 __FUNCTION__, whandle->offset); 108 return NULL; 109 } 110 111 if (whandle->type != WINSYS_HANDLE_TYPE_SHARED && 112 whandle->type != WINSYS_HANDLE_TYPE_FD) { 113 debug_printf("%s: attempt to import unsupported handle type %d\n", 114 __FUNCTION__, whandle->type); 115 return NULL; 116 } 117 118 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) 119 ret = nouveau_bo_name_ref(dev, whandle->handle, &bo); 120 else 121 ret = nouveau_bo_prime_handle_ref(dev, whandle->handle, &bo); 122 123 if (ret) { 124 debug_printf("%s: ref name 0x%08x failed with %d\n", 125 __FUNCTION__, whandle->handle, ret); 126 return NULL; 127 } 128 129 *out_stride = whandle->stride; 130 return bo; 131} 132 133 134bool 135nouveau_screen_bo_get_handle(struct pipe_screen *pscreen, 136 struct nouveau_bo *bo, 137 unsigned stride, 138 struct winsys_handle *whandle) 139{ 140 whandle->stride = stride; 141 142 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 143 return nouveau_bo_name_get(bo, &whandle->handle) == 0; 144 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) { 145 whandle->handle = bo->handle; 146 return true; 147 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 148 return nouveau_bo_set_prime(bo, (int *)&whandle->handle) == 0; 149 } else { 150 return false; 151 } 152} 153 154static void 155nouveau_disk_cache_create(struct nouveau_screen *screen) 156{ 157 struct mesa_sha1 ctx; 158 unsigned char sha1[20]; 159 char cache_id[20 * 2 + 1]; 160 uint64_t driver_flags = 0; 161 162 _mesa_sha1_init(&ctx); 163 if (!disk_cache_get_function_identifier(nouveau_disk_cache_create, 164 &ctx)) 165 return; 166 167 _mesa_sha1_final(&ctx, sha1); 168 disk_cache_format_hex_id(cache_id, sha1, 20 * 2); 169 170 if (screen->prefer_nir) 171 driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR; 172 else 173 driver_flags |= NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI; 174 175 screen->disk_shader_cache = 176 disk_cache_create(nouveau_screen_get_name(&screen->base), 177 cache_id, driver_flags); 178} 179 180static void* 181reserve_vma(uintptr_t start, uint64_t reserved_size) 182{ 183 void *reserved = os_mmap((void*)start, reserved_size, PROT_NONE, 184 MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); 185 if (reserved == MAP_FAILED) 186 return NULL; 187 return reserved; 188} 189 190int 191nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev) 192{ 193 struct pipe_screen *pscreen = &screen->base; 194 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; 195 struct nvc0_fifo nvc0_data = { }; 196 uint64_t time; 197 int size, ret; 198 void *data; 199 union nouveau_bo_config mm_config; 200 201 char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG"); 202 if (nv_dbg) 203 nouveau_mesa_debug = atoi(nv_dbg); 204 205 if (dev->chipset < 0x140) 206 screen->prefer_nir = debug_get_bool_option("NV50_PROG_USE_NIR", false); 207 else 208 screen->prefer_nir = true; 209 210 screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false); 211 if (screen->force_enable_cl) 212 glsl_type_singleton_init_or_ref(); 213 214 /* These must be set before any failure is possible, as the cleanup 215 * paths assume they're responsible for deleting them. 216 */ 217 screen->drm = nouveau_drm(&dev->object); 218 screen->device = dev; 219 220 /* 221 * this is initialized to 1 in nouveau_drm_screen_create after screen 222 * is fully constructed and added to the global screen list. 223 */ 224 screen->refcount = -1; 225 226 if (dev->chipset < 0xc0) { 227 data = &nv04_data; 228 size = sizeof(nv04_data); 229 } else { 230 data = &nvc0_data; 231 size = sizeof(nvc0_data); 232 } 233 234 bool enable_svm = debug_get_bool_option("NOUVEAU_SVM", false); 235 screen->has_svm = false; 236 /* we only care about HMM with OpenCL enabled */ 237 if (dev->chipset > 0x130 && screen->force_enable_cl && enable_svm) { 238 /* Before being able to enable SVM we need to carve out some memory for 239 * driver bo allocations. Let's just base the size on the available VRAM. 240 * 241 * 40 bit is the biggest we care about and for 32 bit systems we don't 242 * want to allocate all of the available memory either. 243 * 244 * Also we align the size we want to reserve to the next POT to make use 245 * of hugepages. 246 */ 247 const int vram_shift = util_logbase2_ceil64(dev->vram_size); 248 const int limit_bit = 249 MIN2(sizeof(void*) * 8 - 1, NV_GENERIC_VM_LIMIT_SHIFT); 250 screen->svm_cutout_size = 251 BITFIELD64_BIT(MIN2(sizeof(void*) == 4 ? 26 : NV_GENERIC_VM_LIMIT_SHIFT, vram_shift)); 252 253 size_t start = screen->svm_cutout_size; 254 do { 255 screen->svm_cutout = reserve_vma(start, screen->svm_cutout_size); 256 if (!screen->svm_cutout) { 257 start += screen->svm_cutout_size; 258 continue; 259 } 260 261 struct drm_nouveau_svm_init svm_args = { 262 .unmanaged_addr = (uintptr_t)screen->svm_cutout, 263 .unmanaged_size = screen->svm_cutout_size, 264 }; 265 266 ret = drmCommandWrite(screen->drm->fd, DRM_NOUVEAU_SVM_INIT, 267 &svm_args, sizeof(svm_args)); 268 screen->has_svm = !ret; 269 if (!screen->has_svm) 270 os_munmap(screen->svm_cutout, screen->svm_cutout_size); 271 break; 272 } while ((start + screen->svm_cutout_size) < BITFIELD64_MASK(limit_bit)); 273 } 274 275 switch (dev->chipset) { 276 case 0x0ea: /* TK1, GK20A */ 277 case 0x12b: /* TX1, GM20B */ 278 case 0x13b: /* TX2, GP10B */ 279 screen->tegra_sector_layout = true; 280 break; 281 default: 282 /* Xavier's GPU and everything else */ 283 screen->tegra_sector_layout = false; 284 break; 285 } 286 287 /* 288 * Set default VRAM domain if not overridden 289 */ 290 if (!screen->vram_domain) { 291 if (dev->vram_size > 0) 292 screen->vram_domain = NOUVEAU_BO_VRAM; 293 else 294 screen->vram_domain = NOUVEAU_BO_GART; 295 } 296 297 ret = nouveau_object_new(&dev->object, 0, NOUVEAU_FIFO_CHANNEL_CLASS, 298 data, size, &screen->channel); 299 if (ret) 300 goto err; 301 302 ret = nouveau_client_new(screen->device, &screen->client); 303 if (ret) 304 goto err; 305 ret = nouveau_pushbuf_new(screen->client, screen->channel, 306 4, 512 * 1024, 1, 307 &screen->pushbuf); 308 if (ret) 309 goto err; 310 311 /* getting CPU time first appears to be more accurate */ 312 screen->cpu_gpu_time_delta = os_time_get(); 313 314 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_PTIMER_TIME, &time); 315 if (!ret) 316 screen->cpu_gpu_time_delta = time - screen->cpu_gpu_time_delta * 1000; 317 318 snprintf(screen->chipset_name, sizeof(screen->chipset_name), "NV%02X", dev->chipset); 319 pscreen->get_name = nouveau_screen_get_name; 320 pscreen->get_vendor = nouveau_screen_get_vendor; 321 pscreen->get_device_vendor = nouveau_screen_get_device_vendor; 322 pscreen->get_disk_shader_cache = nouveau_screen_get_disk_shader_cache; 323 324 pscreen->get_timestamp = nouveau_screen_get_timestamp; 325 326 pscreen->fence_reference = nouveau_screen_fence_ref; 327 pscreen->fence_finish = nouveau_screen_fence_finish; 328 329 nouveau_disk_cache_create(screen); 330 331 screen->transfer_pushbuf_threshold = 192; 332 screen->lowmem_bindings = PIPE_BIND_GLOBAL; /* gallium limit */ 333 screen->vidmem_bindings = 334 PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL | 335 PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | 336 PIPE_BIND_CURSOR | 337 PIPE_BIND_SAMPLER_VIEW | 338 PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | 339 PIPE_BIND_COMPUTE_RESOURCE | 340 PIPE_BIND_GLOBAL; 341 screen->sysmem_bindings = 342 PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT | 343 PIPE_BIND_COMMAND_ARGS_BUFFER; 344 345 memset(&mm_config, 0, sizeof(mm_config)); 346 347 screen->mm_GART = nouveau_mm_create(dev, 348 NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 349 &mm_config); 350 screen->mm_VRAM = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); 351 return 0; 352 353err: 354 if (screen->svm_cutout) 355 os_munmap(screen->svm_cutout, screen->svm_cutout_size); 356 return ret; 357} 358 359void 360nouveau_screen_fini(struct nouveau_screen *screen) 361{ 362 int fd = screen->drm->fd; 363 364 if (screen->force_enable_cl) 365 glsl_type_singleton_decref(); 366 if (screen->has_svm) 367 os_munmap(screen->svm_cutout, screen->svm_cutout_size); 368 369 nouveau_mm_destroy(screen->mm_GART); 370 nouveau_mm_destroy(screen->mm_VRAM); 371 372 nouveau_pushbuf_del(&screen->pushbuf); 373 374 nouveau_client_del(&screen->client); 375 nouveau_object_del(&screen->channel); 376 377 nouveau_device_del(&screen->device); 378 nouveau_drm_del(&screen->drm); 379 close(fd); 380 381 disk_cache_destroy(screen->disk_shader_cache); 382} 383 384static void 385nouveau_set_debug_callback(struct pipe_context *pipe, 386 const struct pipe_debug_callback *cb) 387{ 388 struct nouveau_context *context = nouveau_context(pipe); 389 390 if (cb) 391 context->debug = *cb; 392 else 393 memset(&context->debug, 0, sizeof(context->debug)); 394} 395 396void 397nouveau_context_init(struct nouveau_context *context) 398{ 399 context->pipe.set_debug_callback = nouveau_set_debug_callback; 400} 401