1/* -*- mesa-c++  -*-
2 *
3 * Copyright (c) 2019 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include "sfn_emitinstruction.h"
28
29#include "sfn_shader_base.h"
30
31namespace r600 {
32
33EmitInstruction::EmitInstruction(ShaderFromNirProcessor& processor):
34   m_proc(processor)
35{
36
37}
38
39EmitInstruction::~EmitInstruction()
40{
41}
42
43bool EmitInstruction::emit(nir_instr* instr)
44{
45   return do_emit(instr);
46}
47
48PValue EmitInstruction::from_nir(const nir_src& v, unsigned component, unsigned swizzled)
49{
50   return m_proc.from_nir(v, component, swizzled);
51}
52
53PValue EmitInstruction::from_nir(const nir_alu_src& v, unsigned component)
54{
55   return m_proc.from_nir(v, component);
56}
57
58PValue EmitInstruction::from_nir(const nir_tex_src& v, unsigned component)
59{
60   return m_proc.from_nir(v, component);
61}
62
63PValue EmitInstruction::from_nir(const nir_alu_dest& v, unsigned component)
64{
65   return m_proc.from_nir(v, component);
66}
67
68PValue EmitInstruction::from_nir(const nir_dest& v, unsigned component)
69{
70   return m_proc.from_nir(v, component);
71}
72
73PValue EmitInstruction::from_nir(const nir_src& v, unsigned component)
74{
75   return m_proc.from_nir(v, component);
76}
77
78void EmitInstruction::emit_instruction(Instruction *ir)
79{
80   return m_proc.emit_instruction(ir);
81}
82
83void EmitInstruction::emit_instruction(AluInstruction *ir)
84{
85   return m_proc.emit_instruction(ir);
86}
87
88bool EmitInstruction::emit_instruction(EAluOp opcode, PValue dest,
89                                       std::vector<PValue> src0,
90                                       const std::set<AluModifiers>& m_flags)
91{
92   return m_proc.emit_instruction(opcode, dest,src0, m_flags);
93}
94
95const nir_variable *
96EmitInstruction::get_deref_location(const nir_src& v) const
97{
98   return m_proc.get_deref_location(v);
99}
100
101PValue EmitInstruction::from_nir_with_fetch_constant(const nir_src& src, unsigned component, int channel)
102{
103   return m_proc.from_nir_with_fetch_constant(src, component, channel);
104}
105
106GPRVector EmitInstruction::vec_from_nir_with_fetch_constant(const nir_src& src, unsigned mask,
107                                                            const GPRVector::Swizzle& swizzle, bool match)
108{
109   return m_proc.vec_from_nir_with_fetch_constant(src, mask, swizzle, match);
110}
111
112PGPRValue EmitInstruction::get_temp_register(int channel)
113{
114   return m_proc.get_temp_register(channel);
115}
116
117GPRVector EmitInstruction::get_temp_vec4(const GPRVector::Swizzle& swizzle)
118{
119   return m_proc.get_temp_vec4(swizzle);
120}
121
122PValue EmitInstruction::create_register_from_nir_src(const nir_src& src, unsigned swizzle)
123{
124   return m_proc.create_register_from_nir_src(src, swizzle);
125}
126
127enum chip_class EmitInstruction::get_chip_class(void) const
128{
129   return m_proc.get_chip_class();
130}
131
132PValue EmitInstruction::literal(uint32_t value)
133{
134   return m_proc.literal(value);
135}
136
137GPRVector EmitInstruction::vec_from_nir(const nir_dest& dst, int num_components)
138{
139   return m_proc.vec_from_nir(dst, num_components);
140}
141
142bool EmitInstruction::inject_register(unsigned sel, unsigned swizzle,
143                                      const PValue& reg, bool map)
144{
145   return m_proc.inject_register(sel, swizzle, reg, map);
146}
147
148int EmitInstruction::remap_atomic_base(int base)
149{
150	return m_proc.remap_atomic_base(base);
151}
152
153void EmitInstruction::set_has_txs_cube_array_comp()
154{
155   m_proc.sh_info().has_txq_cube_array_z_comp = 1;
156}
157
158const std::set<AluModifiers> EmitInstruction::empty = {};
159const std::set<AluModifiers> EmitInstruction::write = {alu_write};
160const std::set<AluModifiers> EmitInstruction::last_write = {alu_write, alu_last_instr};
161const std::set<AluModifiers> EmitInstruction::last = {alu_last_instr};
162
163}
164
165