1/* -*- mesa-c++  -*-
2 *
3 * Copyright (c) 2018 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include "sfn_shader_compute.h"
28#include "sfn_instruction_fetch.h"
29
30namespace r600 {
31
32ComputeShaderFromNir::ComputeShaderFromNir(r600_pipe_shader *sh,
33                                           r600_pipe_shader_selector& sel,
34                                           UNUSED const r600_shader_key& key,
35                                           enum chip_class chip_class):
36     ShaderFromNirProcessor (PIPE_SHADER_COMPUTE, sel, sh->shader,
37                             sh->scratch_space_needed, chip_class, 0),
38     m_reserved_registers(0)
39{
40}
41
42bool ComputeShaderFromNir::scan_sysvalue_access(UNUSED nir_instr *instr)
43{
44   return true;
45}
46bool ComputeShaderFromNir::do_allocate_reserved_registers()
47{
48   int thread_id_sel = m_reserved_registers++;
49   int wg_id_sel = m_reserved_registers++;
50
51   for (int i = 0; i < 3; ++i) {
52      auto tmp = new GPRValue(thread_id_sel, i);
53      tmp->set_as_input();
54      tmp->set_keep_alive();
55      m_local_invocation_id[i] = PValue(tmp);
56      inject_register(tmp->sel(), i, m_local_invocation_id[i], false);
57
58      tmp = new GPRValue(wg_id_sel, i);
59      tmp->set_as_input();
60      tmp->set_keep_alive();
61      m_workgroup_id[i] = PValue(tmp);
62      inject_register(tmp->sel(), i, m_workgroup_id[i], false);
63   }
64   return true;
65}
66
67bool ComputeShaderFromNir::emit_intrinsic_instruction_override(nir_intrinsic_instr* instr)
68{
69   switch (instr->intrinsic) {
70   case nir_intrinsic_load_local_invocation_id:
71      return emit_load_3vec(instr, m_local_invocation_id);
72   case nir_intrinsic_load_workgroup_id:
73      return emit_load_3vec(instr, m_workgroup_id);
74   case nir_intrinsic_load_num_workgroups:
75      return emit_load_num_workgroups(instr);
76   default:
77      return false;
78   }
79}
80
81bool ComputeShaderFromNir::emit_load_3vec(nir_intrinsic_instr* instr,
82                                          const std::array<PValue,3>& src)
83{
84   for (int i = 0; i < 3; ++i)
85      load_preloaded_value(instr->dest, i, src[i], i == 2);
86   return true;
87}
88
89bool ComputeShaderFromNir::emit_load_num_workgroups(nir_intrinsic_instr* instr)
90{
91   PValue a_zero = get_temp_register(1);
92   emit_instruction(new AluInstruction(op1_mov, a_zero, Value::zero, EmitInstruction::last_write));
93   GPRVector dest;
94   for (int i = 0; i < 3; ++i)
95      dest.set_reg_i(i, from_nir(instr->dest, i));
96   dest.set_reg_i(3, from_nir(instr->dest, 7));
97
98   auto ir = new FetchInstruction(vc_fetch, no_index_offset,
99                                  fmt_32_32_32_32, vtx_nf_int, vtx_es_none, a_zero, dest, 16,
100                                  false, 16, R600_BUFFER_INFO_CONST_BUFFER, 0,
101                                  bim_none, false, false, 0, 0, 0, PValue(), {0,1,2,7});
102   ir->set_flag(vtx_srf_mode);
103   emit_instruction(ir);
104   return true;
105}
106
107void ComputeShaderFromNir::do_finalize()
108{
109
110}
111
112}
113