1/************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifndef _RADEON_VCN_ENC_H 29#define _RADEON_VCN_ENC_H 30 31#include "radeon_video.h" 32 33#define RENCODE_IB_OP_INITIALIZE 0x01000001 34#define RENCODE_IB_OP_CLOSE_SESSION 0x01000002 35#define RENCODE_IB_OP_ENCODE 0x01000003 36#define RENCODE_IB_OP_INIT_RC 0x01000004 37#define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005 38#define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006 39#define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007 40#define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008 41 42#define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000 43#define RENCODE_IF_MAJOR_VERSION_SHIFT 16 44#define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF 45#define RENCODE_IF_MINOR_VERSION_SHIFT 0 46 47#define RENCODE_ENGINE_TYPE_ENCODE 1 48 49#define RENCODE_ENCODE_STANDARD_HEVC 0 50#define RENCODE_ENCODE_STANDARD_H264 1 51 52#define RENCODE_PREENCODE_MODE_NONE 0x00000000 53#define RENCODE_PREENCODE_MODE_1X 0x00000001 54#define RENCODE_PREENCODE_MODE_2X 0x00000002 55#define RENCODE_PREENCODE_MODE_4X 0x00000004 56 57#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000 58#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 59 60#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000 61#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 62 63#define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000 64#define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001 65#define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002 66#define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003 67 68#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000 69#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001 70#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002 71#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003 72#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004 73#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005 74#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI 0x00000006 75 76#define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16 77#define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16 78 79#define RENCODE_HEADER_INSTRUCTION_END 0x00000000 80#define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001 81 82#define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000 83#define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001 84#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002 85#define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003 86#define RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE 0x00010004 87#define RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE 0x00010005 88 89#define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000 90#define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001 91 92#define RENCODE_PICTURE_TYPE_B 0 93#define RENCODE_PICTURE_TYPE_P 1 94#define RENCODE_PICTURE_TYPE_I 2 95#define RENCODE_PICTURE_TYPE_P_SKIP 3 96 97#define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0 98#define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1 99#define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5 100#define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9 101 102#define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0 103#define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1 104#define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2 105 106#define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0 107#define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1 108#define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2 109 110#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0 111#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1 112#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2 113 114#define RENCODE_INTRA_REFRESH_MODE_NONE 0 115#define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1 116#define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2 117 118#define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34 119 120#define RENCODE_REC_SWIZZLE_MODE_LINEAR 0 121#define RENCODE_REC_SWIZZLE_MODE_256B_S 1 122 123#define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 124#define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 125 126#define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0 127#define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1 128 129#define RENCODE_MAX_NUM_TEMPORAL_LAYERS 4 130 131#define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 132#define RADEON_ENC_BEGIN(cmd) \ 133 { \ 134 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 135 RADEON_ENC_CS(cmd) 136#define RADEON_ENC_READ(buf, domain, off) \ 137 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 138#define RADEON_ENC_WRITE(buf, domain, off) \ 139 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 140#define RADEON_ENC_READWRITE(buf, domain, off) \ 141 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 142#define RADEON_ENC_END() \ 143 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 144 enc->total_task_size += *begin; \ 145 } 146 147typedef struct rvcn_enc_session_info_s { 148 uint32_t interface_version; 149 uint32_t sw_context_address_hi; 150 uint32_t sw_context_address_lo; 151} rvcn_enc_session_info_t; 152 153typedef struct rvcn_enc_task_info_s { 154 uint32_t total_size_of_all_packages; 155 uint32_t task_id; 156 uint32_t allowed_max_num_feedbacks; 157} rvcn_enc_task_info_t; 158 159typedef struct rvcn_enc_session_init_s { 160 uint32_t encode_standard; 161 uint32_t aligned_picture_width; 162 uint32_t aligned_picture_height; 163 uint32_t padding_width; 164 uint32_t padding_height; 165 uint32_t pre_encode_mode; 166 uint32_t pre_encode_chroma_enabled; 167} rvcn_enc_session_init_t; 168 169typedef struct rvcn_enc_layer_control_s { 170 uint32_t max_num_temporal_layers; 171 uint32_t num_temporal_layers; 172} rvcn_enc_layer_control_t; 173 174typedef struct rvcn_enc_layer_select_s { 175 uint32_t temporal_layer_index; 176} rvcn_enc_layer_select_t; 177 178typedef struct rvcn_enc_h264_slice_control_s { 179 uint32_t slice_control_mode; 180 union { 181 uint32_t num_mbs_per_slice; 182 uint32_t num_bits_per_slice; 183 }; 184} rvcn_enc_h264_slice_control_t; 185 186typedef struct rvcn_enc_hevc_slice_control_s { 187 uint32_t slice_control_mode; 188 union { 189 struct { 190 uint32_t num_ctbs_per_slice; 191 uint32_t num_ctbs_per_slice_segment; 192 } fixed_ctbs_per_slice; 193 194 struct { 195 uint32_t num_bits_per_slice; 196 uint32_t num_bits_per_slice_segment; 197 } fixed_bits_per_slice; 198 }; 199} rvcn_enc_hevc_slice_control_t; 200 201typedef struct rvcn_enc_h264_spec_misc_s { 202 uint32_t constrained_intra_pred_flag; 203 uint32_t cabac_enable; 204 uint32_t cabac_init_idc; 205 uint32_t half_pel_enabled; 206 uint32_t quarter_pel_enabled; 207 uint32_t profile_idc; 208 uint32_t level_idc; 209 uint32_t b_picture_enabled; 210 uint32_t weighted_bipred_idc; 211} rvcn_enc_h264_spec_misc_t; 212 213typedef struct rvcn_enc_hevc_spec_misc_s { 214 uint32_t log2_min_luma_coding_block_size_minus3; 215 uint32_t amp_disabled; 216 uint32_t strong_intra_smoothing_enabled; 217 uint32_t constrained_intra_pred_flag; 218 uint32_t cabac_init_flag; 219 uint32_t half_pel_enabled; 220 uint32_t quarter_pel_enabled; 221} rvcn_enc_hevc_spec_misc_t; 222 223typedef struct rvcn_enc_rate_ctl_session_init_s { 224 uint32_t rate_control_method; 225 uint32_t vbv_buffer_level; 226} rvcn_enc_rate_ctl_session_init_t; 227 228typedef struct rvcn_enc_rate_ctl_layer_init_s { 229 uint32_t target_bit_rate; 230 uint32_t peak_bit_rate; 231 uint32_t frame_rate_num; 232 uint32_t frame_rate_den; 233 uint32_t vbv_buffer_size; 234 uint32_t avg_target_bits_per_picture; 235 uint32_t peak_bits_per_picture_integer; 236 uint32_t peak_bits_per_picture_fractional; 237} rvcn_enc_rate_ctl_layer_init_t; 238 239typedef struct rvcn_enc_rate_ctl_per_picture_s { 240 uint32_t qp; 241 uint32_t min_qp_app; 242 uint32_t max_qp_app; 243 uint32_t max_au_size; 244 uint32_t enabled_filler_data; 245 uint32_t skip_frame_enable; 246 uint32_t enforce_hrd; 247} rvcn_enc_rate_ctl_per_picture_t; 248 249typedef struct rvcn_enc_quality_params_s { 250 uint32_t vbaq_mode; 251 uint32_t scene_change_sensitivity; 252 uint32_t scene_change_min_idr_interval; 253 uint32_t two_pass_search_center_map_mode; 254} rvcn_enc_quality_params_t; 255 256typedef struct rvcn_enc_direct_output_nalu_s { 257 uint32_t type; 258 uint32_t size; 259 uint32_t data[1]; 260} rvcn_enc_direct_output_nalu_t; 261 262typedef struct rvcn_enc_slice_header_s { 263 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS]; 264 struct { 265 uint32_t instruction; 266 uint32_t num_bits; 267 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS]; 268} rvcn_enc_slice_header_t; 269 270typedef struct rvcn_enc_h264_reference_picture_info_s { 271 unsigned int pic_type; 272 unsigned int is_long_term; 273 unsigned int picture_structure; 274 unsigned int pic_order_cnt; 275} rvcn_enc_h264_reference_picture_info_t; 276 277typedef struct rvcn_enc_encode_params_s { 278 uint32_t pic_type; 279 uint32_t allowed_max_bitstream_size; 280 uint32_t input_picture_luma_address_hi; 281 uint32_t input_picture_luma_address_lo; 282 uint32_t input_picture_chroma_address_hi; 283 uint32_t input_picture_chroma_address_lo; 284 uint32_t input_pic_luma_pitch; 285 uint32_t input_pic_chroma_pitch; 286 uint8_t input_pic_swizzle_mode; 287 uint32_t reference_picture_index; 288 uint32_t reconstructed_picture_index; 289} rvcn_enc_encode_params_t; 290 291typedef struct rvcn_enc_h264_encode_params_s { 292 uint32_t input_picture_structure; 293 uint32_t input_pic_order_cnt; 294 uint32_t interlaced_mode; 295 uint32_t reference_picture_structure; 296 uint32_t reference_picture1_index; 297 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture0; 298 uint32_t l0_reference_picture1_index; 299 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture1; 300 uint32_t l1_reference_picture0_index; 301 rvcn_enc_h264_reference_picture_info_t picture_info_l1_reference_picture0; 302} rvcn_enc_h264_encode_params_t; 303 304typedef struct rvcn_enc_h264_deblocking_filter_s { 305 uint32_t disable_deblocking_filter_idc; 306 int32_t alpha_c0_offset_div2; 307 int32_t beta_offset_div2; 308 int32_t cb_qp_offset; 309 int32_t cr_qp_offset; 310} rvcn_enc_h264_deblocking_filter_t; 311 312typedef struct rvcn_enc_hevc_deblocking_filter_s { 313 uint32_t loop_filter_across_slices_enabled; 314 int32_t deblocking_filter_disabled; 315 int32_t beta_offset_div2; 316 int32_t tc_offset_div2; 317 int32_t cb_qp_offset; 318 int32_t cr_qp_offset; 319} rvcn_enc_hevc_deblocking_filter_t; 320 321typedef struct rvcn_enc_intra_refresh_s { 322 uint32_t intra_refresh_mode; 323 uint32_t offset; 324 uint32_t region_size; 325} rvcn_enc_intra_refresh_t; 326 327typedef struct rvcn_enc_reconstructed_picture_s { 328 uint32_t luma_offset; 329 uint32_t chroma_offset; 330} rvcn_enc_reconstructed_picture_t; 331 332typedef struct rvcn_enc_pre_encode_input_picture_s { 333 union { 334 struct { 335 uint32_t luma_offset; 336 uint32_t chroma_offset; 337 } yuv; 338 struct { 339 uint32_t red_offset; 340 uint32_t green_offset; 341 uint32_t blue_offset; 342 } rgb; 343 }; 344} rvcn_enc_pre_encode_input_picture_t; 345 346typedef struct rvcn_enc_encode_context_buffer_s { 347 uint32_t encode_context_address_hi; 348 uint32_t encode_context_address_lo; 349 uint32_t swizzle_mode; 350 uint32_t rec_luma_pitch; 351 uint32_t rec_chroma_pitch; 352 uint32_t num_reconstructed_pictures; 353 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 354 uint32_t pre_encode_picture_luma_pitch; 355 uint32_t pre_encode_picture_chroma_pitch; 356 rvcn_enc_reconstructed_picture_t 357 pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 358 rvcn_enc_reconstructed_picture_t pre_encode_input_picture; 359} rvcn_enc_encode_context_buffer_t; 360 361typedef struct rvcn_enc_video_bitstream_buffer_s { 362 uint32_t mode; 363 uint32_t video_bitstream_buffer_address_hi; 364 uint32_t video_bitstream_buffer_address_lo; 365 uint32_t video_bitstream_buffer_size; 366 uint32_t video_bitstream_data_offset; 367} rvcn_enc_video_bitstream_buffer_t; 368 369typedef struct rvcn_enc_feedback_buffer_s { 370 uint32_t mode; 371 uint32_t feedback_buffer_address_hi; 372 uint32_t feedback_buffer_address_lo; 373 uint32_t feedback_buffer_size; 374 uint32_t feedback_data_size; 375} rvcn_enc_feedback_buffer_t; 376 377typedef struct rvcn_enc_cmd_s { 378 uint32_t session_info; 379 uint32_t task_info; 380 uint32_t session_init; 381 uint32_t layer_control; 382 uint32_t layer_select; 383 uint32_t rc_session_init; 384 uint32_t rc_layer_init; 385 uint32_t rc_per_pic; 386 uint32_t quality_params; 387 uint32_t slice_header; 388 uint32_t enc_params; 389 uint32_t intra_refresh; 390 uint32_t ctx; 391 uint32_t bitstream; 392 uint32_t feedback; 393 uint32_t nalu; 394 uint32_t slice_control_hevc; 395 uint32_t spec_misc_hevc; 396 uint32_t enc_params_hevc; 397 uint32_t deblocking_filter_hevc; 398 uint32_t slice_control_h264; 399 uint32_t spec_misc_h264; 400 uint32_t enc_params_h264; 401 uint32_t deblocking_filter_h264; 402 uint32_t input_format; 403 uint32_t output_format; 404} rvcn_enc_cmd_t; 405 406typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle, 407 struct radeon_surf **surface); 408 409struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 410 const struct pipe_video_codec *templat, 411 struct radeon_winsys *ws, 412 radeon_enc_get_buffer get_buffer); 413 414struct radeon_enc_pic { 415 enum pipe_h2645_enc_picture_type picture_type; 416 417 unsigned frame_num; 418 unsigned pic_order_cnt; 419 unsigned pic_order_cnt_type; 420 unsigned ref_idx_l0; 421 unsigned ref_idx_l1; 422 unsigned crop_left; 423 unsigned crop_right; 424 unsigned crop_top; 425 unsigned crop_bottom; 426 unsigned general_tier_flag; 427 unsigned general_profile_idc; 428 unsigned general_level_idc; 429 unsigned max_poc; 430 unsigned log2_max_poc; 431 unsigned chroma_format_idc; 432 unsigned pic_width_in_luma_samples; 433 unsigned pic_height_in_luma_samples; 434 unsigned log2_diff_max_min_luma_coding_block_size; 435 unsigned log2_min_transform_block_size_minus2; 436 unsigned log2_diff_max_min_transform_block_size; 437 unsigned max_transform_hierarchy_depth_inter; 438 unsigned max_transform_hierarchy_depth_intra; 439 unsigned log2_parallel_merge_level_minus2; 440 unsigned bit_depth_luma_minus8; 441 unsigned bit_depth_chroma_minus8; 442 unsigned nal_unit_type; 443 unsigned max_num_merge_cand; 444 unsigned temporal_id; 445 unsigned num_temporal_layers; 446 unsigned temporal_layer_pattern_index; 447 448 bool not_referenced; 449 bool is_idr; 450 bool is_even_frame; 451 bool sample_adaptive_offset_enabled_flag; 452 bool pcm_enabled_flag; 453 bool sps_temporal_mvp_enabled_flag; 454 455 rvcn_enc_session_info_t session_info; 456 rvcn_enc_task_info_t task_info; 457 rvcn_enc_session_init_t session_init; 458 rvcn_enc_layer_control_t layer_ctrl; 459 rvcn_enc_layer_select_t layer_sel; 460 rvcn_enc_h264_slice_control_t slice_ctrl; 461 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 462 rvcn_enc_h264_spec_misc_t spec_misc; 463 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 464 rvcn_enc_rate_ctl_session_init_t rc_session_init; 465 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 466 rvcn_enc_h264_encode_params_t h264_enc_params; 467 rvcn_enc_h264_deblocking_filter_t h264_deblock; 468 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 469 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 470 rvcn_enc_quality_params_t quality_params; 471 rvcn_enc_encode_context_buffer_t ctx_buf; 472 rvcn_enc_video_bitstream_buffer_t bit_buf; 473 rvcn_enc_feedback_buffer_t fb_buf; 474 rvcn_enc_intra_refresh_t intra_ref; 475 rvcn_enc_encode_params_t enc_params; 476}; 477 478struct radeon_encoder { 479 struct pipe_video_codec base; 480 481 void (*begin)(struct radeon_encoder *enc); 482 void (*encode)(struct radeon_encoder *enc); 483 void (*destroy)(struct radeon_encoder *enc); 484 void (*session_info)(struct radeon_encoder *enc); 485 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 486 void (*session_init)(struct radeon_encoder *enc); 487 void (*layer_control)(struct radeon_encoder *enc); 488 void (*layer_select)(struct radeon_encoder *enc); 489 void (*slice_control)(struct radeon_encoder *enc); 490 void (*spec_misc)(struct radeon_encoder *enc); 491 void (*rc_session_init)(struct radeon_encoder *enc); 492 void (*rc_layer_init)(struct radeon_encoder *enc); 493 void (*deblocking_filter)(struct radeon_encoder *enc); 494 void (*quality_params)(struct radeon_encoder *enc); 495 void (*nalu_sps)(struct radeon_encoder *enc); 496 void (*nalu_pps)(struct radeon_encoder *enc); 497 void (*nalu_vps)(struct radeon_encoder *enc); 498 void (*nalu_aud)(struct radeon_encoder *enc); 499 void (*nalu_sei)(struct radeon_encoder *enc); 500 void (*nalu_prefix)(struct radeon_encoder *enc); 501 void (*slice_header)(struct radeon_encoder *enc); 502 void (*ctx)(struct radeon_encoder *enc); 503 void (*bitstream)(struct radeon_encoder *enc); 504 void (*feedback)(struct radeon_encoder *enc); 505 void (*intra_refresh)(struct radeon_encoder *enc); 506 void (*rc_per_pic)(struct radeon_encoder *enc); 507 void (*encode_params)(struct radeon_encoder *enc); 508 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 509 void (*op_init)(struct radeon_encoder *enc); 510 void (*op_close)(struct radeon_encoder *enc); 511 void (*op_enc)(struct radeon_encoder *enc); 512 void (*op_init_rc)(struct radeon_encoder *enc); 513 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 514 void (*op_preset)(struct radeon_encoder *enc); 515 void (*encode_headers)(struct radeon_encoder *enc); 516 void (*input_format)(struct radeon_encoder *enc); 517 void (*output_format)(struct radeon_encoder *enc); 518 519 unsigned stream_handle; 520 521 struct pipe_screen *screen; 522 struct radeon_winsys *ws; 523 struct radeon_cmdbuf cs; 524 525 radeon_enc_get_buffer get_buffer; 526 527 struct pb_buffer *handle; 528 struct radeon_surf *luma; 529 struct radeon_surf *chroma; 530 531 struct pb_buffer *bs_handle; 532 unsigned bs_size; 533 534 unsigned cpb_num; 535 536 struct rvid_buffer *si; 537 struct rvid_buffer *fb; 538 struct rvid_buffer cpb; 539 struct radeon_enc_pic enc_pic; 540 rvcn_enc_cmd_t cmd; 541 542 unsigned alignment; 543 unsigned shifter; 544 unsigned bits_in_shifter; 545 unsigned num_zeros; 546 unsigned byte_index; 547 unsigned bits_output; 548 unsigned bits_size; 549 uint32_t total_task_size; 550 uint32_t *p_task_size; 551 552 bool emulation_prevention; 553 bool need_feedback; 554}; 555 556void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf, 557 enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset); 558 559void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set); 560 561void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte); 562 563void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte); 564 565void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, 566 unsigned int num_bits); 567 568void radeon_enc_reset(struct radeon_encoder *enc); 569 570void radeon_enc_byte_align(struct radeon_encoder *enc); 571 572void radeon_enc_flush_headers(struct radeon_encoder *enc); 573 574void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value); 575 576void radeon_enc_code_se(struct radeon_encoder *enc, int value); 577 578void radeon_enc_1_2_init(struct radeon_encoder *enc); 579 580void radeon_enc_2_0_init(struct radeon_encoder *enc); 581 582void radeon_enc_3_0_init(struct radeon_encoder *enc); 583 584#endif // _RADEON_VCN_ENC_H 585